1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __iop_spu_defs_h
3 #define __iop_spu_defs_h
6 * This file is autogenerated from
7 * file: ../../inst/io_proc/rtl/iop_spu.r
9 * last modfied: Mon Apr 11 16:08:46 2005
11 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r
12 * id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
13 * Any changes here will be lost.
15 * -*- buffer-read-only: t -*-
17 /* Main access macros */
19 #define REG_RD( scope, inst, reg ) \
20 REG_READ( reg_##scope##_##reg, \
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \
26 REG_WRITE( reg_##scope##_##reg, \
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \
32 REG_READ( reg_##scope##_##reg, \
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 (index) * STRIDE_##scope##_##reg )
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 REG_WRITE( reg_##scope##_##reg, \
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 (index) * STRIDE_##scope##_##reg, (val) )
45 #define REG_RD_INT( scope, inst, reg ) \
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
50 #define REG_WR_INT( scope, inst, reg, val ) \
51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #ifndef REG_RD_INT_VECT
55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 (index) * STRIDE_##scope##_##reg )
60 #ifndef REG_WR_INT_VECT
61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
63 (index) * STRIDE_##scope##_##reg, (val) )
67 #define REG_TYPE_CONV( type, orgtype, val ) \
68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
72 #define reg_page_size 8192
76 #define REG_ADDR( scope, inst, reg ) \
77 ( (inst) + REG_RD_ADDR_##scope##_##reg )
81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
83 (index) * STRIDE_##scope##_##reg )
86 /* C-code for register scope iop_spu */
88 #define STRIDE_iop_spu_rw_r 4
89 /* Register rw_r, scope iop_spu, type rw */
90 typedef unsigned int reg_iop_spu_rw_r
;
91 #define REG_RD_ADDR_iop_spu_rw_r 0
92 #define REG_WR_ADDR_iop_spu_rw_r 0
94 /* Register rw_seq_pc, scope iop_spu, type rw */
96 unsigned int addr
: 12;
97 unsigned int dummy1
: 20;
98 } reg_iop_spu_rw_seq_pc
;
99 #define REG_RD_ADDR_iop_spu_rw_seq_pc 64
100 #define REG_WR_ADDR_iop_spu_rw_seq_pc 64
102 /* Register rw_fsm_pc, scope iop_spu, type rw */
104 unsigned int addr
: 12;
105 unsigned int dummy1
: 20;
106 } reg_iop_spu_rw_fsm_pc
;
107 #define REG_RD_ADDR_iop_spu_rw_fsm_pc 68
108 #define REG_WR_ADDR_iop_spu_rw_fsm_pc 68
110 /* Register rw_ctrl, scope iop_spu, type rw */
112 unsigned int fsm
: 1;
114 unsigned int dummy1
: 30;
115 } reg_iop_spu_rw_ctrl
;
116 #define REG_RD_ADDR_iop_spu_rw_ctrl 72
117 #define REG_WR_ADDR_iop_spu_rw_ctrl 72
119 /* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
121 unsigned int val0
: 5;
122 unsigned int src0
: 3;
123 unsigned int val1
: 5;
124 unsigned int src1
: 3;
125 unsigned int val2
: 5;
126 unsigned int src2
: 3;
127 unsigned int val3
: 5;
128 unsigned int src3
: 3;
129 } reg_iop_spu_rw_fsm_inputs3_0
;
130 #define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76
131 #define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76
133 /* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
135 unsigned int val4
: 5;
136 unsigned int src4
: 3;
137 unsigned int val5
: 5;
138 unsigned int src5
: 3;
139 unsigned int val6
: 5;
140 unsigned int src6
: 3;
141 unsigned int val7
: 5;
142 unsigned int src7
: 3;
143 } reg_iop_spu_rw_fsm_inputs7_4
;
144 #define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80
145 #define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80
147 /* Register rw_gio_out, scope iop_spu, type rw */
148 typedef unsigned int reg_iop_spu_rw_gio_out
;
149 #define REG_RD_ADDR_iop_spu_rw_gio_out 84
150 #define REG_WR_ADDR_iop_spu_rw_gio_out 84
152 /* Register rw_bus0_out, scope iop_spu, type rw */
153 typedef unsigned int reg_iop_spu_rw_bus0_out
;
154 #define REG_RD_ADDR_iop_spu_rw_bus0_out 88
155 #define REG_WR_ADDR_iop_spu_rw_bus0_out 88
157 /* Register rw_bus1_out, scope iop_spu, type rw */
158 typedef unsigned int reg_iop_spu_rw_bus1_out
;
159 #define REG_RD_ADDR_iop_spu_rw_bus1_out 92
160 #define REG_WR_ADDR_iop_spu_rw_bus1_out 92
162 /* Register r_gio_in, scope iop_spu, type r */
163 typedef unsigned int reg_iop_spu_r_gio_in
;
164 #define REG_RD_ADDR_iop_spu_r_gio_in 96
166 /* Register r_bus0_in, scope iop_spu, type r */
167 typedef unsigned int reg_iop_spu_r_bus0_in
;
168 #define REG_RD_ADDR_iop_spu_r_bus0_in 100
170 /* Register r_bus1_in, scope iop_spu, type r */
171 typedef unsigned int reg_iop_spu_r_bus1_in
;
172 #define REG_RD_ADDR_iop_spu_r_bus1_in 104
174 /* Register rw_gio_out_set, scope iop_spu, type rw */
175 typedef unsigned int reg_iop_spu_rw_gio_out_set
;
176 #define REG_RD_ADDR_iop_spu_rw_gio_out_set 108
177 #define REG_WR_ADDR_iop_spu_rw_gio_out_set 108
179 /* Register rw_gio_out_clr, scope iop_spu, type rw */
180 typedef unsigned int reg_iop_spu_rw_gio_out_clr
;
181 #define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112
182 #define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112
184 /* Register rs_wr_stat, scope iop_spu, type rs */
196 unsigned int r10
: 1;
197 unsigned int r11
: 1;
198 unsigned int r12
: 1;
199 unsigned int r13
: 1;
200 unsigned int r14
: 1;
201 unsigned int r15
: 1;
202 unsigned int dummy1
: 16;
203 } reg_iop_spu_rs_wr_stat
;
204 #define REG_RD_ADDR_iop_spu_rs_wr_stat 116
206 /* Register r_wr_stat, scope iop_spu, type r */
218 unsigned int r10
: 1;
219 unsigned int r11
: 1;
220 unsigned int r12
: 1;
221 unsigned int r13
: 1;
222 unsigned int r14
: 1;
223 unsigned int r15
: 1;
224 unsigned int dummy1
: 16;
225 } reg_iop_spu_r_wr_stat
;
226 #define REG_RD_ADDR_iop_spu_r_wr_stat 120
228 /* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
229 typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in
;
230 #define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124
232 /* Register r_stat_in, scope iop_spu, type r */
234 unsigned int timer_grp_lo
: 4;
235 unsigned int fifo_out_last
: 1;
236 unsigned int fifo_out_rdy
: 1;
237 unsigned int fifo_out_all
: 1;
238 unsigned int fifo_in_rdy
: 1;
239 unsigned int dmc_out_all
: 1;
240 unsigned int dmc_out_dth
: 1;
241 unsigned int dmc_out_eop
: 1;
242 unsigned int dmc_out_dv
: 1;
243 unsigned int dmc_out_last
: 1;
244 unsigned int dmc_out_cmd_rq
: 1;
245 unsigned int dmc_out_cmd_rdy
: 1;
246 unsigned int pcrc_correct
: 1;
247 unsigned int timer_grp_hi
: 4;
248 unsigned int dmc_in_sth
: 1;
249 unsigned int dmc_in_full
: 1;
250 unsigned int dmc_in_cmd_rdy
: 1;
251 unsigned int spu_gio_out
: 4;
252 unsigned int sync_clk12
: 1;
253 unsigned int scrc_out_data
: 1;
254 unsigned int scrc_in_err
: 1;
255 unsigned int mc_busy
: 1;
256 unsigned int mc_owned
: 1;
257 } reg_iop_spu_r_stat_in
;
258 #define REG_RD_ADDR_iop_spu_r_stat_in 128
260 /* Register r_trigger_in, scope iop_spu, type r */
261 typedef unsigned int reg_iop_spu_r_trigger_in
;
262 #define REG_RD_ADDR_iop_spu_r_trigger_in 132
264 /* Register r_special_stat, scope iop_spu, type r */
266 unsigned int c_flag
: 1;
267 unsigned int v_flag
: 1;
268 unsigned int z_flag
: 1;
269 unsigned int n_flag
: 1;
270 unsigned int xor_bus0_r2_0
: 1;
271 unsigned int xor_bus1_r3_0
: 1;
272 unsigned int xor_bus0m_r2_0
: 1;
273 unsigned int xor_bus1m_r3_0
: 1;
274 unsigned int fsm_in0
: 1;
275 unsigned int fsm_in1
: 1;
276 unsigned int fsm_in2
: 1;
277 unsigned int fsm_in3
: 1;
278 unsigned int fsm_in4
: 1;
279 unsigned int fsm_in5
: 1;
280 unsigned int fsm_in6
: 1;
281 unsigned int fsm_in7
: 1;
282 unsigned int event0
: 1;
283 unsigned int event1
: 1;
284 unsigned int event2
: 1;
285 unsigned int event3
: 1;
286 unsigned int dummy1
: 12;
287 } reg_iop_spu_r_special_stat
;
288 #define REG_RD_ADDR_iop_spu_r_special_stat 136
290 /* Register rw_reg_access, scope iop_spu, type rw */
292 unsigned int addr
: 13;
293 unsigned int dummy1
: 3;
294 unsigned int imm_hi
: 16;
295 } reg_iop_spu_rw_reg_access
;
296 #define REG_RD_ADDR_iop_spu_rw_reg_access 140
297 #define REG_WR_ADDR_iop_spu_rw_reg_access 140
299 #define STRIDE_iop_spu_rw_event_cfg 4
300 /* Register rw_event_cfg, scope iop_spu, type rw */
302 unsigned int addr
: 12;
303 unsigned int src
: 2;
304 unsigned int eq_en
: 1;
305 unsigned int eq_inv
: 1;
306 unsigned int gt_en
: 1;
307 unsigned int gt_inv
: 1;
308 unsigned int dummy1
: 14;
309 } reg_iop_spu_rw_event_cfg
;
310 #define REG_RD_ADDR_iop_spu_rw_event_cfg 144
311 #define REG_WR_ADDR_iop_spu_rw_event_cfg 144
313 #define STRIDE_iop_spu_rw_event_mask 4
314 /* Register rw_event_mask, scope iop_spu, type rw */
315 typedef unsigned int reg_iop_spu_rw_event_mask
;
316 #define REG_RD_ADDR_iop_spu_rw_event_mask 160
317 #define REG_WR_ADDR_iop_spu_rw_event_mask 160
319 #define STRIDE_iop_spu_rw_event_val 4
320 /* Register rw_event_val, scope iop_spu, type rw */
321 typedef unsigned int reg_iop_spu_rw_event_val
;
322 #define REG_RD_ADDR_iop_spu_rw_event_val 176
323 #define REG_WR_ADDR_iop_spu_rw_event_val 176
325 /* Register rw_event_ret, scope iop_spu, type rw */
327 unsigned int addr
: 12;
328 unsigned int dummy1
: 20;
329 } reg_iop_spu_rw_event_ret
;
330 #define REG_RD_ADDR_iop_spu_rw_event_ret 192
331 #define REG_WR_ADDR_iop_spu_rw_event_ret 192
333 /* Register r_trace, scope iop_spu, type r */
335 unsigned int fsm
: 1;
337 unsigned int c_flag
: 1;
338 unsigned int v_flag
: 1;
339 unsigned int z_flag
: 1;
340 unsigned int n_flag
: 1;
341 unsigned int seq_addr
: 12;
342 unsigned int dummy1
: 2;
343 unsigned int fsm_addr
: 12;
344 } reg_iop_spu_r_trace
;
345 #define REG_RD_ADDR_iop_spu_r_trace 196
347 /* Register r_fsm_trace, scope iop_spu, type r */
349 unsigned int fsm
: 1;
351 unsigned int tmr_done
: 1;
352 unsigned int inp0
: 1;
353 unsigned int inp1
: 1;
354 unsigned int inp2
: 1;
355 unsigned int inp3
: 1;
356 unsigned int event0
: 1;
357 unsigned int event1
: 1;
358 unsigned int event2
: 1;
359 unsigned int event3
: 1;
360 unsigned int gio_out
: 8;
361 unsigned int dummy1
: 1;
362 unsigned int fsm_addr
: 12;
363 } reg_iop_spu_r_fsm_trace
;
364 #define REG_RD_ADDR_iop_spu_r_fsm_trace 200
366 #define STRIDE_iop_spu_rw_brp 4
367 /* Register rw_brp, scope iop_spu, type rw */
369 unsigned int addr
: 12;
370 unsigned int fsm
: 1;
372 unsigned int dummy1
: 18;
373 } reg_iop_spu_rw_brp
;
374 #define REG_RD_ADDR_iop_spu_rw_brp 204
375 #define REG_WR_ADDR_iop_spu_rw_brp 204
380 regk_iop_spu_attn_hi
= 0x00000005,
381 regk_iop_spu_attn_lo
= 0x00000005,
382 regk_iop_spu_attn_r0
= 0x00000000,
383 regk_iop_spu_attn_r1
= 0x00000001,
384 regk_iop_spu_attn_r10
= 0x00000002,
385 regk_iop_spu_attn_r11
= 0x00000003,
386 regk_iop_spu_attn_r12
= 0x00000004,
387 regk_iop_spu_attn_r13
= 0x00000005,
388 regk_iop_spu_attn_r14
= 0x00000006,
389 regk_iop_spu_attn_r15
= 0x00000007,
390 regk_iop_spu_attn_r2
= 0x00000002,
391 regk_iop_spu_attn_r3
= 0x00000003,
392 regk_iop_spu_attn_r4
= 0x00000004,
393 regk_iop_spu_attn_r5
= 0x00000005,
394 regk_iop_spu_attn_r6
= 0x00000006,
395 regk_iop_spu_attn_r7
= 0x00000007,
396 regk_iop_spu_attn_r8
= 0x00000000,
397 regk_iop_spu_attn_r9
= 0x00000001,
398 regk_iop_spu_c
= 0x00000000,
399 regk_iop_spu_flag
= 0x00000002,
400 regk_iop_spu_gio_in
= 0x00000000,
401 regk_iop_spu_gio_out
= 0x00000005,
402 regk_iop_spu_gio_out0
= 0x00000008,
403 regk_iop_spu_gio_out1
= 0x00000009,
404 regk_iop_spu_gio_out2
= 0x0000000a,
405 regk_iop_spu_gio_out3
= 0x0000000b,
406 regk_iop_spu_gio_out4
= 0x0000000c,
407 regk_iop_spu_gio_out5
= 0x0000000d,
408 regk_iop_spu_gio_out6
= 0x0000000e,
409 regk_iop_spu_gio_out7
= 0x0000000f,
410 regk_iop_spu_n
= 0x00000003,
411 regk_iop_spu_no
= 0x00000000,
412 regk_iop_spu_r0
= 0x00000008,
413 regk_iop_spu_r1
= 0x00000009,
414 regk_iop_spu_r10
= 0x0000000a,
415 regk_iop_spu_r11
= 0x0000000b,
416 regk_iop_spu_r12
= 0x0000000c,
417 regk_iop_spu_r13
= 0x0000000d,
418 regk_iop_spu_r14
= 0x0000000e,
419 regk_iop_spu_r15
= 0x0000000f,
420 regk_iop_spu_r2
= 0x0000000a,
421 regk_iop_spu_r3
= 0x0000000b,
422 regk_iop_spu_r4
= 0x0000000c,
423 regk_iop_spu_r5
= 0x0000000d,
424 regk_iop_spu_r6
= 0x0000000e,
425 regk_iop_spu_r7
= 0x0000000f,
426 regk_iop_spu_r8
= 0x00000008,
427 regk_iop_spu_r9
= 0x00000009,
428 regk_iop_spu_reg_hi
= 0x00000002,
429 regk_iop_spu_reg_lo
= 0x00000002,
430 regk_iop_spu_rw_brp_default
= 0x00000000,
431 regk_iop_spu_rw_brp_size
= 0x00000004,
432 regk_iop_spu_rw_ctrl_default
= 0x00000000,
433 regk_iop_spu_rw_event_cfg_size
= 0x00000004,
434 regk_iop_spu_rw_event_mask_size
= 0x00000004,
435 regk_iop_spu_rw_event_val_size
= 0x00000004,
436 regk_iop_spu_rw_gio_out_default
= 0x00000000,
437 regk_iop_spu_rw_r_size
= 0x00000010,
438 regk_iop_spu_rw_reg_access_default
= 0x00000000,
439 regk_iop_spu_stat_in
= 0x00000002,
440 regk_iop_spu_statin_hi
= 0x00000004,
441 regk_iop_spu_statin_lo
= 0x00000004,
442 regk_iop_spu_trig
= 0x00000003,
443 regk_iop_spu_trigger
= 0x00000006,
444 regk_iop_spu_v
= 0x00000001,
445 regk_iop_spu_wsts_gioout_spec
= 0x00000001,
446 regk_iop_spu_xor
= 0x00000003,
447 regk_iop_spu_xor_bus0_r2_0
= 0x00000000,
448 regk_iop_spu_xor_bus0m_r2_0
= 0x00000002,
449 regk_iop_spu_xor_bus1_r3_0
= 0x00000001,
450 regk_iop_spu_xor_bus1m_r3_0
= 0x00000003,
451 regk_iop_spu_yes
= 0x00000001,
452 regk_iop_spu_z
= 0x00000002
454 #endif /* __iop_spu_defs_h */