1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This file is autogenerated from
7 * file: ../../inst/syncser/rtl/sser_regs.r
8 * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp
9 * last modfied: Mon Apr 11 16:09:48 2005
11 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r
12 * id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
13 * Any changes here will be lost.
15 * -*- buffer-read-only: t -*-
17 /* Main access macros */
19 #define REG_RD( scope, inst, reg ) \
20 REG_READ( reg_##scope##_##reg, \
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \
26 REG_WRITE( reg_##scope##_##reg, \
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \
32 REG_READ( reg_##scope##_##reg, \
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 (index) * STRIDE_##scope##_##reg )
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 REG_WRITE( reg_##scope##_##reg, \
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 (index) * STRIDE_##scope##_##reg, (val) )
45 #define REG_RD_INT( scope, inst, reg ) \
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
50 #define REG_WR_INT( scope, inst, reg, val ) \
51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #ifndef REG_RD_INT_VECT
55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 (index) * STRIDE_##scope##_##reg )
60 #ifndef REG_WR_INT_VECT
61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
63 (index) * STRIDE_##scope##_##reg, (val) )
67 #define REG_TYPE_CONV( type, orgtype, val ) \
68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
72 #define reg_page_size 8192
76 #define REG_ADDR( scope, inst, reg ) \
77 ( (inst) + REG_RD_ADDR_##scope##_##reg )
81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
83 (index) * STRIDE_##scope##_##reg )
86 /* C-code for register scope sser */
88 /* Register rw_cfg, scope sser, type rw */
90 unsigned int clk_div
: 16;
91 unsigned int base_freq
: 3;
92 unsigned int gate_clk
: 1;
93 unsigned int clkgate_ctrl
: 1;
94 unsigned int clkgate_in
: 1;
95 unsigned int clk_dir
: 1;
96 unsigned int clk_od_mode
: 1;
97 unsigned int out_clk_pol
: 1;
98 unsigned int out_clk_src
: 2;
99 unsigned int clk_in_sel
: 1;
100 unsigned int hold_pol
: 1;
101 unsigned int prepare
: 1;
103 unsigned int dummy1
: 1;
105 #define REG_RD_ADDR_sser_rw_cfg 0
106 #define REG_WR_ADDR_sser_rw_cfg 0
108 /* Register rw_frm_cfg, scope sser, type rw */
110 unsigned int wordrate
: 10;
111 unsigned int rec_delay
: 3;
112 unsigned int tr_delay
: 3;
113 unsigned int early_wend
: 1;
114 unsigned int level
: 2;
115 unsigned int type
: 1;
116 unsigned int clk_pol
: 1;
117 unsigned int fr_in_rxclk
: 1;
118 unsigned int clk_src
: 1;
119 unsigned int out_off
: 1;
120 unsigned int out_on
: 1;
121 unsigned int frame_pin_dir
: 1;
122 unsigned int frame_pin_use
: 2;
123 unsigned int status_pin_dir
: 1;
124 unsigned int status_pin_use
: 2;
125 unsigned int dummy1
: 1;
126 } reg_sser_rw_frm_cfg
;
127 #define REG_RD_ADDR_sser_rw_frm_cfg 4
128 #define REG_WR_ADDR_sser_rw_frm_cfg 4
130 /* Register rw_tr_cfg, scope sser, type rw */
132 unsigned int tr_en
: 1;
133 unsigned int stop
: 1;
134 unsigned int urun_stop
: 1;
135 unsigned int eop_stop
: 1;
136 unsigned int sample_size
: 6;
137 unsigned int sh_dir
: 1;
138 unsigned int clk_pol
: 1;
139 unsigned int clk_src
: 1;
140 unsigned int use_dma
: 1;
141 unsigned int mode
: 2;
142 unsigned int frm_src
: 1;
143 unsigned int use60958
: 1;
144 unsigned int iec60958_ckdiv
: 2;
145 unsigned int rate_ctrl
: 1;
146 unsigned int use_md
: 1;
147 unsigned int dual_i2s
: 1;
148 unsigned int data_pin_use
: 2;
149 unsigned int od_mode
: 1;
150 unsigned int bulk_wspace
: 2;
151 unsigned int dummy1
: 4;
152 } reg_sser_rw_tr_cfg
;
153 #define REG_RD_ADDR_sser_rw_tr_cfg 8
154 #define REG_WR_ADDR_sser_rw_tr_cfg 8
156 /* Register rw_rec_cfg, scope sser, type rw */
158 unsigned int rec_en
: 1;
159 unsigned int force_eop
: 1;
160 unsigned int stop
: 1;
161 unsigned int orun_stop
: 1;
162 unsigned int eop_stop
: 1;
163 unsigned int sample_size
: 6;
164 unsigned int sh_dir
: 1;
165 unsigned int clk_pol
: 1;
166 unsigned int clk_src
: 1;
167 unsigned int use_dma
: 1;
168 unsigned int mode
: 2;
169 unsigned int frm_src
: 2;
170 unsigned int use60958
: 1;
171 unsigned int iec60958_ui_len
: 5;
172 unsigned int slave2_en
: 1;
173 unsigned int slave3_en
: 1;
174 unsigned int fifo_thr
: 2;
175 unsigned int dummy1
: 3;
176 } reg_sser_rw_rec_cfg
;
177 #define REG_RD_ADDR_sser_rw_rec_cfg 12
178 #define REG_WR_ADDR_sser_rw_rec_cfg 12
180 /* Register rw_tr_data, scope sser, type rw */
182 unsigned int data
: 16;
184 unsigned int dummy1
: 15;
185 } reg_sser_rw_tr_data
;
186 #define REG_RD_ADDR_sser_rw_tr_data 16
187 #define REG_WR_ADDR_sser_rw_tr_data 16
189 /* Register r_rec_data, scope sser, type r */
191 unsigned int data
: 16;
193 unsigned int ext_clk
: 1;
194 unsigned int status_in
: 1;
195 unsigned int frame_in
: 1;
196 unsigned int din
: 1;
197 unsigned int data_in
: 1;
198 unsigned int clk_in
: 1;
199 unsigned int dummy1
: 9;
200 } reg_sser_r_rec_data
;
201 #define REG_RD_ADDR_sser_r_rec_data 20
203 /* Register rw_extra, scope sser, type rw */
205 unsigned int clkoff_cycles
: 20;
206 unsigned int clkoff_en
: 1;
207 unsigned int clkon_en
: 1;
208 unsigned int dout_delay
: 5;
209 unsigned int dummy1
: 5;
211 #define REG_RD_ADDR_sser_rw_extra 24
212 #define REG_WR_ADDR_sser_rw_extra 24
214 /* Register rw_intr_mask, scope sser, type rw */
216 unsigned int trdy
: 1;
217 unsigned int rdav
: 1;
218 unsigned int tidle
: 1;
219 unsigned int rstop
: 1;
220 unsigned int urun
: 1;
221 unsigned int orun
: 1;
222 unsigned int md_rec
: 1;
223 unsigned int md_sent
: 1;
224 unsigned int r958err
: 1;
225 unsigned int dummy1
: 23;
226 } reg_sser_rw_intr_mask
;
227 #define REG_RD_ADDR_sser_rw_intr_mask 28
228 #define REG_WR_ADDR_sser_rw_intr_mask 28
230 /* Register rw_ack_intr, scope sser, type rw */
232 unsigned int trdy
: 1;
233 unsigned int rdav
: 1;
234 unsigned int tidle
: 1;
235 unsigned int rstop
: 1;
236 unsigned int urun
: 1;
237 unsigned int orun
: 1;
238 unsigned int md_rec
: 1;
239 unsigned int md_sent
: 1;
240 unsigned int r958err
: 1;
241 unsigned int dummy1
: 23;
242 } reg_sser_rw_ack_intr
;
243 #define REG_RD_ADDR_sser_rw_ack_intr 32
244 #define REG_WR_ADDR_sser_rw_ack_intr 32
246 /* Register r_intr, scope sser, type r */
248 unsigned int trdy
: 1;
249 unsigned int rdav
: 1;
250 unsigned int tidle
: 1;
251 unsigned int rstop
: 1;
252 unsigned int urun
: 1;
253 unsigned int orun
: 1;
254 unsigned int md_rec
: 1;
255 unsigned int md_sent
: 1;
256 unsigned int r958err
: 1;
257 unsigned int dummy1
: 23;
259 #define REG_RD_ADDR_sser_r_intr 36
261 /* Register r_masked_intr, scope sser, type r */
263 unsigned int trdy
: 1;
264 unsigned int rdav
: 1;
265 unsigned int tidle
: 1;
266 unsigned int rstop
: 1;
267 unsigned int urun
: 1;
268 unsigned int orun
: 1;
269 unsigned int md_rec
: 1;
270 unsigned int md_sent
: 1;
271 unsigned int r958err
: 1;
272 unsigned int dummy1
: 23;
273 } reg_sser_r_masked_intr
;
274 #define REG_RD_ADDR_sser_r_masked_intr 40
279 regk_sser_both
= 0x00000002,
280 regk_sser_bulk
= 0x00000001,
281 regk_sser_clk100
= 0x00000000,
282 regk_sser_clk_in
= 0x00000000,
283 regk_sser_const0
= 0x00000003,
284 regk_sser_dout
= 0x00000002,
285 regk_sser_edge
= 0x00000000,
286 regk_sser_ext
= 0x00000001,
287 regk_sser_ext_clk
= 0x00000001,
288 regk_sser_f100
= 0x00000000,
289 regk_sser_f29_493
= 0x00000004,
290 regk_sser_f32
= 0x00000005,
291 regk_sser_f32_768
= 0x00000006,
292 regk_sser_frm
= 0x00000003,
293 regk_sser_gio0
= 0x00000000,
294 regk_sser_gio1
= 0x00000001,
295 regk_sser_hispeed
= 0x00000001,
296 regk_sser_hold
= 0x00000002,
297 regk_sser_in
= 0x00000000,
298 regk_sser_inf
= 0x00000003,
299 regk_sser_intern
= 0x00000000,
300 regk_sser_intern_clk
= 0x00000001,
301 regk_sser_intern_tb
= 0x00000000,
302 regk_sser_iso
= 0x00000000,
303 regk_sser_level
= 0x00000001,
304 regk_sser_lospeed
= 0x00000000,
305 regk_sser_lsbfirst
= 0x00000000,
306 regk_sser_msbfirst
= 0x00000001,
307 regk_sser_neg
= 0x00000001,
308 regk_sser_neg_lo
= 0x00000000,
309 regk_sser_no
= 0x00000000,
310 regk_sser_no_clk
= 0x00000007,
311 regk_sser_nojitter
= 0x00000002,
312 regk_sser_out
= 0x00000001,
313 regk_sser_pos
= 0x00000000,
314 regk_sser_pos_hi
= 0x00000001,
315 regk_sser_rec
= 0x00000000,
316 regk_sser_rw_cfg_default
= 0x00000000,
317 regk_sser_rw_extra_default
= 0x00000000,
318 regk_sser_rw_frm_cfg_default
= 0x00000000,
319 regk_sser_rw_intr_mask_default
= 0x00000000,
320 regk_sser_rw_rec_cfg_default
= 0x00000000,
321 regk_sser_rw_tr_cfg_default
= 0x01800000,
322 regk_sser_rw_tr_data_default
= 0x00000000,
323 regk_sser_thr16
= 0x00000001,
324 regk_sser_thr32
= 0x00000002,
325 regk_sser_thr8
= 0x00000000,
326 regk_sser_tr
= 0x00000001,
327 regk_sser_ts_out
= 0x00000003,
328 regk_sser_tx_bulk
= 0x00000002,
329 regk_sser_wiresave
= 0x00000002,
330 regk_sser_yes
= 0x00000001
332 #endif /* __sser_defs_h */