arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __iop_sap_out_defs_h
   3 #define __iop_sap_out_defs_h
   4
   5 /*
   6  * This file is autogenerated from
   7  *   file:           iop_sap_out.r
   8  *
   9  *   by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r
  10  * Any changes here will be lost.
  11  *
  12  * -*- buffer-read-only: t -*-
  13  */
  14 /* Main access macros */
  15 #ifndef REG_RD
  16 #define REG_RD( scope, inst, reg ) \
  17   REG_READ( reg_##scope##_##reg, \
  18             (inst) + REG_RD_ADDR_##scope##_##reg )
  19 #endif
  20
  21 #ifndef REG_WR
  22 #define REG_WR( scope, inst, reg, val ) \
  23   REG_WRITE( reg_##scope##_##reg, \
  24              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  25 #endif
  26
  27 #ifndef REG_RD_VECT
  28 #define REG_RD_VECT( scope, inst, reg, index ) \
  29   REG_READ( reg_##scope##_##reg, \
  30             (inst) + REG_RD_ADDR_##scope##_##reg + \
  31             (index) * STRIDE_##scope##_##reg )
  32 #endif
  33
  34 #ifndef REG_WR_VECT
  35 #define REG_WR_VECT( scope, inst, reg, index, val ) \
  36   REG_WRITE( reg_##scope##_##reg, \
  37              (inst) + REG_WR_ADDR_##scope##_##reg + \
  38              (index) * STRIDE_##scope##_##reg, (val) )
  39 #endif
  40
  41 #ifndef REG_RD_INT
  42 #define REG_RD_INT( scope, inst, reg ) \
  43   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  44 #endif
  45
  46 #ifndef REG_WR_INT
  47 #define REG_WR_INT( scope, inst, reg, val ) \
  48   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  49 #endif
  50
  51 #ifndef REG_RD_INT_VECT
  52 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
  53   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  54             (index) * STRIDE_##scope##_##reg )
  55 #endif
  56
  57 #ifndef REG_WR_INT_VECT
  58 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  59   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  60              (index) * STRIDE_##scope##_##reg, (val) )
  61 #endif
  62
  63 #ifndef REG_TYPE_CONV
  64 #define REG_TYPE_CONV( type, orgtype, val ) \
  65   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  66 #endif
  67
  68 #ifndef reg_page_size
  69 #define reg_page_size 8192
  70 #endif
  71
  72 #ifndef REG_ADDR
  73 #define REG_ADDR( scope, inst, reg ) \
  74   ( (inst) + REG_RD_ADDR_##scope##_##reg )
  75 #endif
  76
  77 #ifndef REG_ADDR_VECT
  78 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  79   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  80     (index) * STRIDE_##scope##_##reg )
  81 #endif
  82
  83 /* C-code for register scope iop_sap_out */
  84
  85 /* Register rw_gen_gated, scope iop_sap_out, type rw */
  86 typedef struct {
  87   unsigned int clk0_src       : 2;
  88   unsigned int clk0_gate_src  : 2;
  89   unsigned int clk0_force_src : 3;
  90   unsigned int clk1_src       : 2;
  91   unsigned int clk1_gate_src  : 2;
  92   unsigned int clk1_force_src : 3;
  93   unsigned int dummy1         : 18;
  94 } reg_iop_sap_out_rw_gen_gated;
  95 #define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0
  96 #define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0
  97
  98 /* Register rw_bus, scope iop_sap_out, type rw */
  99 typedef struct {
 100   unsigned int byte0_clk_sel   : 2;
 101   unsigned int byte0_clk_ext   : 2;
 102   unsigned int byte0_gated_clk : 1;
 103   unsigned int byte0_clk_inv   : 1;
 104   unsigned int byte0_delay     : 1;
 105   unsigned int byte1_clk_sel   : 2;
 106   unsigned int byte1_clk_ext   : 2;
 107   unsigned int byte1_gated_clk : 1;
 108   unsigned int byte1_clk_inv   : 1;
 109   unsigned int byte1_delay     : 1;
 110   unsigned int byte2_clk_sel   : 2;
 111   unsigned int byte2_clk_ext   : 2;
 112   unsigned int byte2_gated_clk : 1;
 113   unsigned int byte2_clk_inv   : 1;
 114   unsigned int byte2_delay     : 1;
 115   unsigned int byte3_clk_sel   : 2;
 116   unsigned int byte3_clk_ext   : 2;
 117   unsigned int byte3_gated_clk : 1;
 118   unsigned int byte3_clk_inv   : 1;
 119   unsigned int byte3_delay     : 1;
 120   unsigned int dummy1          : 4;
 121 } reg_iop_sap_out_rw_bus;
 122 #define REG_RD_ADDR_iop_sap_out_rw_bus 4
 123 #define REG_WR_ADDR_iop_sap_out_rw_bus 4
 124
 125 /* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
 126 typedef struct {
 127   unsigned int byte0_clk_sel   : 2;
 128   unsigned int byte0_clk_ext   : 2;
 129   unsigned int byte0_gated_clk : 1;
 130   unsigned int byte0_clk_inv   : 1;
 131   unsigned int byte0_delay     : 1;
 132   unsigned int byte0_logic     : 2;
 133   unsigned int byte0_logic_src : 2;
 134   unsigned int byte1_clk_sel   : 2;
 135   unsigned int byte1_clk_ext   : 2;
 136   unsigned int byte1_gated_clk : 1;
 137   unsigned int byte1_clk_inv   : 1;
 138   unsigned int byte1_delay     : 1;
 139   unsigned int byte1_logic     : 2;
 140   unsigned int byte1_logic_src : 2;
 141   unsigned int dummy1          : 10;
 142 } reg_iop_sap_out_rw_bus_lo_oe;
 143 #define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8
 144 #define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8
 145
 146 /* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
 147 typedef struct {
 148   unsigned int byte2_clk_sel   : 2;
 149   unsigned int byte2_clk_ext   : 2;
 150   unsigned int byte2_gated_clk : 1;
 151   unsigned int byte2_clk_inv   : 1;
 152   unsigned int byte2_delay     : 1;
 153   unsigned int byte2_logic     : 2;
 154   unsigned int byte2_logic_src : 2;
 155   unsigned int byte3_clk_sel   : 2;
 156   unsigned int byte3_clk_ext   : 2;
 157   unsigned int byte3_gated_clk : 1;
 158   unsigned int byte3_clk_inv   : 1;
 159   unsigned int byte3_delay     : 1;
 160   unsigned int byte3_logic     : 2;
 161   unsigned int byte3_logic_src : 2;
 162   unsigned int dummy1          : 10;
 163 } reg_iop_sap_out_rw_bus_hi_oe;
 164 #define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12
 165 #define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12
 166
 167 #define STRIDE_iop_sap_out_rw_gio 4
 168 /* Register rw_gio, scope iop_sap_out, type rw */
 169 typedef struct {
 170   unsigned int out_clk_sel   : 3;
 171   unsigned int out_clk_ext   : 2;
 172   unsigned int out_gated_clk : 1;
 173   unsigned int out_clk_inv   : 1;
 174   unsigned int out_delay     : 1;
 175   unsigned int out_logic     : 2;
 176   unsigned int out_logic_src : 2;
 177   unsigned int oe_clk_sel    : 3;
 178   unsigned int oe_clk_ext    : 2;
 179   unsigned int oe_gated_clk  : 1;
 180   unsigned int oe_clk_inv    : 1;
 181   unsigned int oe_delay      : 1;
 182   unsigned int oe_logic      : 2;
 183   unsigned int oe_logic_src  : 2;
 184   unsigned int dummy1        : 8;
 185 } reg_iop_sap_out_rw_gio;
 186 #define REG_RD_ADDR_iop_sap_out_rw_gio 16
 187 #define REG_WR_ADDR_iop_sap_out_rw_gio 16
 188
 189
 190 /* Constants */
 191 enum {
 192   regk_iop_sap_out_always                  = 0x00000001,
 193   regk_iop_sap_out_and                     = 0x00000002,
 194   regk_iop_sap_out_clk0                    = 0x00000000,
 195   regk_iop_sap_out_clk1                    = 0x00000001,
 196   regk_iop_sap_out_clk12                   = 0x00000004,
 197   regk_iop_sap_out_clk200                  = 0x00000000,
 198   regk_iop_sap_out_ext                     = 0x00000002,
 199   regk_iop_sap_out_gated                   = 0x00000003,
 200   regk_iop_sap_out_gio0                    = 0x00000000,
 201   regk_iop_sap_out_gio1                    = 0x00000000,
 202   regk_iop_sap_out_gio16                   = 0x00000002,
 203   regk_iop_sap_out_gio17                   = 0x00000002,
 204   regk_iop_sap_out_gio24                   = 0x00000003,
 205   regk_iop_sap_out_gio25                   = 0x00000003,
 206   regk_iop_sap_out_gio8                    = 0x00000001,
 207   regk_iop_sap_out_gio9                    = 0x00000001,
 208   regk_iop_sap_out_gio_out10               = 0x00000005,
 209   regk_iop_sap_out_gio_out18               = 0x00000006,
 210   regk_iop_sap_out_gio_out2                = 0x00000004,
 211   regk_iop_sap_out_gio_out26               = 0x00000007,
 212   regk_iop_sap_out_inv                     = 0x00000001,
 213   regk_iop_sap_out_nand                    = 0x00000003,
 214   regk_iop_sap_out_no                      = 0x00000000,
 215   regk_iop_sap_out_none                    = 0x00000000,
 216   regk_iop_sap_out_one                     = 0x00000001,
 217   regk_iop_sap_out_rw_bus_default          = 0x00000000,
 218   regk_iop_sap_out_rw_bus_hi_oe_default    = 0x00000000,
 219   regk_iop_sap_out_rw_bus_lo_oe_default    = 0x00000000,
 220   regk_iop_sap_out_rw_gen_gated_default    = 0x00000000,
 221   regk_iop_sap_out_rw_gio_default          = 0x00000000,
 222   regk_iop_sap_out_rw_gio_size             = 0x00000020,
 223   regk_iop_sap_out_spu_gio6                = 0x00000002,
 224   regk_iop_sap_out_spu_gio7                = 0x00000003,
 225   regk_iop_sap_out_timer_grp0_tmr2         = 0x00000000,
 226   regk_iop_sap_out_timer_grp0_tmr3         = 0x00000001,
 227   regk_iop_sap_out_timer_grp1_tmr2         = 0x00000002,
 228   regk_iop_sap_out_timer_grp1_tmr3         = 0x00000003,
 229   regk_iop_sap_out_tmr200                  = 0x00000001,
 230   regk_iop_sap_out_yes                     = 0x00000001
 231 };
 232 #endif /* __iop_sap_out_defs_h */