1 /* SPDX-License-Identifier: GPL-2.0 */
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
4 #ifndef __ASM_CSKY_ENTRY_H
5 #define __ASM_CSKY_ENTRY_H
8 #include <abi/regdef.h>
22 .macro SAVE_ALL epc_inc
54 #ifdef CONFIG_CPU_HAS_HILO
78 #ifdef CONFIG_CPU_HAS_HILO
103 .macro SAVE_REGS_FTRACE
125 #ifdef CONFIG_CPU_HAS_HILO
136 .macro RESTORE_REGS_FTRACE
141 #ifdef CONFIG_CPU_HAS_HILO
163 .macro SAVE_SWITCH_STACK
174 #ifdef CONFIG_CPU_HAS_HILO
185 .macro RESTORE_SWITCH_STACK
186 #ifdef CONFIG_CPU_HAS_HILO
207 /* MMU registers operators. */
237 /* Init psr and enable ee */
238 lrw r6
, DEFAULT_PSR_VALUE
242 /* Invalid I/Dcache BTB BHT */
248 /* Invalid all TLB */
250 mtcr r6
, cr
<8, 15> /* Set MCIR */
252 /* Check MMU on/off */
257 /* MMU off: setup mapping tlb entry */
259 mtcr r6
, cr
<6, 15> /* Set MPR with 4K page size */
261 grs r6
, 1f
/* Get current pa by PC */
262 bmaski r7
, (PAGE_SHIFT
+ 1) /* r7 = 0x1fff */
264 mtcr r6
, cr
<4, 15> /* Set MEH */
269 mtcr r8
, cr
<2, 15> /* Set MEL0 */
272 mtcr r8
, cr
<3, 15> /* Set MEL1 */
275 mtcr r8
, cr
<8, 15> /* Set MCIR to write TLB */
280 * MMU on: use origin MSA value from bootloader
282 * cr<30/31, 15> MSA register format:
283 * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
284 * BA Reserved SH WA B SO SEC C D V
286 mfcr r6
, cr
<30, 15> /* Get MSA0 */
291 mtcr r6
, cr
<30, 15> /* Set MSA0 */
294 mtcr r6
, cr
<31, 15> /* Clr MSA1 */
301 jmpi
3f
/* jump to va */
305 .macro ANDI_R3 rx
, imm
307 andi
\rx
, (\imm
>> 3)
309 #endif /* __ASM_CSKY_ENTRY_H */