arch/m68k/cpu/mcf52x2/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2003
   4  * Josef Baumgartner <josef.baumgartner@telex.de>
   5  *
   6  * MCF5282 additionals
   7  * (C) Copyright 2005
   8  * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
   9  *
  10  * MCF5275 additions
  11  * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  12  *
  13  * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
  14  */
  15
  16 #include <common.h>
  17 #include <init.h>
  18 #include <net.h>
  19 #include <vsprintf.h>
  20 #include <watchdog.h>
  21 #include <command.h>
  22 #include <asm/immap.h>
  23 #include <asm/io.h>
  24 #include <netdev.h>
  25 #include "cpu.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifdef  CONFIG_M5208
  30 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  31 {
  32         rcm_t *rcm = (rcm_t *)(MMAP_RCM);
  33
  34         udelay(1000);
  35
  36         out_8(&rcm->rcr, RCM_RCR_SOFTRST);
  37
  38         /* we don't return! */
  39         return 0;
  40 };
  41
  42 #if defined(CONFIG_DISPLAY_CPUINFO)
  43 int print_cpuinfo(void)
  44 {
  45         char buf1[32], buf2[32];
  46
  47         printf("CPU:   Freescale Coldfire MCF5208\n"
  48                "       CPU CLK %s MHz BUS CLK %s MHz\n",
  49                strmhz(buf1, gd->cpu_clk),
  50                strmhz(buf2, gd->bus_clk));
  51         return 0;
  52 };
  53 #endif /* CONFIG_DISPLAY_CPUINFO */
  54
  55 #if defined(CONFIG_WATCHDOG)
  56 /* Called by macro WATCHDOG_RESET */
  57 void watchdog_reset(void)
  58 {
  59         wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  60
  61         out_be16(&wdt->sr, 0x5555);
  62         out_be16(&wdt->sr, 0xaaaa);
  63 }
  64
  65 int watchdog_disable(void)
  66 {
  67         wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  68
  69         /* reset watchdog counter */
  70         out_be16(&wdt->sr, 0x5555);
  71         out_be16(&wdt->sr, 0xaaaa);
  72         /* disable watchdog timer */
  73         out_be16(&wdt->cr, 0);
  74
  75         puts("WATCHDOG:disabled\n");
  76         return (0);
  77 }
  78
  79 int watchdog_init(void)
  80 {
  81         wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  82
  83         /* disable watchdog */
  84         out_be16(&wdt->cr, 0);
  85
  86         /* set timeout and enable watchdog */
  87         out_be16(&wdt->mr,
  88                 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
  89
  90         /* reset watchdog counter */
  91         out_be16(&wdt->sr, 0x5555);
  92         out_be16(&wdt->sr, 0xaaaa);
  93
  94         puts("WATCHDOG:enabled\n");
  95         return (0);
  96 }
  97 #endif                          /* #ifdef CONFIG_WATCHDOG */
  98 #endif                          /* #ifdef CONFIG_M5208 */
  99
 100 #ifdef  CONFIG_M5271
 101 #if defined(CONFIG_DISPLAY_CPUINFO)
 102 /*
 103  * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
 104  * determine which one we are running on, based on the Chip Identification
 105  * Register (CIR).
 106  */
 107 int print_cpuinfo(void)
 108 {
 109         char buf[32];
 110         unsigned short cir;     /* Chip Identification Register */
 111         unsigned short pin;     /* Part identification number */
 112         unsigned char prn;      /* Part revision number */
 113         char *cpu_model;
 114
 115         cir = mbar_readShort(MCF_CCM_CIR);
 116         pin = cir >> MCF_CCM_CIR_PIN_LEN;
 117         prn = cir & MCF_CCM_CIR_PRN_MASK;
 118
 119         switch (pin) {
 120         case MCF_CCM_CIR_PIN_MCF5270:
 121                 cpu_model = "5270";
 122                 break;
 123         case MCF_CCM_CIR_PIN_MCF5271:
 124                 cpu_model = "5271";
 125                 break;
 126         default:
 127                 cpu_model = NULL;
 128                 break;
 129         }
 130
 131         if (cpu_model)
 132                 printf("CPU:   Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
 133                        cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
 134         else
 135                 printf("CPU:   Unknown - Freescale ColdFire MCF5271 family"
 136                        " (PIN: 0x%x) rev. %hu, at %s MHz\n",
 137                        pin, prn, strmhz(buf, CONFIG_SYS_CLK));
 138
 139         return 0;
 140 }
 141 #endif /* CONFIG_DISPLAY_CPUINFO */
 142
 143 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 144 {
 145         /* Call the board specific reset actions first. */
 146         if(board_reset) {
 147                 board_reset();
 148         }
 149
 150         mbar_writeByte(MCF_RCM_RCR,
 151                        MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
 152         return 0;
 153 };
 154
 155 #if defined(CONFIG_WATCHDOG)
 156 void watchdog_reset(void)
 157 {
 158         mbar_writeShort(MCF_WTM_WSR, 0x5555);
 159         mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
 160 }
 161
 162 int watchdog_disable(void)
 163 {
 164         mbar_writeShort(MCF_WTM_WCR, 0);
 165         return (0);
 166 }
 167
 168 int watchdog_init(void)
 169 {
 170         mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
 171         return (0);
 172 }
 173 #endif                          /* #ifdef CONFIG_WATCHDOG */
 174
 175 #endif
 176
 177 #ifdef  CONFIG_M5272
 178 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 179 {
 180         wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 181
 182         out_be16(&wdp->wdog_wrrr, 0);
 183         udelay(1000);
 184
 185         /* enable watchdog, set timeout to 0 and wait */
 186         out_be16(&wdp->wdog_wrrr, 1);
 187         while (1) ;
 188
 189         /* we don't return! */
 190         return 0;
 191 };
 192
 193 #if defined(CONFIG_DISPLAY_CPUINFO)
 194 int print_cpuinfo(void)
 195 {
 196         sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
 197         uchar msk;
 198         char *suf;
 199
 200         puts("CPU:   ");
 201         msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
 202         switch (msk) {
 203         case 0x2:
 204                 suf = "1K75N";
 205                 break;
 206         case 0x4:
 207                 suf = "3K75N";
 208                 break;
 209         default:
 210                 suf = NULL;
 211                 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
 212                 break;
 213         }
 214
 215         if (suf)
 216                 printf("Freescale MCF5272 %s\n", suf);
 217         return 0;
 218 };
 219 #endif /* CONFIG_DISPLAY_CPUINFO */
 220
 221 #if defined(CONFIG_WATCHDOG)
 222 /* Called by macro WATCHDOG_RESET */
 223 void watchdog_reset(void)
 224 {
 225         wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 226
 227         out_be16(&wdt->wdog_wcr, 0);
 228 }
 229
 230 int watchdog_disable(void)
 231 {
 232         wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 233
 234         /* reset watchdog counter */
 235         out_be16(&wdt->wdog_wcr, 0);
 236         /* disable watchdog interrupt */
 237         out_be16(&wdt->wdog_wirr, 0);
 238         /* disable watchdog timer */
 239         out_be16(&wdt->wdog_wrrr, 0);
 240
 241         puts("WATCHDOG:disabled\n");
 242         return (0);
 243 }
 244
 245 int watchdog_init(void)
 246 {
 247         wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 248
 249         /* disable watchdog interrupt */
 250         out_be16(&wdt->wdog_wirr, 0);
 251
 252         /* set timeout and enable watchdog */
 253         out_be16(&wdt->wdog_wrrr,
 254                 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
 255
 256         /* reset watchdog counter */
 257         out_be16(&wdt->wdog_wcr, 0);
 258
 259         puts("WATCHDOG:enabled\n");
 260         return (0);
 261 }
 262 #endif                          /* #ifdef CONFIG_WATCHDOG */
 263
 264 #endif                          /* #ifdef CONFIG_M5272 */
 265
 266 #ifdef  CONFIG_M5275
 267 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 268 {
 269         rcm_t *rcm = (rcm_t *)(MMAP_RCM);
 270
 271         udelay(1000);
 272
 273         out_8(&rcm->rcr, RCM_RCR_SOFTRST);
 274
 275         /* we don't return! */
 276         return 0;
 277 };
 278
 279 #if defined(CONFIG_DISPLAY_CPUINFO)
 280 int print_cpuinfo(void)
 281 {
 282         char buf[32];
 283
 284         printf("CPU:   Freescale Coldfire MCF5275 at %s MHz\n",
 285                         strmhz(buf, CONFIG_SYS_CLK));
 286         return 0;
 287 };
 288 #endif /* CONFIG_DISPLAY_CPUINFO */
 289
 290 #if defined(CONFIG_WATCHDOG)
 291 /* Called by macro WATCHDOG_RESET */
 292 void watchdog_reset(void)
 293 {
 294         wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 295
 296         out_be16(&wdt->wsr, 0x5555);
 297         out_be16(&wdt->wsr, 0xaaaa);
 298 }
 299
 300 int watchdog_disable(void)
 301 {
 302         wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 303
 304         /* reset watchdog counter */
 305         out_be16(&wdt->wsr, 0x5555);
 306         out_be16(&wdt->wsr, 0xaaaa);
 307
 308         /* disable watchdog timer */
 309         out_be16(&wdt->wcr, 0);
 310
 311         puts("WATCHDOG:disabled\n");
 312         return (0);
 313 }
 314
 315 int watchdog_init(void)
 316 {
 317         wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 318
 319         /* disable watchdog */
 320         out_be16(&wdt->wcr, 0);
 321
 322         /* set timeout and enable watchdog */
 323         out_be16(&wdt->wmr,
 324                 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
 325
 326         /* reset watchdog counter */
 327         out_be16(&wdt->wsr, 0x5555);
 328         out_be16(&wdt->wsr, 0xaaaa);
 329
 330         puts("WATCHDOG:enabled\n");
 331         return (0);
 332 }
 333 #endif                          /* #ifdef CONFIG_WATCHDOG */
 334
 335 #endif                          /* #ifdef CONFIG_M5275 */
 336
 337 #ifdef  CONFIG_M5282
 338 #if defined(CONFIG_DISPLAY_CPUINFO)
 339 int print_cpuinfo(void)
 340 {
 341         unsigned char resetsource = MCFRESET_RSR;
 342
 343         printf("CPU:   Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
 344                MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
 345         printf("Reset:%s%s%s%s%s%s%s\n",
 346                (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
 347                (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
 348                (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
 349                (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
 350                (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
 351                (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
 352                (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
 353         return 0;
 354 }
 355 #endif /* CONFIG_DISPLAY_CPUINFO */
 356
 357 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 358 {
 359         MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
 360         return 0;
 361 };
 362 #endif
 363
 364 #ifdef CONFIG_M5249
 365 #if defined(CONFIG_DISPLAY_CPUINFO)
 366 int print_cpuinfo(void)
 367 {
 368         char buf[32];
 369
 370         printf("CPU:   Freescale Coldfire MCF5249 at %s MHz\n",
 371                strmhz(buf, CONFIG_SYS_CLK));
 372         return 0;
 373 }
 374 #endif /* CONFIG_DISPLAY_CPUINFO */
 375
 376 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 377 {
 378         /* enable watchdog, set timeout to 0 and wait */
 379         mbar_writeByte(MCFSIM_SYPCR, 0xc0);
 380         while (1) ;
 381
 382         /* we don't return! */
 383         return 0;
 384 };
 385 #endif
 386
 387 #ifdef CONFIG_M5253
 388 #if defined(CONFIG_DISPLAY_CPUINFO)
 389 int print_cpuinfo(void)
 390 {
 391         char buf[32];
 392
 393         unsigned char resetsource = mbar_readLong(SIM_RSR);
 394         printf("CPU:   Freescale Coldfire MCF5253 at %s MHz\n",
 395                strmhz(buf, CONFIG_SYS_CLK));
 396
 397         if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
 398                 printf("Reset:%s%s\n",
 399                        (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
 400                        : "",
 401                        (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
 402                        "");
 403         }
 404         return 0;
 405 }
 406 #endif /* CONFIG_DISPLAY_CPUINFO */
 407
 408 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 409 {
 410         /* enable watchdog, set timeout to 0 and wait */
 411         mbar_writeByte(SIM_SYPCR, 0xc0);
 412         while (1) ;
 413
 414         /* we don't return! */
 415         return 0;
 416 };
 417 #endif
 418
 419 #if defined(CONFIG_MCFFEC)
 420 /* Default initializations for MCFFEC controllers.  To override,
 421  * create a board-specific function called:
 422  *      int board_eth_init(bd_t *bis)
 423  */
 424
 425 int cpu_eth_init(bd_t *bis)
 426 {
 427         return mcffec_initialize(bis);
 428 }
 429 #endif