arch/m68k/cpu/mcf5445x/start.S

   1 /*
   2  * Copyright (C) 2003   Josef Baumgartner <josef.baumgartner@telex.de>
   3  * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <config.h>
  25 #include <timestamp.h>
  26 #include "version.h"
  27 #include <asm/cache.h>
  28
  29 #ifndef  CONFIG_IDENT_STRING
  30 #define  CONFIG_IDENT_STRING ""
  31 #endif
  32
  33 #define _START  _start
  34 #define _FAULT  _fault
  35
  36 #define SAVE_ALL                                                \
  37         move.w  #0x2700,%sr;            /* disable intrs */     \
  38         subl    #60,%sp;                /* space for 15 regs */ \
  39         moveml  %d0-%d7/%a0-%a6,%sp@;
  40
  41 #define RESTORE_ALL                                             \
  42         moveml  %sp@,%d0-%d7/%a0-%a6;                           \
  43         addl    #60,%sp;                /* space for 15 regs */ \
  44         rte;
  45
  46 #if defined(CONFIG_CF_SBF)
  47 #define ASM_DRAMINIT    (asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
  48 #define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
  49 #endif
  50
  51 .text
  52
  53 /*
  54  *      Vector table. This is used for initial platform startup.
  55  *      These vectors are to catch any un-intended traps.
  56  */
  57 _vectors:
  58 #if defined(CONFIG_CF_SBF)
  59
  60 INITSP: .long   0               /* Initial SP   */
  61 INITPC: .long   ASM_DRAMINIT    /* Initial PC   */
  62
  63 #else
  64
  65 INITSP:         .long   0       /* Initial SP   */
  66 INITPC:         .long   _START  /* Initial PC           */
  67
  68 #endif
  69
  70 vector02:       .long   _FAULT  /* Access Error         */
  71 vector03:       .long   _FAULT  /* Address Error        */
  72 vector04:       .long   _FAULT  /* Illegal Instruction  */
  73 vector05:       .long   _FAULT  /* Reserved             */
  74 vector06:       .long   _FAULT  /* Reserved             */
  75 vector07:       .long   _FAULT  /* Reserved             */
  76 vector08:       .long   _FAULT  /* Privilege Violation  */
  77 vector09:       .long   _FAULT  /* Trace                */
  78 vector0A:       .long   _FAULT  /* Unimplemented A-Line */
  79 vector0B:       .long   _FAULT  /* Unimplemented F-Line */
  80 vector0C:       .long   _FAULT  /* Debug Interrupt      */
  81 vector0D:       .long   _FAULT  /* Reserved             */
  82 vector0E:       .long   _FAULT  /* Format Error         */
  83 vector0F:       .long   _FAULT  /* Unitialized Int.     */
  84
  85 /* Reserved */
  86 vector10_17:
  87 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
  88
  89 vector18:       .long   _FAULT  /* Spurious Interrupt   */
  90 vector19:       .long   _FAULT  /* Autovector Level 1   */
  91 vector1A:       .long   _FAULT  /* Autovector Level 2   */
  92 vector1B:       .long   _FAULT  /* Autovector Level 3   */
  93 vector1C:       .long   _FAULT  /* Autovector Level 4   */
  94 vector1D:       .long   _FAULT  /* Autovector Level 5   */
  95 vector1E:       .long   _FAULT  /* Autovector Level 6   */
  96 vector1F:       .long   _FAULT  /* Autovector Level 7   */
  97
  98 #if !defined(CONFIG_CF_SBF)
  99
 100 /* TRAP #0 - #15 */
 101 vector20_2F:
 102 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 103 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 104
 105 /* Reserved     */
 106 vector30_3F:
 107 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 108 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 109
 110 vector64_127:
 111 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 112 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 113 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 114 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 115 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 116 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 117 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 118 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 119
 120 vector128_191:
 121 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 122 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 123 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 124 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 125 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 126 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 127 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 128 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 129
 130 vector192_255:
 131 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 132 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 133 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 134 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 135 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 136 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 137 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 138 .long   _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 139 #endif
 140
 141 #if defined(CONFIG_CF_SBF)
 142         /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
 143 asm_sbf_img_hdr:
 144         .long   0x00000000      /* checksum, not yet implemented */
 145         .long   0x00030000      /* image length */
 146         .long   CONFIG_SYS_TEXT_BASE    /* image to be relocated at */
 147
 148 asm_dram_init:
 149         move.w #0x2700,%sr              /* Mask off Interrupt */
 150
 151         move.l  #CONFIG_SYS_INIT_RAM_ADDR, %d0
 152         movec   %d0, %VBR
 153
 154         move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
 155         movec   %d0, %RAMBAR1
 156
 157         /* initialize general use internal ram */
 158         move.l #0, %d0
 159         move.l #(ICACHE_STATUS), %a1    /* icache */
 160         move.l #(DCACHE_STATUS), %a2    /* dcache */
 161         move.l %d0, (%a1)
 162         move.l %d0, (%a2)
 163
 164         /* invalidate and disable cache */
 165         move.l  #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
 166         movec   %d0, %CACR              /* Invalidate cache */
 167         move.l  #0, %d0
 168         movec   %d0, %ACR0
 169         movec   %d0, %ACR1
 170         movec   %d0, %ACR2
 171         movec   %d0, %ACR3
 172
 173         move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 174         clr.l %sp@-
 175
 176         /* Must disable global address */
 177         move.l  #0xFC008000, %a1
 178         move.l  #(CONFIG_SYS_CS0_BASE), (%a1)
 179         move.l  #0xFC008008, %a1
 180         move.l  #(CONFIG_SYS_CS0_CTRL), (%a1)
 181         move.l  #0xFC008004, %a1
 182         move.l  #(CONFIG_SYS_CS0_MASK), (%a1)
 183
 184         /* Dram Initialization a1, a2, and d0 */
 185         /* mscr sdram */
 186         move.l  #0xFC0A4074, %a1
 187         move.b  #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
 188         nop
 189
 190         /* SDRAM Chip 0 and 1 */
 191         move.l  #0xFC0B8110, %a1
 192         move.l  #0xFC0B8114, %a2
 193
 194         /* calculate the size */
 195         move.l  #0x13, %d1
 196         move.l  #(CONFIG_SYS_SDRAM_SIZE), %d2
 197 #ifdef CONFIG_SYS_SDRAM_BASE1
 198         lsr.l   #1, %d2
 199 #endif
 200
 201 dramsz_loop:
 202         lsr.l   #1, %d2
 203         add.l   #1, %d1
 204         cmp.l   #1, %d2
 205         bne     dramsz_loop
 206
 207         /* SDRAM Chip 0 and 1 */
 208         move.l  #(CONFIG_SYS_SDRAM_BASE), (%a1)
 209         or.l    %d1, (%a1)
 210 #ifdef CONFIG_SYS_SDRAM_BASE1
 211         move.l  #(CONFIG_SYS_SDRAM_BASE1), (%a2)
 212         or.l    %d1, (%a2)
 213 #endif
 214         nop
 215
 216         /* dram cfg1 and cfg2 */
 217         move.l  #0xFC0B8008, %a1
 218         move.l  #(CONFIG_SYS_SDRAM_CFG1), (%a1)
 219         nop
 220         move.l  #0xFC0B800C, %a2
 221         move.l  #(CONFIG_SYS_SDRAM_CFG2), (%a2)
 222         nop
 223
 224         move.l  #0xFC0B8000, %a1        /* Mode */
 225         move.l  #0xFC0B8004, %a2        /* Ctrl */
 226
 227         /* Issue PALL */
 228         move.l  #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
 229         nop
 230
 231 #ifdef CONFIG_M54455EVB
 232         /* Issue LEMR */
 233         move.l  #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
 234         nop
 235         move.l  #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
 236         nop
 237 #endif
 238
 239         move.l  #1000, %d1
 240         jsr     asm_delay
 241
 242         /* Issue PALL */
 243         move.l  #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
 244         nop
 245
 246         /* Perform two refresh cycles */
 247         move.l  #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
 248         nop
 249         move.l  %d0, (%a2)
 250         move.l  %d0, (%a2)
 251         nop
 252
 253 #ifdef CONFIG_M54455EVB
 254         move.l  #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
 255         nop
 256 #elif defined(CONFIG_M54451EVB)
 257         /* Issue LEMR */
 258         move.l  #(CONFIG_SYS_SDRAM_MODE), (%a1)
 259         nop
 260         move.l  #(CONFIG_SYS_SDRAM_EMOD), (%a1)
 261 #endif
 262
 263         move.l  #500, %d1
 264         jsr     asm_delay
 265
 266         move.l  #(CONFIG_SYS_SDRAM_CTRL), %d1
 267         and.l   #0x7FFFFFFF, %d1
 268 #ifdef CONFIG_M54455EVB
 269         or.l    #0x10000C00, %d1
 270 #elif defined(CONFIG_M54451EVB)
 271         or.l    #0x10000C00, %d1
 272 #endif
 273         move.l  %d1, (%a2)
 274         nop
 275
 276         move.l  #2000, %d1
 277         jsr     asm_delay
 278
 279         /*
 280          * DSPI Initialization
 281          * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
 282          * a1 - dspi status
 283          * a2 - dtfr
 284          * a3 - drfr
 285          * a4 - Dst addr
 286          */
 287         /* Enable pins for DSPI mode - chip-selects are enabled later */
 288 asm_dspi_init:
 289         move.l  #0xFC0A4063, %a0
 290         move.b  #0x7F, (%a0)
 291
 292         /* Configure DSPI module */
 293         move.l  #0xFC05C000, %a0
 294         move.l  #0x80FF0C00, (%a0)      /* Master, clear TX/RX FIFO */
 295
 296         move.l  #0xFC05C00C, %a0
 297         move.l  #0x3E000011, (%a0)
 298
 299         move.l  #0xFC05C034, %a2        /* dtfr */
 300         move.l  #0xFC05C03B, %a3        /* drfr */
 301
 302         move.l  #(ASM_SBF_IMG_HDR + 4), %a1
 303         move.l  (%a1)+, %d5
 304         move.l  (%a1), %a4
 305
 306         move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
 307         move.l  #(CONFIG_SYS_SBFHDR_SIZE), %d4
 308
 309         move.l  #0xFC05C02C, %a1        /* dspi status */
 310
 311         /* Issue commands and address */
 312         move.l  #0x8002000B, %d2        /* Fast Read Cmd */
 313         jsr     asm_dspi_wr_status
 314         jsr     asm_dspi_rd_status
 315
 316         move.l  #0x80020000, %d2        /* Address byte 2 */
 317         jsr     asm_dspi_wr_status
 318         jsr     asm_dspi_rd_status
 319
 320         move.l  #0x80020000, %d2        /* Address byte 1 */
 321         jsr     asm_dspi_wr_status
 322         jsr     asm_dspi_rd_status
 323
 324         move.l  #0x80020000, %d2        /* Address byte 0 */
 325         jsr     asm_dspi_wr_status
 326         jsr     asm_dspi_rd_status
 327
 328         move.l  #0x80020000, %d2        /* Dummy Wr and Rd */
 329         jsr     asm_dspi_wr_status
 330         jsr     asm_dspi_rd_status
 331
 332         /* Transfer serial boot header to sram */
 333 asm_dspi_rd_loop1:
 334         move.l  #0x80020000, %d2
 335         jsr     asm_dspi_wr_status
 336         jsr     asm_dspi_rd_status
 337
 338         move.b  %d1, (%a0)              /* read, copy to dst */
 339
 340         add.l   #1, %a0                 /* inc dst by 1 */
 341         sub.l   #1, %d4                 /* dec cnt by 1 */
 342         bne     asm_dspi_rd_loop1
 343
 344         /* Transfer u-boot from serial flash to memory */
 345 asm_dspi_rd_loop2:
 346         move.l  #0x80020000, %d2
 347         jsr     asm_dspi_wr_status
 348         jsr     asm_dspi_rd_status
 349
 350         move.b  %d1, (%a4)              /* read, copy to dst */
 351
 352         add.l   #1, %a4                 /* inc dst by 1 */
 353         sub.l   #1, %d5                 /* dec cnt by 1 */
 354         bne     asm_dspi_rd_loop2
 355
 356         move.l  #0x00020000, %d2        /* Terminate */
 357         jsr     asm_dspi_wr_status
 358         jsr     asm_dspi_rd_status
 359
 360         /* jump to memory and execute */
 361         move.l  #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
 362         jmp     (%a0)
 363
 364 asm_dspi_wr_status:
 365         move.l  (%a1), %d0              /* status */
 366         and.l   #0x0000F000, %d0
 367         cmp.l   #0x00003000, %d0
 368         bgt     asm_dspi_wr_status
 369
 370         move.l  %d2, (%a2)
 371         rts
 372
 373 asm_dspi_rd_status:
 374         move.l  (%a1), %d0              /* status */
 375         and.l   #0x000000F0, %d0
 376         lsr.l   #4, %d0
 377         cmp.l   #0, %d0
 378         beq     asm_dspi_rd_status
 379
 380         move.b  (%a3), %d1
 381         rts
 382
 383 asm_delay:
 384         nop
 385         subq.l  #1, %d1
 386         bne     asm_delay
 387         rts
 388 #endif                  /* CONFIG_CF_SBF */
 389
 390         .text
 391         . = 0x400
 392         .globl  _start
 393 _start:
 394 #if !defined(CONFIG_CF_SBF)
 395         nop
 396         nop
 397         move.w #0x2700,%sr              /* Mask off Interrupt */
 398
 399         /* Set vector base register at the beginning of the Flash */
 400         move.l  #CONFIG_SYS_FLASH_BASE, %d0
 401         movec   %d0, %VBR
 402
 403         move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
 404         movec   %d0, %RAMBAR1
 405
 406         /* initialize general use internal ram */
 407         move.l #0, %d0
 408         move.l #(ICACHE_STATUS), %a1    /* icache */
 409         move.l #(DCACHE_STATUS), %a2    /* dcache */
 410         move.l %d0, (%a1)
 411         move.l %d0, (%a2)
 412
 413         /* invalidate and disable cache */
 414         move.l  #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
 415         movec   %d0, %CACR              /* Invalidate cache */
 416         move.l  #0, %d0
 417         movec   %d0, %ACR0
 418         movec   %d0, %ACR1
 419         movec   %d0, %ACR2
 420         movec   %d0, %ACR3
 421
 422         /* set stackpointer to end of internal ram to get some stackspace for
 423            the first c-code */
 424         move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 425         clr.l %sp@-
 426 #endif
 427
 428         move.l #__got_start, %a5        /* put relocation table address to a5 */
 429
 430         bsr cpu_init_f                  /* run low-level CPU init code (from flash) */
 431         bsr board_init_f                /* run low-level board init code (from flash) */
 432
 433         /* board_init_f() does not return */
 434
 435 /*------------------------------------------------------------------------------*/
 436
 437 /*
 438  * void relocate_code (addr_sp, gd, addr_moni)
 439  *
 440  * This "function" does not return, instead it continues in RAM
 441  * after relocating the monitor code.
 442  *
 443  * r3 = dest
 444  * r4 = src
 445  * r5 = length in bytes
 446  * r6 = cachelinesize
 447  */
 448         .globl  relocate_code
 449 relocate_code:
 450         link.w %a6,#0
 451         move.l 8(%a6), %sp              /* set new stack pointer */
 452
 453         move.l 12(%a6), %d0             /* Save copy of Global Data pointer */
 454         move.l 16(%a6), %a0             /* Save copy of Destination Address */
 455
 456         move.l #CONFIG_SYS_MONITOR_BASE, %a1
 457         move.l #__init_end, %a2
 458         move.l %a0, %a3
 459
 460         /* copy the code to RAM */
 461 1:
 462         move.l (%a1)+, (%a3)+
 463         cmp.l  %a1,%a2
 464         bgt.s    1b
 465
 466 /*
 467  * We are done. Do not return, instead branch to second part of board
 468  * initialization, now running from RAM.
 469  */
 470         move.l  %a0, %a1
 471         add.l   #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
 472         jmp     (%a1)
 473
 474 in_ram:
 475
 476 clear_bss:
 477         /*
 478          * Now clear BSS segment
 479          */
 480         move.l  %a0, %a1
 481         add.l   #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
 482         move.l  %a0, %d1
 483         add.l   #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
 484 6:
 485         clr.l   (%a1)+
 486         cmp.l   %a1,%d1
 487         bgt.s   6b
 488
 489         /*
 490          * fix got table in RAM
 491          */
 492         move.l  %a0, %a1
 493         add.l   #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
 494         move.l  %a1,%a5                 /* * fix got pointer register a5 */
 495
 496         move.l  %a0, %a2
 497         add.l   #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
 498
 499 7:
 500         move.l  (%a1),%d1
 501         sub.l   #_start,%d1
 502         add.l   %a0,%d1
 503         move.l  %d1,(%a1)+
 504         cmp.l   %a2, %a1
 505         bne     7b
 506
 507         /* calculate relative jump to board_init_r in ram */
 508         move.l %a0, %a1
 509         add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
 510
 511         /* set parameters for board_init_r */
 512         move.l %a0,-(%sp)               /* dest_addr */
 513         move.l %d0,-(%sp)               /* gd */
 514         jsr     (%a1)
 515
 516 /*------------------------------------------------------------------------------*/
 517 /* exception code */
 518         .globl _fault
 519 _fault:
 520         bra _fault
 521         .globl  _exc_handler
 522
 523 _exc_handler:
 524         SAVE_ALL
 525         movel   %sp,%sp@-
 526         bsr exc_handler
 527         addql   #4,%sp
 528         RESTORE_ALL
 529
 530         .globl  _int_handler
 531 _int_handler:
 532         SAVE_ALL
 533         movel   %sp,%sp@-
 534         bsr int_handler
 535         addql   #4,%sp
 536         RESTORE_ALL
 537
 538 /*------------------------------------------------------------------------------*/
 539
 540         .globl  version_string
 541 version_string:
 542         .ascii U_BOOT_VERSION
 543         .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
 544         .ascii CONFIG_IDENT_STRING, "\0"
 545         .align 4