arch/m68k/cpu/mcf547x_8x/pci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
   4  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   5  */
   6
   7 /*
   8  * PCI Configuration space access support
   9  */
  10 #include <common.h>
  11 #include <pci.h>
  12 #include <asm/io.h>
  13 #include <asm/immap.h>
  14
  15 #if defined(CONFIG_PCI)
  16 /* System RAM mapped over PCI */
  17 #define CONFIG_SYS_PCI_SYS_MEM_BUS      CONFIG_SYS_SDRAM_BASE
  18 #define CONFIG_SYS_PCI_SYS_MEM_PHYS     CONFIG_SYS_SDRAM_BASE
  19 #define CONFIG_SYS_PCI_SYS_MEM_SIZE     (1024 * 1024 * 1024)
  20
  21 #define cfg_read(val, addr, type, op)           *val = op((type)(addr));
  22 #define cfg_write(val, addr, type, op)          op((type *)(addr), (val));
  23
  24 #define PCI_OP(rw, size, type, op, mask)                                \
  25 int pci_##rw##_cfg_##size(struct pci_controller *hose,                  \
  26         pci_dev_t dev, int offset, type val)                            \
  27 {                                                                       \
  28         u32 addr = 0;                                                   \
  29         u16 cfg_type = 0;                                               \
  30         addr = ((offset & 0xfc) | cfg_type | (dev)  | 0x80000000);      \
  31         out_be32(hose->cfg_addr, addr);                                 \
  32         cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);      \
  33         __asm__ __volatile__("nop");                                    \
  34         __asm__ __volatile__("nop");                                    \
  35         out_be32(hose->cfg_addr, addr & 0x7fffffff);                    \
  36         return 0;                                                       \
  37 }
  38
  39 PCI_OP(read, byte, u8 *, in_8, 3)
  40 PCI_OP(read, word, u16 *, in_le16, 2)
  41 PCI_OP(write, byte, u8, out_8, 3)
  42 PCI_OP(write, word, u16, out_le16, 2)
  43 PCI_OP(write, dword, u32, out_le32, 0)
  44
  45 int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
  46                        int offset, u32 * val)
  47 {
  48         u32 addr;
  49         u32 tmpv;
  50         u32 mask = 2;           /* word access */
  51         /* Read lower 16 bits */
  52         addr = ((offset & 0xfc) | (dev) | 0x80000000);
  53         out_be32(hose->cfg_addr, addr);
  54         *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
  55         __asm__ __volatile__("nop");
  56         out_be32(hose->cfg_addr, addr & 0x7fffffff);
  57
  58         /* Read upper 16 bits */
  59         offset += 2;
  60         addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
  61         out_be32(hose->cfg_addr, addr);
  62         tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
  63         __asm__ __volatile__("nop");
  64         out_be32(hose->cfg_addr, addr & 0x7fffffff);
  65
  66         /* combine results into dword value */
  67         *val = (tmpv << 16) | *val;
  68
  69         return 0;
  70 }
  71
  72 void pci_mcf547x_8x_init(struct pci_controller *hose)
  73 {
  74         pci_t *pci = (pci_t *) MMAP_PCI;
  75         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  76
  77         /* Port configuration */
  78         out_be16(&gpio->par_pcibg,
  79                 GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
  80                 GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
  81                 GPIO_PAR_PCIBG_PCIBG4(3));
  82         out_be16(&gpio->par_pcibr,
  83                 GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
  84                 GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
  85                 GPIO_PAR_PCIBR_PCIBR4(3));
  86
  87         /* Assert reset bit */
  88         setbits_be32(&pci->gscr, PCI_GSCR_PR);
  89
  90         out_be32(&pci->tcr1, PCI_TCR1_P);
  91
  92         /* Initiator windows */
  93         out_be32(&pci->iw0btar,
  94                 CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
  95         out_be32(&pci->iw1btar,
  96                 CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
  97         out_be32(&pci->iw2btar,
  98                 CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
  99
 100         out_be32(&pci->iwcr,
 101                 PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
 102                 PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
 103
 104         out_be32(&pci->icr, 0);
 105
 106         /* Enable bus master and mem access */
 107         out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
 108
 109         /* Cache line size and master latency */
 110         out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8));
 111         out_be32(&pci->cr2, 0);
 112
 113 #ifdef CONFIG_SYS_PCI_BAR0
 114         out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
 115         out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
 116 #endif
 117 #ifdef CONFIG_SYS_PCI_BAR1
 118         out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
 119         out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
 120 #endif
 121
 122         /* Deassert reset bit */
 123         clrbits_be32(&pci->gscr, PCI_GSCR_PR);
 124         udelay(1000);
 125
 126         /* Enable PCI bus master support */
 127         hose->first_busno = 0;
 128         hose->last_busno = 0xff;
 129
 130         pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
 131                        CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
 132
 133         pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
 134                        CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
 135
 136         pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
 137                        CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
 138                        PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 139
 140         hose->region_count = 3;
 141
 142         hose->cfg_addr = &(pci->car);
 143         hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
 144
 145         pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
 146                     pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
 147                     pci_write_cfg_dword);
 148
 149         /* Hose scan */
 150         pci_register_hose(hose);
 151         hose->last_busno = pci_hose_scan(hose);
 152 }
 153 #endif                          /* CONFIG_PCI */