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License cleanup: add SPDX GPL-2.0 license identifier to files with no license
[people/arne_f/kernel.git] / arch / m68k / include / asm / MC68VZ328.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
4 *
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
7 * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
8 * Bare & Hare Software, Inc.
9 * Based on include/asm-m68knommu/MC68332.h
10 * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
11 * The Silver Hammer Group, Ltd.
12 *
13 * M68VZ328 fixes by Evan Stawnyczy <evan@lineo.com>
14 * vz multiport fixes by Michael Leslie <mleslie@lineo.com>
15 */
16
17 #ifndef _MC68VZ328_H_
18 #define _MC68VZ328_H_
19
20 #define BYTE_REF(addr) (*((volatile unsigned char*)addr))
21 #define WORD_REF(addr) (*((volatile unsigned short*)addr))
22 #define LONG_REF(addr) (*((volatile unsigned long*)addr))
23
24 #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
25 #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
26
27 /**********
28 *
29 * 0xFFFFF0xx -- System Control
30 *
31 **********/
32
33 /*
34 * System Control Register (SCR)
35 */
36 #define SCR_ADDR 0xfffff000
37 #define SCR BYTE_REF(SCR_ADDR)
38
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_DMAP 0x04 /* Double Map */
41 #define SCR_SO 0x08 /* Supervisor Only */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_PRV 0x20 /* Privilege Violation */
44 #define SCR_WPV 0x40 /* Write Protect Violation */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
46
47 /*
48 * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
49 */
50 #define MRR_ADDR 0xfffff004
51 #define MRR LONG_REF(MRR_ADDR)
52
53 /**********
54 *
55 * 0xFFFFF1xx -- Chip-Select logic
56 *
57 **********/
58
59 /*
60 * Chip Select Group Base Registers
61 */
62 #define CSGBA_ADDR 0xfffff100
63 #define CSGBB_ADDR 0xfffff102
64
65 #define CSGBC_ADDR 0xfffff104
66 #define CSGBD_ADDR 0xfffff106
67
68 #define CSGBA WORD_REF(CSGBA_ADDR)
69 #define CSGBB WORD_REF(CSGBB_ADDR)
70 #define CSGBC WORD_REF(CSGBC_ADDR)
71 #define CSGBD WORD_REF(CSGBD_ADDR)
72
73 /*
74 * Chip Select Registers
75 */
76 #define CSA_ADDR 0xfffff110
77 #define CSB_ADDR 0xfffff112
78 #define CSC_ADDR 0xfffff114
79 #define CSD_ADDR 0xfffff116
80
81 #define CSA WORD_REF(CSA_ADDR)
82 #define CSB WORD_REF(CSB_ADDR)
83 #define CSC WORD_REF(CSC_ADDR)
84 #define CSD WORD_REF(CSD_ADDR)
85
86 #define CSA_EN 0x0001 /* Chip-Select Enable */
87 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
88 #define CSA_SIZ_SHIFT 1
89 #define CSA_WS_MASK 0x0070 /* Wait State */
90 #define CSA_WS_SHIFT 4
91 #define CSA_BSW 0x0080 /* Data Bus Width */
92 #define CSA_FLASH 0x0100 /* FLASH Memory Support */
93 #define CSA_RO 0x8000 /* Read-Only */
94
95 #define CSB_EN 0x0001 /* Chip-Select Enable */
96 #define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
97 #define CSB_SIZ_SHIFT 1
98 #define CSB_WS_MASK 0x0070 /* Wait State */
99 #define CSB_WS_SHIFT 4
100 #define CSB_BSW 0x0080 /* Data Bus Width */
101 #define CSB_FLASH 0x0100 /* FLASH Memory Support */
102 #define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
103 #define CSB_UPSIZ_SHIFT 11
104 #define CSB_ROP 0x2000 /* Readonly if protected */
105 #define CSB_SOP 0x4000 /* Supervisor only if protected */
106 #define CSB_RO 0x8000 /* Read-Only */
107
108 #define CSC_EN 0x0001 /* Chip-Select Enable */
109 #define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
110 #define CSC_SIZ_SHIFT 1
111 #define CSC_WS_MASK 0x0070 /* Wait State */
112 #define CSC_WS_SHIFT 4
113 #define CSC_BSW 0x0080 /* Data Bus Width */
114 #define CSC_FLASH 0x0100 /* FLASH Memory Support */
115 #define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
116 #define CSC_UPSIZ_SHIFT 11
117 #define CSC_ROP 0x2000 /* Readonly if protected */
118 #define CSC_SOP 0x4000 /* Supervisor only if protected */
119 #define CSC_RO 0x8000 /* Read-Only */
120
121 #define CSD_EN 0x0001 /* Chip-Select Enable */
122 #define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
123 #define CSD_SIZ_SHIFT 1
124 #define CSD_WS_MASK 0x0070 /* Wait State */
125 #define CSD_WS_SHIFT 4
126 #define CSD_BSW 0x0080 /* Data Bus Width */
127 #define CSD_FLASH 0x0100 /* FLASH Memory Support */
128 #define CSD_DRAM 0x0200 /* Dram Selection */
129 #define CSD_COMB 0x0400 /* Combining */
130 #define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
131 #define CSD_UPSIZ_SHIFT 11
132 #define CSD_ROP 0x2000 /* Readonly if protected */
133 #define CSD_SOP 0x4000 /* Supervisor only if protected */
134 #define CSD_RO 0x8000 /* Read-Only */
135
136 /*
137 * Emulation Chip-Select Register
138 */
139 #define EMUCS_ADDR 0xfffff118
140 #define EMUCS WORD_REF(EMUCS_ADDR)
141
142 #define EMUCS_WS_MASK 0x0070
143 #define EMUCS_WS_SHIFT 4
144
145 /**********
146 *
147 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
148 *
149 **********/
150
151 /*
152 * PLL Control Register
153 */
154 #define PLLCR_ADDR 0xfffff200
155 #define PLLCR WORD_REF(PLLCR_ADDR)
156
157 #define PLLCR_DISPLL 0x0008 /* Disable PLL */
158 #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
159 #define PLLCR_PRESC 0x0020 /* VCO prescaler */
160 #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
161 #define PLLCR_SYSCLK_SEL_SHIFT 8
162 #define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
163 #define PLLCR_LCDCLK_SEL_SHIFT 11
164
165 /* '328-compatible definitions */
166 #define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK
167 #define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT
168
169 /*
170 * PLL Frequency Select Register
171 */
172 #define PLLFSR_ADDR 0xfffff202
173 #define PLLFSR WORD_REF(PLLFSR_ADDR)
174
175 #define PLLFSR_PC_MASK 0x00ff /* P Count */
176 #define PLLFSR_PC_SHIFT 0
177 #define PLLFSR_QC_MASK 0x0f00 /* Q Count */
178 #define PLLFSR_QC_SHIFT 8
179 #define PLLFSR_PROT 0x4000 /* Protect P & Q */
180 #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
181
182 /*
183 * Power Control Register
184 */
185 #define PCTRL_ADDR 0xfffff207
186 #define PCTRL BYTE_REF(PCTRL_ADDR)
187
188 #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
189 #define PCTRL_WIDTH_SHIFT 0
190 #define PCTRL_PCEN 0x80 /* Power Control Enable */
191
192 /**********
193 *
194 * 0xFFFFF3xx -- Interrupt Controller
195 *
196 **********/
197
198 /*
199 * Interrupt Vector Register
200 */
201 #define IVR_ADDR 0xfffff300
202 #define IVR BYTE_REF(IVR_ADDR)
203
204 #define IVR_VECTOR_MASK 0xF8
205
206 /*
207 * Interrupt control Register
208 */
209 #define ICR_ADDR 0xfffff302
210 #define ICR WORD_REF(ICR_ADDR)
211
212 #define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */
213 #define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
214 #define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
215 #define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
216 #define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
217 #define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
218 #define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
219 #define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
220 #define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
221
222 /*
223 * Interrupt Mask Register
224 */
225 #define IMR_ADDR 0xfffff304
226 #define IMR LONG_REF(IMR_ADDR)
227
228 /*
229 * Define the names for bit positions first. This is useful for
230 * request_irq
231 */
232 #define SPI2_IRQ_NUM 0 /* SPI 2 interrupt */
233 #define TMR_IRQ_NUM 1 /* Timer 1 interrupt */
234 #define UART1_IRQ_NUM 2 /* UART 1 interrupt */
235 #define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
236 #define RTC_IRQ_NUM 4 /* RTC interrupt */
237 #define TMR2_IRQ_NUM 5 /* Timer 2 interrupt */
238 #define KB_IRQ_NUM 6 /* Keyboard Interrupt */
239 #define PWM1_IRQ_NUM 7 /* Pulse-Width Modulator 1 int. */
240 #define INT0_IRQ_NUM 8 /* External INT0 */
241 #define INT1_IRQ_NUM 9 /* External INT1 */
242 #define INT2_IRQ_NUM 10 /* External INT2 */
243 #define INT3_IRQ_NUM 11 /* External INT3 */
244 #define UART2_IRQ_NUM 12 /* UART 2 interrupt */
245 #define PWM2_IRQ_NUM 13 /* Pulse-Width Modulator 1 int. */
246 #define IRQ1_IRQ_NUM 16 /* IRQ1 */
247 #define IRQ2_IRQ_NUM 17 /* IRQ2 */
248 #define IRQ3_IRQ_NUM 18 /* IRQ3 */
249 #define IRQ6_IRQ_NUM 19 /* IRQ6 */
250 #define IRQ5_IRQ_NUM 20 /* IRQ5 */
251 #define SPI1_IRQ_NUM 21 /* SPI 1 interrupt */
252 #define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */
253 #define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */
254
255 #define SPI_IRQ_NUM SPI2_IRQ_NUM
256
257 /* '328-compatible definitions */
258 #define SPIM_IRQ_NUM SPI_IRQ_NUM
259 #define TMR1_IRQ_NUM TMR_IRQ_NUM
260 #define UART_IRQ_NUM UART1_IRQ_NUM
261
262 /*
263 * Here go the bitmasks themselves
264 */
265 #define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */
266 #define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */
267 #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
268 #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
269 #define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
270 #define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
271 #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
272 #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
273 #define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
274 #define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
275 #define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
276 #define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
277 #define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
278 #define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
279 #define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
280 #define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */
281 #define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */
282 #define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */
283
284 /* '328-compatible definitions */
285 #define IMR_MSPIM IMR_MSPI
286 #define IMR_MTMR1 IMR_MTMR
287
288 /*
289 * Interrupt Status Register
290 */
291 #define ISR_ADDR 0xfffff30c
292 #define ISR LONG_REF(ISR_ADDR)
293
294 #define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
295 #define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
296 #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
297 #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
298 #define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
299 #define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
300 #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
301 #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
302 #define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
303 #define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
304 #define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
305 #define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
306 #define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
307 #define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
308 #define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
309 #define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
310 #define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
311 #define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
312
313 /* '328-compatible definitions */
314 #define ISR_SPIM ISR_SPI
315 #define ISR_TMR1 ISR_TMR
316
317 /*
318 * Interrupt Pending Register
319 */
320 #define IPR_ADDR 0xfffff30c
321 #define IPR LONG_REF(IPR_ADDR)
322
323 #define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
324 #define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
325 #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
326 #define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
327 #define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
328 #define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
329 #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
330 #define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
331 #define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
332 #define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
333 #define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
334 #define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
335 #define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
336 #define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
337 #define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
338 #define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
339 #define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
340 #define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
341
342 /* '328-compatible definitions */
343 #define IPR_SPIM IPR_SPI
344 #define IPR_TMR1 IPR_TMR
345
346 /**********
347 *
348 * 0xFFFFF4xx -- Parallel Ports
349 *
350 **********/
351
352 /*
353 * Port A
354 */
355 #define PADIR_ADDR 0xfffff400 /* Port A direction reg */
356 #define PADATA_ADDR 0xfffff401 /* Port A data register */
357 #define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
358
359 #define PADIR BYTE_REF(PADIR_ADDR)
360 #define PADATA BYTE_REF(PADATA_ADDR)
361 #define PAPUEN BYTE_REF(PAPUEN_ADDR)
362
363 #define PA(x) (1 << (x))
364
365 /*
366 * Port B
367 */
368 #define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
369 #define PBDATA_ADDR 0xfffff409 /* Port B data register */
370 #define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
371 #define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
372
373 #define PBDIR BYTE_REF(PBDIR_ADDR)
374 #define PBDATA BYTE_REF(PBDATA_ADDR)
375 #define PBPUEN BYTE_REF(PBPUEN_ADDR)
376 #define PBSEL BYTE_REF(PBSEL_ADDR)
377
378 #define PB(x) (1 << (x))
379
380 #define PB_CSB0 0x01 /* Use CSB0 as PB[0] */
381 #define PB_CSB1 0x02 /* Use CSB1 as PB[1] */
382 #define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */
383 #define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */
384 #define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */
385 #define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */
386 #define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */
387 #define PB_PWMO 0x80 /* Use PWMO as PB[7] */
388
389 /*
390 * Port C
391 */
392 #define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
393 #define PCDATA_ADDR 0xfffff411 /* Port C data register */
394 #define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
395 #define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
396
397 #define PCDIR BYTE_REF(PCDIR_ADDR)
398 #define PCDATA BYTE_REF(PCDATA_ADDR)
399 #define PCPDEN BYTE_REF(PCPDEN_ADDR)
400 #define PCSEL BYTE_REF(PCSEL_ADDR)
401
402 #define PC(x) (1 << (x))
403
404 #define PC_LD0 0x01 /* Use LD0 as PC[0] */
405 #define PC_LD1 0x02 /* Use LD1 as PC[1] */
406 #define PC_LD2 0x04 /* Use LD2 as PC[2] */
407 #define PC_LD3 0x08 /* Use LD3 as PC[3] */
408 #define PC_LFLM 0x10 /* Use LFLM as PC[4] */
409 #define PC_LLP 0x20 /* Use LLP as PC[5] */
410 #define PC_LCLK 0x40 /* Use LCLK as PC[6] */
411 #define PC_LACD 0x80 /* Use LACD as PC[7] */
412
413 /*
414 * Port D
415 */
416 #define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
417 #define PDDATA_ADDR 0xfffff419 /* Port D data register */
418 #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
419 #define PDSEL_ADDR 0xfffff41b /* Port D Select Register */
420 #define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
421 #define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
422 #define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */
423 #define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
424
425 #define PDDIR BYTE_REF(PDDIR_ADDR)
426 #define PDDATA BYTE_REF(PDDATA_ADDR)
427 #define PDPUEN BYTE_REF(PDPUEN_ADDR)
428 #define PDSEL BYTE_REF(PDSEL_ADDR)
429 #define PDPOL BYTE_REF(PDPOL_ADDR)
430 #define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
431 #define PDKBEN BYTE_REF(PDKBEN_ADDR)
432 #define PDIQEG BYTE_REF(PDIQEG_ADDR)
433
434 #define PD(x) (1 << (x))
435
436 #define PD_INT0 0x01 /* Use INT0 as PD[0] */
437 #define PD_INT1 0x02 /* Use INT1 as PD[1] */
438 #define PD_INT2 0x04 /* Use INT2 as PD[2] */
439 #define PD_INT3 0x08 /* Use INT3 as PD[3] */
440 #define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */
441 #define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */
442 #define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */
443 #define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */
444
445 /*
446 * Port E
447 */
448 #define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
449 #define PEDATA_ADDR 0xfffff421 /* Port E data register */
450 #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
451 #define PESEL_ADDR 0xfffff423 /* Port E Select Register */
452
453 #define PEDIR BYTE_REF(PEDIR_ADDR)
454 #define PEDATA BYTE_REF(PEDATA_ADDR)
455 #define PEPUEN BYTE_REF(PEPUEN_ADDR)
456 #define PESEL BYTE_REF(PESEL_ADDR)
457
458 #define PE(x) (1 << (x))
459
460 #define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */
461 #define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */
462 #define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */
463 #define PE_DWE 0x08 /* Use DWE as PE[3] */
464 #define PE_RXD 0x10 /* Use RXD as PE[4] */
465 #define PE_TXD 0x20 /* Use TXD as PE[5] */
466 #define PE_RTS 0x40 /* Use RTS as PE[6] */
467 #define PE_CTS 0x80 /* Use CTS as PE[7] */
468
469 /*
470 * Port F
471 */
472 #define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
473 #define PFDATA_ADDR 0xfffff429 /* Port F data register */
474 #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
475 #define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
476
477 #define PFDIR BYTE_REF(PFDIR_ADDR)
478 #define PFDATA BYTE_REF(PFDATA_ADDR)
479 #define PFPUEN BYTE_REF(PFPUEN_ADDR)
480 #define PFSEL BYTE_REF(PFSEL_ADDR)
481
482 #define PF(x) (1 << (x))
483
484 #define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */
485 #define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */
486 #define PF_CLKO 0x04 /* Use CLKO as PF[2] */
487 #define PF_A20 0x08 /* Use A20 as PF[3] */
488 #define PF_A21 0x10 /* Use A21 as PF[4] */
489 #define PF_A22 0x20 /* Use A22 as PF[5] */
490 #define PF_A23 0x40 /* Use A23 as PF[6] */
491 #define PF_CSA1 0x80 /* Use CSA1 as PF[7] */
492
493 /*
494 * Port G
495 */
496 #define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
497 #define PGDATA_ADDR 0xfffff431 /* Port G data register */
498 #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
499 #define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
500
501 #define PGDIR BYTE_REF(PGDIR_ADDR)
502 #define PGDATA BYTE_REF(PGDATA_ADDR)
503 #define PGPUEN BYTE_REF(PGPUEN_ADDR)
504 #define PGSEL BYTE_REF(PGSEL_ADDR)
505
506 #define PG(x) (1 << (x))
507
508 #define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */
509 #define PG_A0 0x02 /* Use A0 as PG[1] */
510 #define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */
511 #define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */
512 #define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */
513 #define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */
514
515 /*
516 * Port J
517 */
518 #define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
519 #define PJDATA_ADDR 0xfffff439 /* Port J data register */
520 #define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enb. reg */
521 #define PJSEL_ADDR 0xfffff43B /* Port J Select Register */
522
523 #define PJDIR BYTE_REF(PJDIR_ADDR)
524 #define PJDATA BYTE_REF(PJDATA_ADDR)
525 #define PJPUEN BYTE_REF(PJPUEN_ADDR)
526 #define PJSEL BYTE_REF(PJSEL_ADDR)
527
528 #define PJ(x) (1 << (x))
529
530 /*
531 * Port K
532 */
533 #define PKDIR_ADDR 0xfffff440 /* Port K direction reg */
534 #define PKDATA_ADDR 0xfffff441 /* Port K data register */
535 #define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enb. reg */
536 #define PKSEL_ADDR 0xfffff443 /* Port K Select Register */
537
538 #define PKDIR BYTE_REF(PKDIR_ADDR)
539 #define PKDATA BYTE_REF(PKDATA_ADDR)
540 #define PKPUEN BYTE_REF(PKPUEN_ADDR)
541 #define PKSEL BYTE_REF(PKSEL_ADDR)
542
543 #define PK(x) (1 << (x))
544
545 #define PK_DATAREADY 0x01 /* Use ~DATA_READY as PK[0] */
546 #define PK_PWM2 0x01 /* Use PWM2 as PK[0] */
547 #define PK_R_W 0x02 /* Use R/W as PK[1] */
548 #define PK_LDS 0x04 /* Use /LDS as PK[2] */
549 #define PK_UDS 0x08 /* Use /UDS as PK[3] */
550 #define PK_LD4 0x10 /* Use LD4 as PK[4] */
551 #define PK_LD5 0x20 /* Use LD5 as PK[5] */
552 #define PK_LD6 0x40 /* Use LD6 as PK[6] */
553 #define PK_LD7 0x80 /* Use LD7 as PK[7] */
554
555 #define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
556 #define PJDATA_ADDR 0xfffff439 /* Port J data register */
557 #define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enable reg */
558 #define PJSEL_ADDR 0xfffff43B /* Port J Select Register */
559
560 #define PJDIR BYTE_REF(PJDIR_ADDR)
561 #define PJDATA BYTE_REF(PJDATA_ADDR)
562 #define PJPUEN BYTE_REF(PJPUEN_ADDR)
563 #define PJSEL BYTE_REF(PJSEL_ADDR)
564
565 #define PJ(x) (1 << (x))
566
567 #define PJ_MOSI 0x01 /* Use MOSI as PJ[0] */
568 #define PJ_MISO 0x02 /* Use MISO as PJ[1] */
569 #define PJ_SPICLK1 0x04 /* Use SPICLK1 as PJ[2] */
570 #define PJ_SS 0x08 /* Use SS as PJ[3] */
571 #define PJ_RXD2 0x10 /* Use RXD2 as PJ[4] */
572 #define PJ_TXD2 0x20 /* Use TXD2 as PJ[5] */
573 #define PJ_RTS2 0x40 /* Use RTS2 as PJ[5] */
574 #define PJ_CTS2 0x80 /* Use CTS2 as PJ[5] */
575
576 /*
577 * Port M
578 */
579 #define PMDIR_ADDR 0xfffff448 /* Port M direction reg */
580 #define PMDATA_ADDR 0xfffff449 /* Port M data register */
581 #define PMPUEN_ADDR 0xfffff44a /* Port M Pull-Up enable reg */
582 #define PMSEL_ADDR 0xfffff44b /* Port M Select Register */
583
584 #define PMDIR BYTE_REF(PMDIR_ADDR)
585 #define PMDATA BYTE_REF(PMDATA_ADDR)
586 #define PMPUEN BYTE_REF(PMPUEN_ADDR)
587 #define PMSEL BYTE_REF(PMSEL_ADDR)
588
589 #define PM(x) (1 << (x))
590
591 #define PM_SDCLK 0x01 /* Use SDCLK as PM[0] */
592 #define PM_SDCE 0x02 /* Use SDCE as PM[1] */
593 #define PM_DQMH 0x04 /* Use DQMH as PM[2] */
594 #define PM_DQML 0x08 /* Use DQML as PM[3] */
595 #define PM_SDA10 0x10 /* Use SDA10 as PM[4] */
596 #define PM_DMOE 0x20 /* Use DMOE as PM[5] */
597
598 /**********
599 *
600 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
601 *
602 **********/
603
604 /*
605 * PWM Control Register
606 */
607 #define PWMC_ADDR 0xfffff500
608 #define PWMC WORD_REF(PWMC_ADDR)
609
610 #define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
611 #define PWMC_CLKSEL_SHIFT 0
612 #define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */
613 #define PWMC_REPEAT_SHIFT 2
614 #define PWMC_EN 0x0010 /* Enable PWM */
615 #define PMNC_FIFOAV 0x0020 /* FIFO Available */
616 #define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */
617 #define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */
618 #define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
619 #define PWMC_PRESCALER_SHIFT 8
620 #define PWMC_CLKSRC 0x8000 /* Clock Source Select */
621
622 /* '328-compatible definitions */
623 #define PWMC_PWMEN PWMC_EN
624
625 /*
626 * PWM Sample Register
627 */
628 #define PWMS_ADDR 0xfffff502
629 #define PWMS WORD_REF(PWMS_ADDR)
630
631 /*
632 * PWM Period Register
633 */
634 #define PWMP_ADDR 0xfffff504
635 #define PWMP BYTE_REF(PWMP_ADDR)
636
637 /*
638 * PWM Counter Register
639 */
640 #define PWMCNT_ADDR 0xfffff505
641 #define PWMCNT BYTE_REF(PWMCNT_ADDR)
642
643 /**********
644 *
645 * 0xFFFFF6xx -- General-Purpose Timer
646 *
647 **********/
648
649 /*
650 * Timer Control register
651 */
652 #define TCTL_ADDR 0xfffff600
653 #define TCTL WORD_REF(TCTL_ADDR)
654
655 #define TCTL_TEN 0x0001 /* Timer Enable */
656 #define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
657 #define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
658 #define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
659 #define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
660 #define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
661 #define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
662 #define TCTL_IRQEN 0x0010 /* IRQ Enable */
663 #define TCTL_OM 0x0020 /* Output Mode */
664 #define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
665 #define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
666 #define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
667 #define TCTL_FRR 0x0010 /* Free-Run Mode */
668
669 /* '328-compatible definitions */
670 #define TCTL1_ADDR TCTL_ADDR
671 #define TCTL1 TCTL
672
673 /*
674 * Timer Prescaler Register
675 */
676 #define TPRER_ADDR 0xfffff602
677 #define TPRER WORD_REF(TPRER_ADDR)
678
679 /* '328-compatible definitions */
680 #define TPRER1_ADDR TPRER_ADDR
681 #define TPRER1 TPRER
682
683 /*
684 * Timer Compare Register
685 */
686 #define TCMP_ADDR 0xfffff604
687 #define TCMP WORD_REF(TCMP_ADDR)
688
689 /* '328-compatible definitions */
690 #define TCMP1_ADDR TCMP_ADDR
691 #define TCMP1 TCMP
692
693 /*
694 * Timer Capture register
695 */
696 #define TCR_ADDR 0xfffff606
697 #define TCR WORD_REF(TCR_ADDR)
698
699 /* '328-compatible definitions */
700 #define TCR1_ADDR TCR_ADDR
701 #define TCR1 TCR
702
703 /*
704 * Timer Counter Register
705 */
706 #define TCN_ADDR 0xfffff608
707 #define TCN WORD_REF(TCN_ADDR)
708
709 /* '328-compatible definitions */
710 #define TCN1_ADDR TCN_ADDR
711 #define TCN1 TCN
712
713 /*
714 * Timer Status Register
715 */
716 #define TSTAT_ADDR 0xfffff60a
717 #define TSTAT WORD_REF(TSTAT_ADDR)
718
719 #define TSTAT_COMP 0x0001 /* Compare Event occurred */
720 #define TSTAT_CAPT 0x0001 /* Capture Event occurred */
721
722 /* '328-compatible definitions */
723 #define TSTAT1_ADDR TSTAT_ADDR
724 #define TSTAT1 TSTAT
725
726 /**********
727 *
728 * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
729 *
730 **********/
731
732 /*
733 * SPIM Data Register
734 */
735 #define SPIMDATA_ADDR 0xfffff800
736 #define SPIMDATA WORD_REF(SPIMDATA_ADDR)
737
738 /*
739 * SPIM Control/Status Register
740 */
741 #define SPIMCONT_ADDR 0xfffff802
742 #define SPIMCONT WORD_REF(SPIMCONT_ADDR)
743
744 #define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
745 #define SPIMCONT_BIT_COUNT_SHIFT 0
746 #define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
747 #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
748 #define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
749 #define SPIMCONT_IRQ 0x0080 /* Interrupt Request */
750 #define SPIMCONT_XCH 0x0100 /* Exchange */
751 #define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */
752 #define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
753 #define SPIMCONT_DATA_RATE_SHIFT 13
754
755 /* '328-compatible definitions */
756 #define SPIMCONT_SPIMIRQ SPIMCONT_IRQ
757 #define SPIMCONT_SPIMEN SPIMCONT_ENABLE
758
759 /**********
760 *
761 * 0xFFFFF9xx -- UART
762 *
763 **********/
764
765 /*
766 * UART Status/Control Register
767 */
768
769 #define USTCNT_ADDR 0xfffff900
770 #define USTCNT WORD_REF(USTCNT_ADDR)
771
772 #define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */
773 #define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */
774 #define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */
775 #define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */
776 #define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
777 #define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */
778 #define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */
779 #define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */
780 #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
781 #define USTCNT_STOP 0x0200 /* Stop bit transmission */
782 #define USTCNT_ODD 0x0400 /* Odd Parity */
783 #define USTCNT_PEN 0x0800 /* Parity Enable */
784 #define USTCNT_CLKM 0x1000 /* Clock Mode Select */
785 #define USTCNT_TXEN 0x2000 /* Transmitter Enable */
786 #define USTCNT_RXEN 0x4000 /* Receiver Enable */
787 #define USTCNT_UEN 0x8000 /* UART Enable */
788
789 /* '328-compatible definitions */
790 #define USTCNT_TXAVAILEN USTCNT_TXAE
791 #define USTCNT_TXHALFEN USTCNT_TXHE
792 #define USTCNT_TXEMPTYEN USTCNT_TXEE
793 #define USTCNT_RXREADYEN USTCNT_RXRE
794 #define USTCNT_RXHALFEN USTCNT_RXHE
795 #define USTCNT_RXFULLEN USTCNT_RXFE
796 #define USTCNT_CTSDELTAEN USTCNT_CTSD
797 #define USTCNT_ODD_EVEN USTCNT_ODD
798 #define USTCNT_PARITYEN USTCNT_PEN
799 #define USTCNT_CLKMODE USTCNT_CLKM
800 #define USTCNT_UARTEN USTCNT_UEN
801
802 /*
803 * UART Baud Control Register
804 */
805 #define UBAUD_ADDR 0xfffff902
806 #define UBAUD WORD_REF(UBAUD_ADDR)
807
808 #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
809 #define UBAUD_PRESCALER_SHIFT 0
810 #define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divisor */
811 #define UBAUD_DIVIDE_SHIFT 8
812 #define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
813 #define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
814
815 /*
816 * UART Receiver Register
817 */
818 #define URX_ADDR 0xfffff904
819 #define URX WORD_REF(URX_ADDR)
820
821 #define URX_RXDATA_ADDR 0xfffff905
822 #define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
823
824 #define URX_RXDATA_MASK 0x00ff /* Received data */
825 #define URX_RXDATA_SHIFT 0
826 #define URX_PARITY_ERROR 0x0100 /* Parity Error */
827 #define URX_BREAK 0x0200 /* Break Detected */
828 #define URX_FRAME_ERROR 0x0400 /* Framing Error */
829 #define URX_OVRUN 0x0800 /* Serial Overrun */
830 #define URX_OLD_DATA 0x1000 /* Old data in FIFO */
831 #define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
832 #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
833 #define URX_FIFO_FULL 0x8000 /* FIFO is Full */
834
835 /*
836 * UART Transmitter Register
837 */
838 #define UTX_ADDR 0xfffff906
839 #define UTX WORD_REF(UTX_ADDR)
840
841 #define UTX_TXDATA_ADDR 0xfffff907
842 #define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
843
844 #define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
845 #define UTX_TXDATA_SHIFT 0
846 #define UTX_CTS_DELTA 0x0100 /* CTS changed */
847 #define UTX_CTS_STAT 0x0200 /* CTS State */
848 #define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */
849 #define UTX_NOCTS 0x0800 /* Ignore CTS */
850 #define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
851 #define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
852 #define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
853 #define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
854
855 /* '328-compatible definitions */
856 #define UTX_CTS_STATUS UTX_CTS_STAT
857 #define UTX_IGNORE_CTS UTX_NOCTS
858
859 /*
860 * UART Miscellaneous Register
861 */
862 #define UMISC_ADDR 0xfffff908
863 #define UMISC WORD_REF(UMISC_ADDR)
864
865 #define UMISC_TX_POL 0x0004 /* Transmit Polarity */
866 #define UMISC_RX_POL 0x0008 /* Receive Polarity */
867 #define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
868 #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
869 #define UMISC_RTS 0x0040 /* Set RTS status */
870 #define UMISC_RTSCONT 0x0080 /* Choose RTS control */
871 #define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */
872 #define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */
873 #define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
874 #define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
875 #define UMISC_CLKSRC 0x4000 /* Clock Source */
876 #define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */
877
878 /*
879 * UART Non-integer Prescaler Register
880 */
881 #define NIPR_ADDR 0xfffff90a
882 #define NIPR WORD_REF(NIPR_ADDR)
883
884 #define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */
885 #define NIPR_STEP_VALUE_SHIFT 0
886 #define NIPR_SELECT_MASK 0x0700 /* Tap Selection */
887 #define NIPR_SELECT_SHIFT 8
888 #define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
889
890
891 /* generalization of uart control registers to support multiple ports: */
892 typedef struct {
893 volatile unsigned short int ustcnt;
894 volatile unsigned short int ubaud;
895 union {
896 volatile unsigned short int w;
897 struct {
898 volatile unsigned char status;
899 volatile unsigned char rxdata;
900 } b;
901 } urx;
902 union {
903 volatile unsigned short int w;
904 struct {
905 volatile unsigned char status;
906 volatile unsigned char txdata;
907 } b;
908 } utx;
909 volatile unsigned short int umisc;
910 volatile unsigned short int nipr;
911 volatile unsigned short int hmark;
912 volatile unsigned short int unused;
913 } __packed m68328_uart;
914
915
916
917
918 /**********
919 *
920 * 0xFFFFFAxx -- LCD Controller
921 *
922 **********/
923
924 /*
925 * LCD Screen Starting Address Register
926 */
927 #define LSSA_ADDR 0xfffffa00
928 #define LSSA LONG_REF(LSSA_ADDR)
929
930 #define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
931
932 /*
933 * LCD Virtual Page Width Register
934 */
935 #define LVPW_ADDR 0xfffffa05
936 #define LVPW BYTE_REF(LVPW_ADDR)
937
938 /*
939 * LCD Screen Width Register (not compatible with '328 !!!)
940 */
941 #define LXMAX_ADDR 0xfffffa08
942 #define LXMAX WORD_REF(LXMAX_ADDR)
943
944 #define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
945
946 /*
947 * LCD Screen Height Register
948 */
949 #define LYMAX_ADDR 0xfffffa0a
950 #define LYMAX WORD_REF(LYMAX_ADDR)
951
952 #define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
953
954 /*
955 * LCD Cursor X Position Register
956 */
957 #define LCXP_ADDR 0xfffffa18
958 #define LCXP WORD_REF(LCXP_ADDR)
959
960 #define LCXP_CC_MASK 0xc000 /* Cursor Control */
961 #define LCXP_CC_TRAMSPARENT 0x0000
962 #define LCXP_CC_BLACK 0x4000
963 #define LCXP_CC_REVERSED 0x8000
964 #define LCXP_CC_WHITE 0xc000
965 #define LCXP_CXP_MASK 0x02ff /* Cursor X position */
966
967 /*
968 * LCD Cursor Y Position Register
969 */
970 #define LCYP_ADDR 0xfffffa1a
971 #define LCYP WORD_REF(LCYP_ADDR)
972
973 #define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
974
975 /*
976 * LCD Cursor Width and Heigth Register
977 */
978 #define LCWCH_ADDR 0xfffffa1c
979 #define LCWCH WORD_REF(LCWCH_ADDR)
980
981 #define LCWCH_CH_MASK 0x001f /* Cursor Height */
982 #define LCWCH_CH_SHIFT 0
983 #define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
984 #define LCWCH_CW_SHIFT 8
985
986 /*
987 * LCD Blink Control Register
988 */
989 #define LBLKC_ADDR 0xfffffa1f
990 #define LBLKC BYTE_REF(LBLKC_ADDR)
991
992 #define LBLKC_BD_MASK 0x7f /* Blink Divisor */
993 #define LBLKC_BD_SHIFT 0
994 #define LBLKC_BKEN 0x80 /* Blink Enabled */
995
996 /*
997 * LCD Panel Interface Configuration Register
998 */
999 #define LPICF_ADDR 0xfffffa20
1000 #define LPICF BYTE_REF(LPICF_ADDR)
1001
1002 #define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
1003 #define LPICF_GS_BW 0x00
1004 #define LPICF_GS_GRAY_4 0x01
1005 #define LPICF_GS_GRAY_16 0x02
1006 #define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */
1007 #define LPICF_PBSIZ_1 0x00
1008 #define LPICF_PBSIZ_2 0x04
1009 #define LPICF_PBSIZ_4 0x08
1010
1011 /*
1012 * LCD Polarity Configuration Register
1013 */
1014 #define LPOLCF_ADDR 0xfffffa21
1015 #define LPOLCF BYTE_REF(LPOLCF_ADDR)
1016
1017 #define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
1018 #define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
1019 #define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
1020 #define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
1021
1022 /*
1023 * LACD (LCD Alternate Crystal Direction) Rate Control Register
1024 */
1025 #define LACDRC_ADDR 0xfffffa23
1026 #define LACDRC BYTE_REF(LACDRC_ADDR)
1027
1028 #define LACDRC_ACDSLT 0x80 /* Signal Source Select */
1029 #define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
1030 #define LACDRC_ACD_SHIFT 0
1031
1032 /*
1033 * LCD Pixel Clock Divider Register
1034 */
1035 #define LPXCD_ADDR 0xfffffa25
1036 #define LPXCD BYTE_REF(LPXCD_ADDR)
1037
1038 #define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
1039 #define LPXCD_PCD_SHIFT 0
1040
1041 /*
1042 * LCD Clocking Control Register
1043 */
1044 #define LCKCON_ADDR 0xfffffa27
1045 #define LCKCON BYTE_REF(LCKCON_ADDR)
1046
1047 #define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
1048 #define LCKCON_DWS_SHIFT 0
1049 #define LCKCON_DWIDTH 0x40 /* Display Memory Width */
1050 #define LCKCON_LCDON 0x80 /* Enable LCD Controller */
1051
1052 /* '328-compatible definitions */
1053 #define LCKCON_DW_MASK LCKCON_DWS_MASK
1054 #define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
1055
1056 /*
1057 * LCD Refresh Rate Adjustment Register
1058 */
1059 #define LRRA_ADDR 0xfffffa29
1060 #define LRRA BYTE_REF(LRRA_ADDR)
1061
1062 /*
1063 * LCD Panning Offset Register
1064 */
1065 #define LPOSR_ADDR 0xfffffa2d
1066 #define LPOSR BYTE_REF(LPOSR_ADDR)
1067
1068 #define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */
1069 #define LPOSR_POS_SHIFT 0
1070
1071 /*
1072 * LCD Frame Rate Control Modulation Register
1073 */
1074 #define LFRCM_ADDR 0xfffffa31
1075 #define LFRCM BYTE_REF(LFRCM_ADDR)
1076
1077 #define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
1078 #define LFRCM_YMOD_SHIFT 0
1079 #define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
1080 #define LFRCM_XMOD_SHIFT 4
1081
1082 /*
1083 * LCD Gray Palette Mapping Register
1084 */
1085 #define LGPMR_ADDR 0xfffffa33
1086 #define LGPMR BYTE_REF(LGPMR_ADDR)
1087
1088 #define LGPMR_G1_MASK 0x0f
1089 #define LGPMR_G1_SHIFT 0
1090 #define LGPMR_G2_MASK 0xf0
1091 #define LGPMR_G2_SHIFT 4
1092
1093 /*
1094 * PWM Contrast Control Register
1095 */
1096 #define PWMR_ADDR 0xfffffa36
1097 #define PWMR WORD_REF(PWMR_ADDR)
1098
1099 #define PWMR_PW_MASK 0x00ff /* Pulse Width */
1100 #define PWMR_PW_SHIFT 0
1101 #define PWMR_CCPEN 0x0100 /* Contrast Control Enable */
1102 #define PWMR_SRC_MASK 0x0600 /* Input Clock Source */
1103 #define PWMR_SRC_LINE 0x0000 /* Line Pulse */
1104 #define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */
1105 #define PWMR_SRC_LCD 0x4000 /* LCD clock */
1106
1107 /**********
1108 *
1109 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1110 *
1111 **********/
1112
1113 /*
1114 * RTC Hours Minutes and Seconds Register
1115 */
1116 #define RTCTIME_ADDR 0xfffffb00
1117 #define RTCTIME LONG_REF(RTCTIME_ADDR)
1118
1119 #define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
1120 #define RTCTIME_SECONDS_SHIFT 0
1121 #define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
1122 #define RTCTIME_MINUTES_SHIFT 16
1123 #define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
1124 #define RTCTIME_HOURS_SHIFT 24
1125
1126 /*
1127 * RTC Alarm Register
1128 */
1129 #define RTCALRM_ADDR 0xfffffb04
1130 #define RTCALRM LONG_REF(RTCALRM_ADDR)
1131
1132 #define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
1133 #define RTCALRM_SECONDS_SHIFT 0
1134 #define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
1135 #define RTCALRM_MINUTES_SHIFT 16
1136 #define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
1137 #define RTCALRM_HOURS_SHIFT 24
1138
1139 /*
1140 * Watchdog Timer Register
1141 */
1142 #define WATCHDOG_ADDR 0xfffffb0a
1143 #define WATCHDOG WORD_REF(WATCHDOG_ADDR)
1144
1145 #define WATCHDOG_EN 0x0001 /* Watchdog Enabled */
1146 #define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */
1147 #define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occurred */
1148 #define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */
1149 #define WATCHDOG_CNT_SHIFT 8
1150
1151 /*
1152 * RTC Control Register
1153 */
1154 #define RTCCTL_ADDR 0xfffffb0c
1155 #define RTCCTL WORD_REF(RTCCTL_ADDR)
1156
1157 #define RTCCTL_XTL 0x0020 /* Crystal Selection */
1158 #define RTCCTL_EN 0x0080 /* RTC Enable */
1159
1160 /* '328-compatible definitions */
1161 #define RTCCTL_384 RTCCTL_XTL
1162 #define RTCCTL_ENABLE RTCCTL_EN
1163
1164 /*
1165 * RTC Interrupt Status Register
1166 */
1167 #define RTCISR_ADDR 0xfffffb0e
1168 #define RTCISR WORD_REF(RTCISR_ADDR)
1169
1170 #define RTCISR_SW 0x0001 /* Stopwatch timed out */
1171 #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
1172 #define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
1173 #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
1174 #define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
1175 #define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
1176 #define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */
1177 #define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */
1178 #define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */
1179 #define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */
1180 #define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */
1181 #define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */
1182 #define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */
1183 #define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */
1184
1185 /*
1186 * RTC Interrupt Enable Register
1187 */
1188 #define RTCIENR_ADDR 0xfffffb10
1189 #define RTCIENR WORD_REF(RTCIENR_ADDR)
1190
1191 #define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
1192 #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
1193 #define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
1194 #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
1195 #define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
1196 #define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
1197 #define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */
1198 #define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */
1199 #define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */
1200 #define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */
1201 #define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */
1202 #define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */
1203 #define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */
1204 #define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */
1205
1206 /*
1207 * Stopwatch Minutes Register
1208 */
1209 #define STPWCH_ADDR 0xfffffb12
1210 #define STPWCH WORD_REF(STPWCH_ADDR)
1211
1212 #define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */
1213 #define SPTWCH_CNT_SHIFT 0
1214
1215 /*
1216 * RTC Day Count Register
1217 */
1218 #define DAYR_ADDR 0xfffffb1a
1219 #define DAYR WORD_REF(DAYR_ADDR)
1220
1221 #define DAYR_DAYS_MASK 0x1ff /* Day Setting */
1222 #define DAYR_DAYS_SHIFT 0
1223
1224 /*
1225 * RTC Day Alarm Register
1226 */
1227 #define DAYALARM_ADDR 0xfffffb1c
1228 #define DAYALARM WORD_REF(DAYALARM_ADDR)
1229
1230 #define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */
1231 #define DAYALARM_DAYSAL_SHIFT 0
1232
1233 /**********
1234 *
1235 * 0xFFFFFCxx -- DRAM Controller
1236 *
1237 **********/
1238
1239 /*
1240 * DRAM Memory Configuration Register
1241 */
1242 #define DRAMMC_ADDR 0xfffffc00
1243 #define DRAMMC WORD_REF(DRAMMC_ADDR)
1244
1245 #define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */
1246 #define DRAMMC_ROW12_PA10 0x0000
1247 #define DRAMMC_ROW12_PA21 0x4000
1248 #define DRAMMC_ROW12_PA23 0x8000
1249 #define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */
1250 #define DRAMMC_ROW0_PA11 0x0000
1251 #define DRAMMC_ROW0_PA22 0x1000
1252 #define DRAMMC_ROW0_PA23 0x2000
1253 #define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */
1254 #define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */
1255 #define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */
1256 #define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */
1257 #define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */
1258 #define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */
1259 #define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */
1260 #define DRAMMC_REF_MASK 0x001f /* Refresh Cycle */
1261 #define DRAMMC_REF_SHIFT 0
1262
1263 /*
1264 * DRAM Control Register
1265 */
1266 #define DRAMC_ADDR 0xfffffc02
1267 #define DRAMC WORD_REF(DRAMC_ADDR)
1268
1269 #define DRAMC_DWE 0x0001 /* DRAM Write Enable */
1270 #define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */
1271 #define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
1272 #define DRAMC_SLW 0x0008 /* Slow RAM */
1273 #define DRAMC_LSP 0x0010 /* Light Sleep */
1274 #define DRAMC_MSW 0x0020 /* Slow Multiplexing */
1275 #define DRAMC_WS_MASK 0x00c0 /* Wait-states */
1276 #define DRAMC_WS_SHIFT 6
1277 #define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */
1278 #define DRAMC_PGSZ_SHIFT 8
1279 #define DRAMC_PGSZ_256K 0x0000
1280 #define DRAMC_PGSZ_512K 0x0100
1281 #define DRAMC_PGSZ_1024K 0x0200
1282 #define DRAMC_PGSZ_2048K 0x0300
1283 #define DRAMC_EDO 0x0400 /* EDO DRAM */
1284 #define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */
1285 #define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */
1286 #define DRAMC_BC_SHIFT 12
1287 #define DRAMC_RM 0x4000 /* Refresh Mode */
1288 #define DRAMC_EN 0x8000 /* DRAM Controller enable */
1289
1290
1291 /**********
1292 *
1293 * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
1294 *
1295 **********/
1296
1297 /*
1298 * ICE Module Address Compare Register
1299 */
1300 #define ICEMACR_ADDR 0xfffffd00
1301 #define ICEMACR LONG_REF(ICEMACR_ADDR)
1302
1303 /*
1304 * ICE Module Address Mask Register
1305 */
1306 #define ICEMAMR_ADDR 0xfffffd04
1307 #define ICEMAMR LONG_REF(ICEMAMR_ADDR)
1308
1309 /*
1310 * ICE Module Control Compare Register
1311 */
1312 #define ICEMCCR_ADDR 0xfffffd08
1313 #define ICEMCCR WORD_REF(ICEMCCR_ADDR)
1314
1315 #define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */
1316 #define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */
1317
1318 /*
1319 * ICE Module Control Mask Register
1320 */
1321 #define ICEMCMR_ADDR 0xfffffd0a
1322 #define ICEMCMR WORD_REF(ICEMCMR_ADDR)
1323
1324 #define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */
1325 #define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */
1326
1327 /*
1328 * ICE Module Control Register
1329 */
1330 #define ICEMCR_ADDR 0xfffffd0c
1331 #define ICEMCR WORD_REF(ICEMCR_ADDR)
1332
1333 #define ICEMCR_CEN 0x0001 /* Compare Enable */
1334 #define ICEMCR_PBEN 0x0002 /* Program Break Enable */
1335 #define ICEMCR_SB 0x0004 /* Single Breakpoint */
1336 #define ICEMCR_HMDIS 0x0008 /* HardMap disable */
1337 #define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */
1338
1339 /*
1340 * ICE Module Status Register
1341 */
1342 #define ICEMSR_ADDR 0xfffffd0e
1343 #define ICEMSR WORD_REF(ICEMSR_ADDR)
1344
1345 #define ICEMSR_EMUEN 0x0001 /* Emulation Enable */
1346 #define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */
1347 #define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */
1348 #define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */
1349
1350 #endif /* _MC68VZ328_H_ */
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