arch/m68k/include/asm/cache.h

   1 /*
   2  * ColdFire cache
   3  *
   4  * Copyright 2004-2012 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef __CACHE_H
  27 #define __CACHE_H
  28
  29 #if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
  30     defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x)
  31 #define CONFIG_CF_V2
  32 #endif
  33
  34 #if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x)
  35 #define CONFIG_CF_V3
  36 #endif
  37
  38 #if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
  39 #define CONFIG_CF_V4
  40 #elif defined(CONFIG_MCF5441x)
  41 #define CONFIG_CF_V4E           /* Four Extra ACRn */
  42 #endif
  43
  44 /* ***** CACR ***** */
  45 /* V2 Core */
  46 #ifdef CONFIG_CF_V2
  47
  48 #define CF_CACR_CENB            (1 << 31)
  49 #define CF_CACR_CPD             (1 << 28)
  50 #define CF_CACR_CFRZ            (1 << 27)
  51 #define CF_CACR_CEIB            (1 << 10)
  52 #define CF_CACR_DCM             (1 << 9)
  53 #define CF_CACR_DBWE            (1 << 8)
  54
  55 #if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253)
  56 #define CF_CACR_DWP             (1 << 6)
  57 #else
  58 #define CF_CACR_CINV            (1 << 24)
  59 #define CF_CACR_DISI            (1 << 23)
  60 #define CF_CACR_DISD            (1 << 22)
  61 #define CF_CACR_INVI            (1 << 21)
  62 #define CF_CACR_INVD            (1 << 20)
  63 #define CF_CACR_DWP             (1 << 5)
  64 #define CF_CACR_EUSP            (1 << 4)
  65 #endif                          /* CONFIG_MCF5249 || CONFIG_MCF5253 */
  66
  67 #endif                          /* CONFIG_CF_V2 */
  68
  69 /* V3 Core */
  70 #ifdef CONFIG_CF_V3
  71
  72 #define CF_CACR_EC              (1 << 31)
  73 #define CF_CACR_ESB             (1 << 29)
  74 #define CF_CACR_DPI             (1 << 28)
  75 #define CF_CACR_HLCK            (1 << 27)
  76 #define CF_CACR_CINVA           (1 << 24)
  77 #define CF_CACR_DNFB            (1 << 10)
  78 #define CF_CACR_DCM_UNMASK      0xFFFFFCFF
  79 #define CF_CACR_DCM_WT          (0 << 8)
  80 #define CF_CACR_DCM_CB          (1 << 8)
  81 #define CF_CACR_DCM_P           (2 << 8)
  82 #define CF_CACR_DCM_IP          (3 << 8)
  83 #define CF_CACR_DW              (1 << 5)
  84 #define CF_CACR_EUSP            (1 << 4)
  85
  86 #endif                          /* CONFIG_CF_V3 */
  87
  88 /* V4 Core */
  89 #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
  90
  91 #define CF_CACR_DEC             (1 << 31)
  92 #define CF_CACR_DW              (1 << 30)
  93 #define CF_CACR_DESB            (1 << 29)
  94 #define CF_CACR_DDPI            (1 << 28)
  95 #define CF_CACR_DHLCK           (1 << 27)
  96 #define CF_CACR_DDCM_UNMASK     (0xF9FFFFFF)
  97 #define CF_CACR_DDCM_WT         (0 << 25)
  98 #define CF_CACR_DDCM_CB         (1 << 25)
  99 #define CF_CACR_DDCM_P          (2 << 25)
 100 #define CF_CACR_DDCM_IP         (3 << 25)
 101 #define CF_CACR_DCINVA          (1 << 24)
 102
 103 #define CF_CACR_DDSP            (1 << 23)
 104 #define CF_CACR_BEC             (1 << 19)
 105 #define CF_CACR_BCINVA          (1 << 18)
 106 #define CF_CACR_IEC             (1 << 15)
 107 #define CF_CACR_DNFB            (1 << 13)
 108 #define CF_CACR_IDPI            (1 << 12)
 109 #define CF_CACR_IHLCK           (1 << 11)
 110 #define CF_CACR_IDCM            (1 << 10)
 111 #define CF_CACR_ICINVA          (1 << 8)
 112 #define CF_CACR_IDSP            (1 << 7)
 113 #define CF_CACR_EUSP            (1 << 5)
 114
 115 #if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x)
 116 #define CF_CACR_IVO             (1 << 20)
 117 #define CF_CACR_SPA             (1 << 14)
 118 #else
 119 #define CF_CACR_DF              (1 << 4)
 120 #endif
 121
 122 #endif                          /* CONFIG_CF_V4 */
 123
 124 /* ***** ACR ***** */
 125 #define CF_ACR_ADR_UNMASK       (0x00FFFFFF)
 126 #define CF_ACR_ADR(x)           ((x & 0xFF) << 24)
 127 #define CF_ACR_ADRMSK_UNMASK    (0xFF00FFFF)
 128 #define CF_ACR_ADRMSK(x)        ((x & 0xFF) << 16)
 129 #define CF_ACR_EN               (1 << 15)
 130 #define CF_ACR_SM_UNMASK        (0xFFFF9FFF)
 131 #define CF_ACR_SM_UM            (0 << 13)
 132 #define CF_ACR_SM_SM            (1 << 13)
 133 #define CF_ACR_SM_ALL           (3 << 13)
 134 #define CF_ACR_WP               (1 << 2)
 135
 136 /* V2 Core */
 137 #ifdef CONFIG_CF_V2
 138 #define CF_ACR_CM               (1 << 6)
 139 #define CF_ACR_BWE              (1 << 5)
 140 #else
 141 /* V3 & V4 */
 142 #define CF_ACR_CM_UNMASK        (0xFFFFFF9F)
 143 #define CF_ACR_CM_WT            (0 << 5)
 144 #define CF_ACR_CM_CB            (1 << 5)
 145 #define CF_ACR_CM_P             (2 << 5)
 146 #define CF_ACR_CM_IP            (3 << 5)
 147 #endif                          /* CONFIG_CF_V2 */
 148
 149 /* V4 Core */
 150 #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
 151 #define CF_ACR_AMM              (1 << 10)
 152 #define CF_ACR_SP               (1 << 3)
 153 #endif                          /* CONFIG_CF_V4 */
 154
 155
 156 #ifndef CONFIG_SYS_CACHE_ICACR
 157 #define CONFIG_SYS_CACHE_ICACR  0
 158 #endif
 159
 160 #ifndef CONFIG_SYS_CACHE_DCACR
 161 #ifdef CONFIG_SYS_CACHE_ICACR
 162 #define CONFIG_SYS_CACHE_DCACR  CONFIG_SYS_CACHE_ICACR
 163 #else
 164 #define CONFIG_SYS_CACHE_DCACR  0
 165 #endif
 166 #endif
 167
 168 #ifndef CONFIG_SYS_CACHE_ACR0
 169 #define CONFIG_SYS_CACHE_ACR0   0
 170 #endif
 171
 172 #ifndef CONFIG_SYS_CACHE_ACR1
 173 #define CONFIG_SYS_CACHE_ACR1   0
 174 #endif
 175
 176 #ifndef CONFIG_SYS_CACHE_ACR2
 177 #define CONFIG_SYS_CACHE_ACR2   0
 178 #endif
 179
 180 #ifndef CONFIG_SYS_CACHE_ACR3
 181 #define CONFIG_SYS_CACHE_ACR3   0
 182 #endif
 183
 184 #ifndef CONFIG_SYS_CACHE_ACR4
 185 #define CONFIG_SYS_CACHE_ACR4   0
 186 #endif
 187
 188 #ifndef CONFIG_SYS_CACHE_ACR5
 189 #define CONFIG_SYS_CACHE_ACR5   0
 190 #endif
 191
 192 #ifndef CONFIG_SYS_CACHE_ACR6
 193 #define CONFIG_SYS_CACHE_ACR6   0
 194 #endif
 195
 196 #ifndef CONFIG_SYS_CACHE_ACR7
 197 #define CONFIG_SYS_CACHE_ACR7   0
 198 #endif
 199
 200 #define CF_ADDRMASK(x)          (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16)
 201
 202 #ifndef __ASSEMBLY__            /* put C only stuff in this section */
 203
 204 void icache_invalid(void);
 205 void dcache_invalid(void);
 206
 207 #endif
 208
 209 /*
 210  * m68k uses 16 byte L1 data cache line sizes.  Use this for DMA buffer
 211  * alignment unless the board configuration has specified a new value.
 212  */
 213 #ifdef CONFIG_SYS_CACHELINE_SIZE
 214 #define ARCH_DMA_MINALIGN       CONFIG_SYS_CACHELINE_SIZE
 215 #else
 216 #define ARCH_DMA_MINALIGN       16
 217 #endif
 218
 219 #endif                          /* __CACHE_H */