arch/m68k/include/asm/coldfire/edma.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * EDMA Internal Memory Map
   4  *
   5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 #ifndef __EDMA_H__
  10 #define __EDMA_H__
  11
  12 /*********************************************************************
  13 * Enhanced DMA (EDMA)
  14 *********************************************************************/
  15
  16 /* eDMA module registers */
  17 typedef struct edma_ctrl {
  18         u32 cr;                 /* 0x00 Control Register */
  19         u32 es;                 /* 0x04 Error Status Register */
  20         u16 res1[3];            /* 0x08 - 0x0D */
  21         u16 erq;                /* 0x0E Enable Request Register */
  22         u16 res2[3];            /* 0x10 - 0x15 */
  23         u16 eei;                /* 0x16 Enable Error Interrupt Request */
  24         u8 serq;                /* 0x18 Set Enable Request */
  25         u8 cerq;                /* 0x19 Clear Enable Request */
  26         u8 seei;                /* 0x1A Set En Error Interrupt Request */
  27         u8 ceei;                /* 0x1B Clear En Error Interrupt Request */
  28         u8 cint;                /* 0x1C Clear Interrupt Enable */
  29         u8 cerr;                /* 0x1D Clear Error */
  30         u8 ssrt;                /* 0x1E Set START Bit */
  31         u8 cdne;                /* 0x1F Clear DONE Status Bit */
  32         u16 res3[3];            /* 0x20 - 0x25 */
  33         u16 intr;               /* 0x26 Interrupt Request */
  34         u16 res4[3];            /* 0x28 - 0x2D */
  35         u16 err;                /* 0x2E Error Register */
  36         u32 res5[52];           /* 0x30 - 0xFF */
  37         u8 dchpri0;             /* 0x100 Channel 0 Priority */
  38         u8 dchpri1;             /* 0x101 Channel 1 Priority */
  39         u8 dchpri2;             /* 0x102 Channel 2 Priority */
  40         u8 dchpri3;             /* 0x103 Channel 3 Priority */
  41         u8 dchpri4;             /* 0x104 Channel 4 Priority */
  42         u8 dchpri5;             /* 0x105 Channel 5 Priority */
  43         u8 dchpri6;             /* 0x106 Channel 6 Priority */
  44         u8 dchpri7;             /* 0x107 Channel 7 Priority */
  45         u8 dchpri8;             /* 0x108 Channel 8 Priority */
  46         u8 dchpri9;             /* 0x109 Channel 9 Priority */
  47         u8 dchpri10;            /* 0x110 Channel 10 Priority */
  48         u8 dchpri11;            /* 0x111 Channel 11 Priority */
  49         u8 dchpri12;            /* 0x112 Channel 12 Priority */
  50         u8 dchpri13;            /* 0x113 Channel 13 Priority */
  51         u8 dchpri14;            /* 0x114 Channel 14 Priority */
  52         u8 dchpri15;            /* 0x115 Channel 15 Priority */
  53 } edma_t;
  54
  55 /* TCD - eDMA*/
  56 typedef struct tcd_ctrl {
  57         u32 saddr;              /* 0x00 Source Address */
  58         u16 attr;               /* 0x04 Transfer Attributes */
  59         u16 soff;               /* 0x06 Signed Source Address Offset */
  60         u32 nbytes;             /* 0x08 Minor Byte Count */
  61         u32 slast;              /* 0x0C Last Source Address Adjustment */
  62         u32 daddr;              /* 0x10 Destination address */
  63         u16 citer;              /* 0x14 Cur Minor Loop Link, Major Loop Cnt */
  64         u16 doff;               /* 0x16 Signed Destination Address Offset */
  65         u32 dlast_sga;          /* 0x18 Last Dest Adr Adj/Scatter Gather Adr */
  66         u16 biter;              /* 0x1C Minor Loop Lnk, Major Loop Cnt */
  67         u16 csr;                /* 0x1E Control and Status */
  68 } tcd_st;
  69
  70 typedef struct tcd_multiple {
  71         tcd_st tcd[16];
  72 } tcd_t;
  73
  74 /* Bit definitions and macros for EPPAR */
  75 #define EPORT_EPPAR_EPPA1(x)            (((x)&0x0003)<<2)
  76 #define EPORT_EPPAR_EPPA2(x)            (((x)&0x0003)<<4)
  77 #define EPORT_EPPAR_EPPA3(x)            (((x)&0x0003)<<6)
  78 #define EPORT_EPPAR_EPPA4(x)            (((x)&0x0003)<<8)
  79 #define EPORT_EPPAR_EPPA5(x)            (((x)&0x0003)<<10)
  80 #define EPORT_EPPAR_EPPA6(x)            (((x)&0x0003)<<12)
  81 #define EPORT_EPPAR_EPPA7(x)            (((x)&0x0003)<<14)
  82 #define EPORT_EPPAR_LEVEL               (0)
  83 #define EPORT_EPPAR_RISING              (1)
  84 #define EPORT_EPPAR_FALLING             (2)
  85 #define EPORT_EPPAR_BOTH                (3)
  86 #define EPORT_EPPAR_EPPA7_LEVEL         (0x0000)
  87 #define EPORT_EPPAR_EPPA7_RISING        (0x4000)
  88 #define EPORT_EPPAR_EPPA7_FALLING       (0x8000)
  89 #define EPORT_EPPAR_EPPA7_BOTH          (0xC000)
  90 #define EPORT_EPPAR_EPPA6_LEVEL         (0x0000)
  91 #define EPORT_EPPAR_EPPA6_RISING        (0x1000)
  92 #define EPORT_EPPAR_EPPA6_FALLING       (0x2000)
  93 #define EPORT_EPPAR_EPPA6_BOTH          (0x3000)
  94 #define EPORT_EPPAR_EPPA5_LEVEL         (0x0000)
  95 #define EPORT_EPPAR_EPPA5_RISING        (0x0400)
  96 #define EPORT_EPPAR_EPPA5_FALLING       (0x0800)
  97 #define EPORT_EPPAR_EPPA5_BOTH          (0x0C00)
  98 #define EPORT_EPPAR_EPPA4_LEVEL         (0x0000)
  99 #define EPORT_EPPAR_EPPA4_RISING        (0x0100)
 100 #define EPORT_EPPAR_EPPA4_FALLING       (0x0200)
 101 #define EPORT_EPPAR_EPPA4_BOTH          (0x0300)
 102 #define EPORT_EPPAR_EPPA3_LEVEL         (0x0000)
 103 #define EPORT_EPPAR_EPPA3_RISING        (0x0040)
 104 #define EPORT_EPPAR_EPPA3_FALLING       (0x0080)
 105 #define EPORT_EPPAR_EPPA3_BOTH          (0x00C0)
 106 #define EPORT_EPPAR_EPPA2_LEVEL         (0x0000)
 107 #define EPORT_EPPAR_EPPA2_RISING        (0x0010)
 108 #define EPORT_EPPAR_EPPA2_FALLING       (0x0020)
 109 #define EPORT_EPPAR_EPPA2_BOTH          (0x0030)
 110 #define EPORT_EPPAR_EPPA1_LEVEL         (0x0000)
 111 #define EPORT_EPPAR_EPPA1_RISING        (0x0004)
 112 #define EPORT_EPPAR_EPPA1_FALLING       (0x0008)
 113 #define EPORT_EPPAR_EPPA1_BOTH          (0x000C)
 114
 115 /* Bit definitions and macros for EPDDR */
 116 #define EPORT_EPDDR_EPDD1               (0x02)
 117 #define EPORT_EPDDR_EPDD2               (0x04)
 118 #define EPORT_EPDDR_EPDD3               (0x08)
 119 #define EPORT_EPDDR_EPDD4               (0x10)
 120 #define EPORT_EPDDR_EPDD5               (0x20)
 121 #define EPORT_EPDDR_EPDD6               (0x40)
 122 #define EPORT_EPDDR_EPDD7               (0x80)
 123
 124 /* Bit definitions and macros for EPIER */
 125 #define EPORT_EPIER_EPIE1               (0x02)
 126 #define EPORT_EPIER_EPIE2               (0x04)
 127 #define EPORT_EPIER_EPIE3               (0x08)
 128 #define EPORT_EPIER_EPIE4               (0x10)
 129 #define EPORT_EPIER_EPIE5               (0x20)
 130 #define EPORT_EPIER_EPIE6               (0x40)
 131 #define EPORT_EPIER_EPIE7               (0x80)
 132
 133 /* Bit definitions and macros for EPDR */
 134 #define EPORT_EPDR_EPD1                 (0x02)
 135 #define EPORT_EPDR_EPD2                 (0x04)
 136 #define EPORT_EPDR_EPD3                 (0x08)
 137 #define EPORT_EPDR_EPD4                 (0x10)
 138 #define EPORT_EPDR_EPD5                 (0x20)
 139 #define EPORT_EPDR_EPD6                 (0x40)
 140 #define EPORT_EPDR_EPD7                 (0x80)
 141
 142 /* Bit definitions and macros for EPPDR */
 143 #define EPORT_EPPDR_EPPD1               (0x02)
 144 #define EPORT_EPPDR_EPPD2               (0x04)
 145 #define EPORT_EPPDR_EPPD3               (0x08)
 146 #define EPORT_EPPDR_EPPD4               (0x10)
 147 #define EPORT_EPPDR_EPPD5               (0x20)
 148 #define EPORT_EPPDR_EPPD6               (0x40)
 149 #define EPORT_EPPDR_EPPD7               (0x80)
 150
 151 /* Bit definitions and macros for EPFR */
 152 #define EPORT_EPFR_EPF1                 (0x02)
 153 #define EPORT_EPFR_EPF2                 (0x04)
 154 #define EPORT_EPFR_EPF3                 (0x08)
 155 #define EPORT_EPFR_EPF4                 (0x10)
 156 #define EPORT_EPFR_EPF5                 (0x20)
 157 #define EPORT_EPFR_EPF6                 (0x40)
 158 #define EPORT_EPFR_EPF7                 (0x80)
 159
 160 #endif                                  /* __EDMA_H__ */