arch/m68k/lib/time.c

   1 /*
   2  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27
  28 #include <asm/timer.h>
  29 #include <asm/immap.h>
  30 #include <watchdog.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 static volatile ulong timestamp = 0;
  35
  36 #ifndef CONFIG_SYS_WATCHDOG_FREQ
  37 #define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
  38 #endif
  39
  40 #if defined(CONFIG_MCFTMR)
  41 #ifndef CONFIG_SYS_UDELAY_BASE
  42 #       error   "uDelay base not defined!"
  43 #endif
  44
  45 #if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
  46 #       error   "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
  47 #endif
  48 extern void dtimer_intr_setup(void);
  49
  50 void __udelay(unsigned long usec)
  51 {
  52         volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_UDELAY_BASE);
  53         uint start, now, tmp;
  54
  55         while (usec > 0) {
  56                 if (usec > 65000)
  57                         tmp = 65000;
  58                 else
  59                         tmp = usec;
  60                 usec = usec - tmp;
  61
  62                 /* Set up TIMER 3 as timebase clock */
  63                 timerp->tmr = DTIM_DTMR_RST_RST;
  64                 timerp->tcn = 0;
  65                 /* set period to 1 us */
  66                 timerp->tmr =
  67                     CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
  68                     DTIM_DTMR_RST_EN;
  69
  70                 start = now = timerp->tcn;
  71                 while (now < start + tmp)
  72                         now = timerp->tcn;
  73         }
  74 }
  75
  76 void dtimer_interrupt(void *not_used)
  77 {
  78         volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
  79
  80         /* check for timer interrupt asserted */
  81         if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
  82                 timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
  83                 timestamp++;
  84
  85                 #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
  86                 if ((timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) {
  87                         WATCHDOG_RESET ();
  88                 }
  89                 #endif    /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
  90                 return;
  91         }
  92 }
  93
  94 void timer_init(void)
  95 {
  96         volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
  97
  98         timestamp = 0;
  99
 100         timerp->tcn = 0;
 101         timerp->trr = 0;
 102
 103         /* Set up TIMER 4 as clock */
 104         timerp->tmr = DTIM_DTMR_RST_RST;
 105
 106         /* initialize and enable timer interrupt */
 107         irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
 108
 109         timerp->tcn = 0;
 110         timerp->trr = 1000;     /* Interrupt every ms */
 111
 112         dtimer_intr_setup();
 113
 114         /* set a period of 1us, set timer mode to restart and enable timer and interrupt */
 115         timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
 116             DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
 117 }
 118
 119 void reset_timer(void)
 120 {
 121         timestamp = 0;
 122 }
 123
 124 ulong get_timer(ulong base)
 125 {
 126         return (timestamp - base);
 127 }
 128
 129 #endif                          /* CONFIG_MCFTMR */
 130
 131 #if defined(CONFIG_MCFPIT)
 132 #if !defined(CONFIG_SYS_PIT_BASE)
 133 #       error   "CONFIG_SYS_PIT_BASE not defined!"
 134 #endif
 135
 136 static unsigned short lastinc;
 137
 138 void __udelay(unsigned long usec)
 139 {
 140         volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_UDELAY_BASE);
 141         uint tmp;
 142
 143         while (usec > 0) {
 144                 if (usec > 65000)
 145                         tmp = 65000;
 146                 else
 147                         tmp = usec;
 148                 usec = usec - tmp;
 149
 150                 /* Set up TIMER 3 as timebase clock */
 151                 timerp->pcsr = PIT_PCSR_OVW;
 152                 timerp->pmr = 0;
 153                 /* set period to 1 us */
 154                 timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
 155
 156                 timerp->pmr = tmp;
 157                 while (timerp->pcntr > 0) ;
 158         }
 159 }
 160
 161 void timer_init(void)
 162 {
 163         volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
 164         timestamp = 0;
 165
 166         /* Set up TIMER 4 as poll clock */
 167         timerp->pcsr = PIT_PCSR_OVW;
 168         timerp->pmr = lastinc = 0;
 169         timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
 170 }
 171
 172 ulong get_timer(ulong base)
 173 {
 174         unsigned short now, diff;
 175         volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
 176
 177         now = timerp->pcntr;
 178         diff = -(now - lastinc);
 179
 180         timestamp += diff;
 181         lastinc = now;
 182         return timestamp - base;
 183 }
 184
 185 void wait_ticks(unsigned long ticks)
 186 {
 187         u32 start = get_timer(0);
 188         while (get_timer(start) < ticks) ;
 189 }
 190 #endif                          /* CONFIG_MCFPIT */
 191
 192 /*
 193  * This function is derived from PowerPC code (read timebase as long long).
 194  * On M68K it just returns the timer value.
 195  */
 196 unsigned long long get_ticks(void)
 197 {
 198         return get_timer(0);
 199 }
 200
 201 unsigned long usec2ticks(unsigned long usec)
 202 {
 203         return get_timer(usec);
 204 }
 205
 206 /*
 207  * This function is derived from PowerPC code (timebase clock frequency).
 208  * On M68K it returns the number of timer ticks per second.
 209  */
 210 ulong get_tbclk(void)
 211 {
 212         ulong tbclk;
 213         tbclk = CONFIG_SYS_HZ;
 214         return tbclk;
 215 }