arch/metag/include/asm/cache.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ASM_METAG_CACHE_H
   3 #define __ASM_METAG_CACHE_H
   4
   5 /* L1 cache line size (64 bytes) */
   6 #define L1_CACHE_SHIFT          6
   7 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
   8
   9 /* Meta requires large data items to be 8 byte aligned. */
  10 #define ARCH_SLAB_MINALIGN      8
  11
  12 /*
  13  * With an L2 cache, we may invalidate dirty lines, so we need to ensure DMA
  14  * buffers have cache line alignment.
  15  */
  16 #ifdef CONFIG_METAG_L2C
  17 #define ARCH_DMA_MINALIGN       L1_CACHE_BYTES
  18 #else
  19 #define ARCH_DMA_MINALIGN       8
  20 #endif
  21
  22 #define __read_mostly __attribute__((__section__(".data..read_mostly")))
  23
  24 #endif