arch/mips/Kconfig

   1 menu "MIPS architecture"
   2         depends on MIPS
   3
   4 config SYS_ARCH
   5         default "mips"
   6
   7 config SYS_CPU
   8         default "mips32" if CPU_MIPS32
   9         default "mips64" if CPU_MIPS64
  10
  11 choice
  12         prompt "Target select"
  13         optional
  14
  15 config TARGET_QEMU_MIPS
  16         bool "Support qemu-mips"
  17         select SUPPORTS_BIG_ENDIAN
  18         select SUPPORTS_LITTLE_ENDIAN
  19         select SUPPORTS_CPU_MIPS32_R1
  20         select SUPPORTS_CPU_MIPS32_R2
  21         select SUPPORTS_CPU_MIPS64_R1
  22         select SUPPORTS_CPU_MIPS64_R2
  23
  24 config TARGET_MALTA
  25         bool "Support malta"
  26         select DM
  27         select DM_SERIAL
  28         select DYNAMIC_IO_PORT_BASE
  29         select OF_CONTROL
  30         select OF_ISA_BUS
  31         select SUPPORTS_BIG_ENDIAN
  32         select SUPPORTS_LITTLE_ENDIAN
  33         select SUPPORTS_CPU_MIPS32_R1
  34         select SUPPORTS_CPU_MIPS32_R2
  35         select SUPPORTS_CPU_MIPS32_R6
  36         select SUPPORTS_CPU_MIPS64_R1
  37         select SUPPORTS_CPU_MIPS64_R2
  38         select SUPPORTS_CPU_MIPS64_R6
  39         select SWAP_IO_SPACE
  40         select MIPS_L1_CACHE_SHIFT_6
  41
  42 config TARGET_VCT
  43         bool "Support vct"
  44         select SUPPORTS_BIG_ENDIAN
  45         select SUPPORTS_CPU_MIPS32_R1
  46         select SUPPORTS_CPU_MIPS32_R2
  47         select SYS_MIPS_CACHE_INIT_RAM_LOAD
  48
  49 config TARGET_DBAU1X00
  50         bool "Support dbau1x00"
  51         select SUPPORTS_BIG_ENDIAN
  52         select SUPPORTS_LITTLE_ENDIAN
  53         select SUPPORTS_CPU_MIPS32_R1
  54         select SUPPORTS_CPU_MIPS32_R2
  55         select SYS_MIPS_CACHE_INIT_RAM_LOAD
  56         select MIPS_TUNE_4KC
  57
  58 config TARGET_PB1X00
  59         bool "Support pb1x00"
  60         select SUPPORTS_LITTLE_ENDIAN
  61         select SUPPORTS_CPU_MIPS32_R1
  62         select SUPPORTS_CPU_MIPS32_R2
  63         select SYS_MIPS_CACHE_INIT_RAM_LOAD
  64         select MIPS_TUNE_4KC
  65
  66 config ARCH_ATH79
  67         bool "Support QCA/Atheros ath79"
  68         select OF_CONTROL
  69         select DM
  70
  71 config MACH_PIC32
  72         bool "Support Microchip PIC32"
  73         select OF_CONTROL
  74         select DM
  75
  76 endchoice
  77
  78 source "board/dbau1x00/Kconfig"
  79 source "board/imgtec/malta/Kconfig"
  80 source "board/micronas/vct/Kconfig"
  81 source "board/pb1x00/Kconfig"
  82 source "board/qemu-mips/Kconfig"
  83 source "arch/mips/mach-ath79/Kconfig"
  84 source "arch/mips/mach-pic32/Kconfig"
  85
  86 if MIPS
  87
  88 choice
  89         prompt "Endianness selection"
  90         help
  91           Some MIPS boards can be configured for either little or big endian
  92           byte order. These modes require different U-Boot images. In general there
  93           is one preferred byteorder for a particular system but some systems are
  94           just as commonly used in the one or the other endianness.
  95
  96 config SYS_BIG_ENDIAN
  97         bool "Big endian"
  98         depends on SUPPORTS_BIG_ENDIAN
  99
 100 config SYS_LITTLE_ENDIAN
 101         bool "Little endian"
 102         depends on SUPPORTS_LITTLE_ENDIAN
 103
 104 endchoice
 105
 106 choice
 107         prompt "CPU selection"
 108         default CPU_MIPS32_R2
 109
 110 config CPU_MIPS32_R1
 111         bool "MIPS32 Release 1"
 112         depends on SUPPORTS_CPU_MIPS32_R1
 113         select 32BIT
 114         help
 115           Choose this option to build an U-Boot for release 1 through 5 of the
 116           MIPS32 architecture.
 117
 118 config CPU_MIPS32_R2
 119         bool "MIPS32 Release 2"
 120         depends on SUPPORTS_CPU_MIPS32_R2
 121         select 32BIT
 122         help
 123           Choose this option to build an U-Boot for release 2 through 5 of the
 124           MIPS32 architecture.
 125
 126 config CPU_MIPS32_R6
 127         bool "MIPS32 Release 6"
 128         depends on SUPPORTS_CPU_MIPS32_R6
 129         select 32BIT
 130         help
 131           Choose this option to build an U-Boot for release 6 or later of the
 132           MIPS32 architecture.
 133
 134 config CPU_MIPS64_R1
 135         bool "MIPS64 Release 1"
 136         depends on SUPPORTS_CPU_MIPS64_R1
 137         select 64BIT
 138         help
 139           Choose this option to build a kernel for release 1 through 5 of the
 140           MIPS64 architecture.
 141
 142 config CPU_MIPS64_R2
 143         bool "MIPS64 Release 2"
 144         depends on SUPPORTS_CPU_MIPS64_R2
 145         select 64BIT
 146         help
 147           Choose this option to build a kernel for release 2 through 5 of the
 148           MIPS64 architecture.
 149
 150 config CPU_MIPS64_R6
 151         bool "MIPS64 Release 6"
 152         depends on SUPPORTS_CPU_MIPS64_R6
 153         select 64BIT
 154         help
 155           Choose this option to build a kernel for release 6 or later of the
 156           MIPS64 architecture.
 157
 158 endchoice
 159
 160 menu "OS boot interface"
 161
 162 config MIPS_BOOT_CMDLINE_LEGACY
 163         bool "Hand over legacy command line to Linux kernel"
 164         default y
 165         help
 166           Enable this option if you want U-Boot to hand over the Yamon-style
 167           command line to the kernel. All bootargs will be prepared as argc/argv
 168           compatible list. The argument count (argc) is stored in register $a0.
 169           The address of the argument list (argv) is stored in register $a1.
 170
 171 config MIPS_BOOT_ENV_LEGACY
 172         bool "Hand over legacy environment to Linux kernel"
 173         default y
 174         help
 175           Enable this option if you want U-Boot to hand over the Yamon-style
 176           environment to the kernel. Information like memory size, initrd
 177           address and size will be prepared as zero-terminated key/value list.
 178           The address of the environment is stored in register $a2.
 179
 180 config MIPS_BOOT_FDT
 181         bool "Hand over a flattened device tree to Linux kernel"
 182         default n
 183         help
 184           Enable this option if you want U-Boot to hand over a flattened
 185           device tree to the kernel. According to UHI register $a0 will be set
 186           to -2 and the FDT address is stored in $a1.
 187
 188 endmenu
 189
 190 config SUPPORTS_BIG_ENDIAN
 191         bool
 192
 193 config SUPPORTS_LITTLE_ENDIAN
 194         bool
 195
 196 config SUPPORTS_CPU_MIPS32_R1
 197         bool
 198
 199 config SUPPORTS_CPU_MIPS32_R2
 200         bool
 201
 202 config SUPPORTS_CPU_MIPS32_R6
 203         bool
 204
 205 config SUPPORTS_CPU_MIPS64_R1
 206         bool
 207
 208 config SUPPORTS_CPU_MIPS64_R2
 209         bool
 210
 211 config SUPPORTS_CPU_MIPS64_R6
 212         bool
 213
 214 config CPU_MIPS32
 215         bool
 216         default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
 217
 218 config CPU_MIPS64
 219         bool
 220         default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
 221
 222 config MIPS_TUNE_4KC
 223         bool
 224
 225 config MIPS_TUNE_14KC
 226         bool
 227
 228 config MIPS_TUNE_24KC
 229         bool
 230
 231 config MIPS_TUNE_34KC
 232         bool
 233
 234 config MIPS_TUNE_74KC
 235         bool
 236
 237 config 32BIT
 238         bool
 239
 240 config 64BIT
 241         bool
 242
 243 config SWAP_IO_SPACE
 244         bool
 245
 246 config SYS_MIPS_CACHE_INIT_RAM_LOAD
 247         bool
 248
 249 config SYS_DCACHE_SIZE
 250         int
 251         default 0
 252         help
 253           The total size of the L1 Dcache, if known at compile time.
 254
 255 config SYS_DCACHE_LINE_SIZE
 256         int
 257         default 0
 258         help
 259           The size of L1 Dcache lines, if known at compile time.
 260
 261 config SYS_ICACHE_SIZE
 262         int
 263         default 0
 264         help
 265           The total size of the L1 ICache, if known at compile time.
 266
 267 config SYS_ICACHE_LINE_SIZE
 268         int
 269         default 0
 270         help
 271           The size of L1 Icache lines, if known at compile time.
 272
 273 config SYS_CACHE_SIZE_AUTO
 274         def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
 275                 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
 276         help
 277           Select this (or let it be auto-selected by not defining any cache
 278           sizes) in order to allow U-Boot to automatically detect the sizes
 279           of caches at runtime. This has a small cost in code size & runtime
 280           so if you know the cache configuration for your system at compile
 281           time it would be beneficial to configure it.
 282
 283 config MIPS_L1_CACHE_SHIFT_4
 284         bool
 285
 286 config MIPS_L1_CACHE_SHIFT_5
 287         bool
 288
 289 config MIPS_L1_CACHE_SHIFT_6
 290         bool
 291
 292 config MIPS_L1_CACHE_SHIFT_7
 293         bool
 294
 295 config MIPS_L1_CACHE_SHIFT
 296         int
 297         default "7" if MIPS_L1_CACHE_SHIFT_7
 298         default "6" if MIPS_L1_CACHE_SHIFT_6
 299         default "5" if MIPS_L1_CACHE_SHIFT_5
 300         default "4" if MIPS_L1_CACHE_SHIFT_4
 301         default "5"
 302
 303 config DYNAMIC_IO_PORT_BASE
 304         bool
 305
 306 endif
 307
 308 endmenu