arch/mips/Kconfig

   1 menu "MIPS architecture"
   2         depends on MIPS
   3
   4 config SYS_ARCH
   5         default "mips"
   6
   7 config SYS_CPU
   8         default "mips32" if CPU_MIPS32
   9         default "mips64" if CPU_MIPS64
  10
  11 choice
  12         prompt "Target select"
  13         optional
  14
  15 config TARGET_QEMU_MIPS
  16         bool "Support qemu-mips"
  17         select SUPPORTS_BIG_ENDIAN
  18         select SUPPORTS_LITTLE_ENDIAN
  19         select SUPPORTS_CPU_MIPS32_R1
  20         select SUPPORTS_CPU_MIPS32_R2
  21         select SUPPORTS_CPU_MIPS64_R1
  22         select SUPPORTS_CPU_MIPS64_R2
  23         select ROM_EXCEPTION_VECTORS
  24
  25 config TARGET_MALTA
  26         bool "Support malta"
  27         select DM
  28         select DM_SERIAL
  29         select DYNAMIC_IO_PORT_BASE
  30         select MIPS_CM
  31         select MIPS_L2_CACHE
  32         select OF_CONTROL
  33         select OF_ISA_BUS
  34         select SUPPORTS_BIG_ENDIAN
  35         select SUPPORTS_LITTLE_ENDIAN
  36         select SUPPORTS_CPU_MIPS32_R1
  37         select SUPPORTS_CPU_MIPS32_R2
  38         select SUPPORTS_CPU_MIPS32_R6
  39         select SUPPORTS_CPU_MIPS64_R1
  40         select SUPPORTS_CPU_MIPS64_R2
  41         select SUPPORTS_CPU_MIPS64_R6
  42         select SWAP_IO_SPACE
  43         select MIPS_L1_CACHE_SHIFT_6
  44         select ROM_EXCEPTION_VECTORS
  45
  46 config TARGET_VCT
  47         bool "Support vct"
  48         select SUPPORTS_BIG_ENDIAN
  49         select SUPPORTS_CPU_MIPS32_R1
  50         select SUPPORTS_CPU_MIPS32_R2
  51         select SYS_MIPS_CACHE_INIT_RAM_LOAD
  52         select ROM_EXCEPTION_VECTORS
  53
  54 config TARGET_DBAU1X00
  55         bool "Support dbau1x00"
  56         select SUPPORTS_BIG_ENDIAN
  57         select SUPPORTS_LITTLE_ENDIAN
  58         select SUPPORTS_CPU_MIPS32_R1
  59         select SUPPORTS_CPU_MIPS32_R2
  60         select SYS_MIPS_CACHE_INIT_RAM_LOAD
  61         select ROM_EXCEPTION_VECTORS
  62         select MIPS_TUNE_4KC
  63
  64 config TARGET_PB1X00
  65         bool "Support pb1x00"
  66         select SUPPORTS_LITTLE_ENDIAN
  67         select SUPPORTS_CPU_MIPS32_R1
  68         select SUPPORTS_CPU_MIPS32_R2
  69         select SYS_MIPS_CACHE_INIT_RAM_LOAD
  70         select ROM_EXCEPTION_VECTORS
  71         select MIPS_TUNE_4KC
  72
  73 config ARCH_ATH79
  74         bool "Support QCA/Atheros ath79"
  75         select OF_CONTROL
  76         select DM
  77
  78 config MACH_PIC32
  79         bool "Support Microchip PIC32"
  80         select OF_CONTROL
  81         select DM
  82
  83 config TARGET_BOSTON
  84         bool "Support Boston"
  85         select DM
  86         select DM_SERIAL
  87         select OF_CONTROL
  88         select MIPS_CM
  89         select MIPS_L1_CACHE_SHIFT_6
  90         select MIPS_L2_CACHE
  91         select SUPPORTS_BIG_ENDIAN
  92         select SUPPORTS_LITTLE_ENDIAN
  93         select SUPPORTS_CPU_MIPS32_R1
  94         select SUPPORTS_CPU_MIPS32_R2
  95         select SUPPORTS_CPU_MIPS32_R6
  96         select SUPPORTS_CPU_MIPS64_R1
  97         select SUPPORTS_CPU_MIPS64_R2
  98         select SUPPORTS_CPU_MIPS64_R6
  99         select ROM_EXCEPTION_VECTORS
 100
 101 config TARGET_XILFPGA
 102         bool "Support Imagination Xilfpga"
 103         select OF_CONTROL
 104         select DM
 105         select DM_SERIAL
 106         select DM_GPIO
 107         select DM_ETH
 108         select SUPPORTS_LITTLE_ENDIAN
 109         select SUPPORTS_CPU_MIPS32_R1
 110         select SUPPORTS_CPU_MIPS32_R2
 111         select MIPS_L1_CACHE_SHIFT_4
 112         select ROM_EXCEPTION_VECTORS
 113         help
 114           This supports IMGTEC MIPSfpga platform
 115
 116 endchoice
 117
 118 source "board/dbau1x00/Kconfig"
 119 source "board/imgtec/boston/Kconfig"
 120 source "board/imgtec/malta/Kconfig"
 121 source "board/imgtec/xilfpga/Kconfig"
 122 source "board/micronas/vct/Kconfig"
 123 source "board/pb1x00/Kconfig"
 124 source "board/qemu-mips/Kconfig"
 125 source "arch/mips/mach-ath79/Kconfig"
 126 source "arch/mips/mach-pic32/Kconfig"
 127
 128 if MIPS
 129
 130 choice
 131         prompt "Endianness selection"
 132         help
 133           Some MIPS boards can be configured for either little or big endian
 134           byte order. These modes require different U-Boot images. In general there
 135           is one preferred byteorder for a particular system but some systems are
 136           just as commonly used in the one or the other endianness.
 137
 138 config SYS_BIG_ENDIAN
 139         bool "Big endian"
 140         depends on SUPPORTS_BIG_ENDIAN
 141
 142 config SYS_LITTLE_ENDIAN
 143         bool "Little endian"
 144         depends on SUPPORTS_LITTLE_ENDIAN
 145
 146 endchoice
 147
 148 choice
 149         prompt "CPU selection"
 150         default CPU_MIPS32_R2
 151
 152 config CPU_MIPS32_R1
 153         bool "MIPS32 Release 1"
 154         depends on SUPPORTS_CPU_MIPS32_R1
 155         select 32BIT
 156         help
 157           Choose this option to build an U-Boot for release 1 through 5 of the
 158           MIPS32 architecture.
 159
 160 config CPU_MIPS32_R2
 161         bool "MIPS32 Release 2"
 162         depends on SUPPORTS_CPU_MIPS32_R2
 163         select 32BIT
 164         help
 165           Choose this option to build an U-Boot for release 2 through 5 of the
 166           MIPS32 architecture.
 167
 168 config CPU_MIPS32_R6
 169         bool "MIPS32 Release 6"
 170         depends on SUPPORTS_CPU_MIPS32_R6
 171         select 32BIT
 172         help
 173           Choose this option to build an U-Boot for release 6 or later of the
 174           MIPS32 architecture.
 175
 176 config CPU_MIPS64_R1
 177         bool "MIPS64 Release 1"
 178         depends on SUPPORTS_CPU_MIPS64_R1
 179         select 64BIT
 180         help
 181           Choose this option to build a kernel for release 1 through 5 of the
 182           MIPS64 architecture.
 183
 184 config CPU_MIPS64_R2
 185         bool "MIPS64 Release 2"
 186         depends on SUPPORTS_CPU_MIPS64_R2
 187         select 64BIT
 188         help
 189           Choose this option to build a kernel for release 2 through 5 of the
 190           MIPS64 architecture.
 191
 192 config CPU_MIPS64_R6
 193         bool "MIPS64 Release 6"
 194         depends on SUPPORTS_CPU_MIPS64_R6
 195         select 64BIT
 196         help
 197           Choose this option to build a kernel for release 6 or later of the
 198           MIPS64 architecture.
 199
 200 endchoice
 201
 202 menu "General setup"
 203
 204 config ROM_EXCEPTION_VECTORS
 205         bool "Build U-Boot image with exception vectors"
 206         help
 207           Enable this to include exception vectors in the U-Boot image. This is
 208           required if the U-Boot entry point is equal to the address of the
 209           CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
 210           U-Boot booted from parallel NOR flash).
 211           Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
 212           In that case the image size will be reduced by 0x500 bytes.
 213
 214 endmenu
 215
 216 menu "OS boot interface"
 217
 218 config MIPS_BOOT_CMDLINE_LEGACY
 219         bool "Hand over legacy command line to Linux kernel"
 220         default y
 221         help
 222           Enable this option if you want U-Boot to hand over the Yamon-style
 223           command line to the kernel. All bootargs will be prepared as argc/argv
 224           compatible list. The argument count (argc) is stored in register $a0.
 225           The address of the argument list (argv) is stored in register $a1.
 226
 227 config MIPS_BOOT_ENV_LEGACY
 228         bool "Hand over legacy environment to Linux kernel"
 229         default y
 230         help
 231           Enable this option if you want U-Boot to hand over the Yamon-style
 232           environment to the kernel. Information like memory size, initrd
 233           address and size will be prepared as zero-terminated key/value list.
 234           The address of the environment is stored in register $a2.
 235
 236 config MIPS_BOOT_FDT
 237         bool "Hand over a flattened device tree to Linux kernel"
 238         default n
 239         help
 240           Enable this option if you want U-Boot to hand over a flattened
 241           device tree to the kernel. According to UHI register $a0 will be set
 242           to -2 and the FDT address is stored in $a1.
 243
 244 endmenu
 245
 246 config SUPPORTS_BIG_ENDIAN
 247         bool
 248
 249 config SUPPORTS_LITTLE_ENDIAN
 250         bool
 251
 252 config SUPPORTS_CPU_MIPS32_R1
 253         bool
 254
 255 config SUPPORTS_CPU_MIPS32_R2
 256         bool
 257
 258 config SUPPORTS_CPU_MIPS32_R6
 259         bool
 260
 261 config SUPPORTS_CPU_MIPS64_R1
 262         bool
 263
 264 config SUPPORTS_CPU_MIPS64_R2
 265         bool
 266
 267 config SUPPORTS_CPU_MIPS64_R6
 268         bool
 269
 270 config CPU_MIPS32
 271         bool
 272         default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
 273
 274 config CPU_MIPS64
 275         bool
 276         default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
 277
 278 config MIPS_TUNE_4KC
 279         bool
 280
 281 config MIPS_TUNE_14KC
 282         bool
 283
 284 config MIPS_TUNE_24KC
 285         bool
 286
 287 config MIPS_TUNE_34KC
 288         bool
 289
 290 config MIPS_TUNE_74KC
 291         bool
 292
 293 config 32BIT
 294         bool
 295
 296 config 64BIT
 297         bool
 298
 299 config SWAP_IO_SPACE
 300         bool
 301
 302 config SYS_MIPS_CACHE_INIT_RAM_LOAD
 303         bool
 304
 305 config SYS_DCACHE_SIZE
 306         int
 307         default 0
 308         help
 309           The total size of the L1 Dcache, if known at compile time.
 310
 311 config SYS_DCACHE_LINE_SIZE
 312         int
 313         default 0
 314         help
 315           The size of L1 Dcache lines, if known at compile time.
 316
 317 config SYS_ICACHE_SIZE
 318         int
 319         default 0
 320         help
 321           The total size of the L1 ICache, if known at compile time.
 322
 323 config SYS_ICACHE_LINE_SIZE
 324         int
 325         default 0
 326         help
 327           The size of L1 Icache lines, if known at compile time.
 328
 329 config SYS_CACHE_SIZE_AUTO
 330         def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
 331                 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
 332         help
 333           Select this (or let it be auto-selected by not defining any cache
 334           sizes) in order to allow U-Boot to automatically detect the sizes
 335           of caches at runtime. This has a small cost in code size & runtime
 336           so if you know the cache configuration for your system at compile
 337           time it would be beneficial to configure it.
 338
 339 config MIPS_L1_CACHE_SHIFT_4
 340         bool
 341
 342 config MIPS_L1_CACHE_SHIFT_5
 343         bool
 344
 345 config MIPS_L1_CACHE_SHIFT_6
 346         bool
 347
 348 config MIPS_L1_CACHE_SHIFT_7
 349         bool
 350
 351 config MIPS_L1_CACHE_SHIFT
 352         int
 353         default "7" if MIPS_L1_CACHE_SHIFT_7
 354         default "6" if MIPS_L1_CACHE_SHIFT_6
 355         default "5" if MIPS_L1_CACHE_SHIFT_5
 356         default "4" if MIPS_L1_CACHE_SHIFT_4
 357         default "5"
 358
 359 config MIPS_L2_CACHE
 360         bool
 361         help
 362           Select this if your system includes an L2 cache and you want U-Boot
 363           to initialise & maintain it.
 364
 365 config DYNAMIC_IO_PORT_BASE
 366         bool
 367
 368 config MIPS_CM
 369         bool
 370         help
 371           Select this if your system contains a MIPS Coherence Manager and you
 372           wish U-Boot to configure it or make use of it to retrieve system
 373           information such as cache configuration.
 374
 375 config MIPS_CM_BASE
 376         hex
 377         default 0x1fbf8000
 378         help
 379           The physical base address at which to map the MIPS Coherence Manager
 380           Global Configuration Registers (GCRs). This should be set such that
 381           the GCRs occupy a region of the physical address space which is
 382           otherwise unused, or at minimum that software doesn't need to access.
 383
 384 endif
 385
 386 endmenu