arch/mips/Kconfig

   1 menu "MIPS architecture"
   2         depends on MIPS
   3
   4 config SYS_ARCH
   5         default "mips"
   6
   7 config SYS_CPU
   8         default "mips32" if CPU_MIPS32
   9         default "mips64" if CPU_MIPS64
  10
  11 choice
  12         prompt "Target select"
  13         optional
  14
  15 config TARGET_MALTA
  16         bool "Support malta"
  17         select HAS_FIXED_TIMER_FREQUENCY
  18         select BOARD_EARLY_INIT_R
  19         select DM
  20         select DM_SERIAL
  21         select PCI
  22         select DYNAMIC_IO_PORT_BASE
  23         select MIPS_CM
  24         select MIPS_INSERT_BOOT_CONFIG
  25         select SYS_CACHE_SHIFT_6
  26         select MIPS_L2_CACHE
  27         select OF_CONTROL
  28         select OF_ISA_BUS
  29         select PCI_MAP_SYSTEM_MEMORY
  30         select ROM_EXCEPTION_VECTORS
  31         select SUPPORTS_BIG_ENDIAN
  32         select SUPPORTS_CPU_MIPS32_R1
  33         select SUPPORTS_CPU_MIPS32_R2
  34         select SUPPORTS_CPU_MIPS32_R6
  35         select SUPPORTS_CPU_MIPS64_R1
  36         select SUPPORTS_CPU_MIPS64_R2
  37         select SUPPORTS_CPU_MIPS64_R6
  38         select SUPPORTS_LITTLE_ENDIAN
  39         select SWAP_IO_SPACE
  40         imply CMD_DM
  41
  42 config ARCH_ATH79
  43         bool "Support QCA/Atheros ath79"
  44         select HAS_FIXED_TIMER_FREQUENCY
  45         select DM
  46         select OF_CONTROL
  47         imply CMD_DM
  48
  49 config ARCH_MSCC
  50         bool "Support MSCC VCore-III"
  51         select HAS_FIXED_TIMER_FREQUENCY
  52         select OF_CONTROL
  53         select DM
  54
  55 config ARCH_BMIPS
  56         bool "Support BMIPS SoCs"
  57         select HAS_FIXED_TIMER_FREQUENCY
  58         select CLK
  59         select CPU
  60         select DM
  61         select OF_CONTROL
  62         select RAM
  63         select SYSRESET
  64         imply CMD_DM
  65
  66 config ARCH_MTMIPS
  67         bool "Support MediaTek MIPS platforms"
  68         select HAS_FIXED_TIMER_FREQUENCY
  69         select CLK
  70         imply CMD_DM
  71         select DISPLAY_CPUINFO
  72         select DM
  73         imply DM_GPIO
  74         select DM_RESET
  75         select DM_SERIAL
  76         select PINCTRL
  77         select PINMUX
  78         select PINCONF
  79         select RESET_MTMIPS
  80         imply MTD
  81         imply DM_SPI
  82         imply DM_SPI_FLASH
  83         select LAST_STAGE_INIT
  84         select MIPS_TUNE_24KC
  85         select OF_CONTROL
  86         select ROM_EXCEPTION_VECTORS
  87         select SUPPORTS_CPU_MIPS32_R1
  88         select SUPPORTS_CPU_MIPS32_R2
  89         select SUPPORTS_LITTLE_ENDIAN
  90         select SUPPORT_SPL
  91
  92 config ARCH_JZ47XX
  93         bool "Support Ingenic JZ47xx"
  94         select SUPPORT_SPL
  95         select HAS_FIXED_TIMER_FREQUENCY
  96         select OF_CONTROL
  97         select DM
  98
  99 config ARCH_OCTEON
 100         bool "Support Marvell Octeon CN7xxx platforms"
 101         select ARCH_EARLY_INIT_R
 102         select CPU_CAVIUM_OCTEON
 103         select DISPLAY_CPUINFO
 104         select DMA_ADDR_T_64BIT
 105         select DM
 106         select DM_GPIO
 107         select DM_I2C
 108         select DM_SERIAL
 109         select DM_SPI
 110         select MIPS_L2_CACHE
 111         select MIPS_MACH_EARLY_INIT
 112         select MIPS_TUNE_OCTEON3
 113         select MTD
 114         select ROM_EXCEPTION_VECTORS
 115         select SUPPORTS_BIG_ENDIAN
 116         select SUPPORTS_CPU_MIPS64_OCTEON
 117         select PHYS_64BIT
 118         select OF_CONTROL
 119         select OF_LIVE
 120         imply CMD_DM
 121
 122 config MACH_PIC32
 123         bool "Support Microchip PIC32"
 124         select HAS_FIXED_TIMER_FREQUENCY
 125         select DM
 126         select DM_EVENT
 127         select OF_CONTROL
 128         imply CMD_DM
 129
 130 config TARGET_BOSTON
 131         bool "Support Boston"
 132         select HAS_FIXED_TIMER_FREQUENCY
 133         select DM
 134         select DM_SERIAL
 135         select MIPS_CM
 136         select SYS_CACHE_SHIFT_6
 137         select MIPS_L2_CACHE
 138         select OF_BOARD_SETUP
 139         select OF_CONTROL
 140         select ROM_EXCEPTION_VECTORS
 141         select SUPPORTS_BIG_ENDIAN
 142         select SUPPORTS_CPU_MIPS32_R1
 143         select SUPPORTS_CPU_MIPS32_R2
 144         select SUPPORTS_CPU_MIPS32_R6
 145         select SUPPORTS_CPU_MIPS64_R1
 146         select SUPPORTS_CPU_MIPS64_R2
 147         select SUPPORTS_CPU_MIPS64_R6
 148         select SUPPORTS_LITTLE_ENDIAN
 149         imply CMD_DM
 150
 151 config TARGET_XILFPGA
 152         bool "Support Imagination Xilfpga"
 153         select HAS_FIXED_TIMER_FREQUENCY
 154         select DM
 155         select DM_GPIO
 156         select DM_SERIAL
 157         select SYS_CACHE_SHIFT_4
 158         select OF_CONTROL
 159         select ROM_EXCEPTION_VECTORS
 160         select SUPPORTS_CPU_MIPS32_R1
 161         select SUPPORTS_CPU_MIPS32_R2
 162         select SUPPORTS_LITTLE_ENDIAN
 163         imply CMD_DM
 164         help
 165           This supports IMGTEC MIPSfpga platform
 166
 167 endchoice
 168
 169 source "board/imgtec/boston/Kconfig"
 170 source "board/imgtec/malta/Kconfig"
 171 source "board/imgtec/xilfpga/Kconfig"
 172 source "arch/mips/mach-ath79/Kconfig"
 173 source "arch/mips/mach-mscc/Kconfig"
 174 source "arch/mips/mach-bmips/Kconfig"
 175 source "arch/mips/mach-jz47xx/Kconfig"
 176 source "arch/mips/mach-pic32/Kconfig"
 177 source "arch/mips/mach-mtmips/Kconfig"
 178 source "arch/mips/mach-octeon/Kconfig"
 179
 180 if MIPS
 181
 182 choice
 183         prompt "CPU selection"
 184         default CPU_MIPS32_R2
 185
 186 config CPU_MIPS32_R1
 187         bool "MIPS32 Release 1"
 188         depends on SUPPORTS_CPU_MIPS32_R1
 189         select 32BIT
 190         help
 191           Choose this option to build an U-Boot for release 1 through 5 of the
 192           MIPS32 architecture.
 193
 194 config CPU_MIPS32_R2
 195         bool "MIPS32 Release 2"
 196         depends on SUPPORTS_CPU_MIPS32_R2
 197         select 32BIT
 198         help
 199           Choose this option to build an U-Boot for release 2 through 5 of the
 200           MIPS32 architecture.
 201
 202 config CPU_MIPS32_R6
 203         bool "MIPS32 Release 6"
 204         depends on SUPPORTS_CPU_MIPS32_R6
 205         select 32BIT
 206         help
 207           Choose this option to build an U-Boot for release 6 or later of the
 208           MIPS32 architecture.
 209
 210 config CPU_MIPS64_R1
 211         bool "MIPS64 Release 1"
 212         depends on SUPPORTS_CPU_MIPS64_R1
 213         select 64BIT
 214         help
 215           Choose this option to build a kernel for release 1 through 5 of the
 216           MIPS64 architecture.
 217
 218 config CPU_MIPS64_R2
 219         bool "MIPS64 Release 2"
 220         depends on SUPPORTS_CPU_MIPS64_R2
 221         select 64BIT
 222         help
 223           Choose this option to build a kernel for release 2 through 5 of the
 224           MIPS64 architecture.
 225
 226 config CPU_MIPS64_R6
 227         bool "MIPS64 Release 6"
 228         depends on SUPPORTS_CPU_MIPS64_R6
 229         select 64BIT
 230         help
 231           Choose this option to build a kernel for release 6 or later of the
 232           MIPS64 architecture.
 233
 234 config CPU_MIPS64_OCTEON
 235         bool "Marvell Octeon series of CPUs"
 236         depends on SUPPORTS_CPU_MIPS64_OCTEON
 237         select 64BIT
 238         help
 239          Choose this option for Marvell Octeon CPUs.  These CPUs are between
 240          MIPS64 R5 and R6 with other extensions.
 241
 242 endchoice
 243
 244 menu "General setup"
 245
 246 config ROM_EXCEPTION_VECTORS
 247         bool "Build U-Boot image with exception vectors"
 248         help
 249           Enable this to include exception vectors in the U-Boot image. This is
 250           required if the U-Boot entry point is equal to the address of the
 251           CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
 252           U-Boot booted from parallel NOR flash).
 253           Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
 254           In that case the image size will be reduced by 0x500 bytes.
 255
 256 config SYS_MIPS_TIMER_FREQ
 257         int "Fixed MIPS CPU timer frequency in Hz"
 258         depends on HAS_FIXED_TIMER_FREQUENCY
 259         help
 260           Configures a fixed CPU timer frequency.
 261
 262 config MIPS_CM_BASE
 263         hex "MIPS CM GCR Base Address"
 264         depends on MIPS_CM
 265         default 0x16100000 if TARGET_BOSTON
 266         default 0x1fbf8000
 267         help
 268           The physical base address at which to map the MIPS Coherence Manager
 269           Global Configuration Registers (GCRs). This should be set such that
 270           the GCRs occupy a region of the physical address space which is
 271           otherwise unused, or at minimum that software doesn't need to access.
 272
 273 config MIPS_CACHE_INDEX_BASE
 274         hex "Index base address for cache initialisation"
 275         default 0x80000000 if CPU_MIPS32
 276         default 0xffffffff80000000 if CPU_MIPS64
 277         help
 278           This is the base address for a memory block, which is used for
 279           initialising the cache lines. This is also the base address of a memory
 280           block which is used for loading and filling cache lines when
 281           SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
 282           Normally this is CKSEG0. If the MIPS system needs to move this block
 283           to some SRAM or ScratchPad RAM, adapt this option accordingly.
 284
 285 config MIPS_MACH_EARLY_INIT
 286         bool "Enable mach specific very early init code"
 287         help
 288           Use this to enable the call to mips_mach_early_init() very early
 289           from start.S. This function can be used e.g. to do some very early
 290           CPU / SoC intitialization or image copying. Its called very early
 291           and at this stage the PC might not match the linking address
 292           (CONFIG_TEXT_BASE) - no absolute jump done until this call.
 293
 294 config MIPS_CACHE_SETUP
 295         bool "Allow generic start code to initialize and setup caches"
 296         default n if SKIP_LOWLEVEL_INIT
 297         default y
 298         help
 299           This allows the generic start code to invoke the generic initialization
 300           of the CPU caches. Disabling this can be useful for RAM boot scenarios
 301           (EJTAG, SPL payload) or for machines which don't need cache initialization
 302           or which want to provide their own cache implementation.
 303
 304           If unsure, say yes.
 305
 306 config MIPS_CACHE_DISABLE
 307         bool "Allow generic start code to initially disable caches"
 308         default n if SKIP_LOWLEVEL_INIT
 309         default y
 310         help
 311           This allows the generic start code to initially disable the CPU caches
 312           and run uncached until the caches are initialized and enabled. Disabling
 313           this can be useful on machines which don't need cache initialization or
 314           which want to provide their own cache implementation.
 315
 316           If unsure, say yes.
 317
 318 config MIPS_RELOCATION_TABLE_SIZE
 319         hex "Relocation table size"
 320         range 0x100 0x10000
 321         default "0x8000"
 322         ---help---
 323           A table of relocation data will be appended to the U-Boot binary
 324           and parsed in relocate_code() to fix up all offsets in the relocated
 325           U-Boot.
 326
 327           This option allows the amount of space reserved for the table to be
 328           adjusted in a range from 256 up to 64k. The default is 32k and should
 329           be ok in most cases. Reduce this value to shrink the size of U-Boot
 330           binary.
 331
 332           The build will fail and a valid size suggested if this is too small.
 333
 334           If unsure, leave at the default value.
 335
 336 config RESTORE_EXCEPTION_VECTOR_BASE
 337         bool "Restore exception vector base before booting linux kernel"
 338         help
 339           In U-Boot the exception vector base will be moved to top of memory,
 340           to be used to display register dump when exception occurs.
 341           But some old linux kernel does not honor the base set in CP0_EBASE.
 342           A modified exception vector base will cause kernel crash.
 343
 344           This option will restore the exception vector base to its previous
 345           value.
 346
 347           If unsure, say N.
 348
 349 config OVERRIDE_EXCEPTION_VECTOR_BASE
 350         bool "Override the exception vector base to be restored"
 351         depends on RESTORE_EXCEPTION_VECTOR_BASE
 352         help
 353           Enable this option if you want to use a different exception vector
 354           base rather than the previously saved one.
 355
 356 config NEW_EXCEPTION_VECTOR_BASE
 357         hex "New exception vector base"
 358         depends on OVERRIDE_EXCEPTION_VECTOR_BASE
 359         range 0x80000000 0xbffff000
 360         default 0x80000000
 361         help
 362           The exception vector base to be restored before booting linux kernel
 363
 364 config INIT_STACK_WITHOUT_MALLOC_F
 365         bool "Do not reserve malloc space on initial stack"
 366         help
 367           Enable this option if you don't want to reserve malloc space on
 368           initial stack. This is useful if the initial stack can't hold large
 369           malloc space. Platform should set the malloc_base later when DRAM is
 370           ready to use.
 371
 372 config SPL_INIT_STACK_WITHOUT_MALLOC_F
 373         bool "Do not reserve malloc space on initial stack in SPL"
 374         help
 375           Enable this option if you don't want to reserve malloc space on
 376           initial stack. This is useful if the initial stack can't hold large
 377           malloc space. Platform should set the malloc_base later when DRAM is
 378           ready to use.
 379
 380 config SPL_LOADER_SUPPORT
 381         bool
 382         help
 383           Enable this option if you want to use SPL loaders without DM enabled.
 384
 385 endmenu
 386
 387 menu "OS boot interface"
 388
 389 config MIPS_BOOT_CMDLINE_LEGACY
 390         bool "Hand over legacy command line to Linux kernel"
 391         default y
 392         help
 393           Enable this option if you want U-Boot to hand over the Yamon-style
 394           command line to the kernel. All bootargs will be prepared as argc/argv
 395           compatible list. The argument count (argc) is stored in register $a0.
 396           The address of the argument list (argv) is stored in register $a1.
 397
 398 config MIPS_BOOT_ENV_LEGACY
 399         bool "Hand over legacy environment to Linux kernel"
 400         default y
 401         help
 402           Enable this option if you want U-Boot to hand over the Yamon-style
 403           environment to the kernel. Information like memory size, initrd
 404           address and size will be prepared as zero-terminated key/value list.
 405           The address of the environment is stored in register $a2.
 406
 407 config MIPS_BOOT_FDT
 408         bool "Hand over a flattened device tree to Linux kernel"
 409         help
 410           Enable this option if you want U-Boot to hand over a flattened
 411           device tree to the kernel. According to UHI register $a0 will be set
 412           to -2 and the FDT address is stored in $a1.
 413
 414 endmenu
 415
 416 config SUPPORTS_BIG_ENDIAN
 417         bool
 418
 419 config SUPPORTS_LITTLE_ENDIAN
 420         bool
 421
 422 config SUPPORTS_CPU_MIPS32_R1
 423         bool
 424
 425 config SUPPORTS_CPU_MIPS32_R2
 426         bool
 427
 428 config SUPPORTS_CPU_MIPS32_R6
 429         bool
 430
 431 config SUPPORTS_CPU_MIPS64_R1
 432         bool
 433
 434 config SUPPORTS_CPU_MIPS64_R2
 435         bool
 436
 437 config SUPPORTS_CPU_MIPS64_R6
 438         bool
 439
 440 config SUPPORTS_CPU_MIPS64_OCTEON
 441         bool
 442
 443 config HAS_FIXED_TIMER_FREQUENCY
 444         bool
 445
 446 config CPU_CAVIUM_OCTEON
 447         bool
 448
 449 config CPU_MIPS32
 450         bool
 451         default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
 452
 453 config CPU_MIPS64
 454         bool
 455         default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
 456         default y if CPU_MIPS64_OCTEON
 457
 458 config MIPS_TUNE_4KC
 459         bool
 460
 461 config MIPS_TUNE_14KC
 462         bool
 463
 464 config MIPS_TUNE_24KC
 465         bool
 466
 467 config MIPS_TUNE_34KC
 468         bool
 469
 470 config MIPS_TUNE_74KC
 471         bool
 472
 473 config MIPS_TUNE_OCTEON3
 474         bool
 475
 476 config SWAP_IO_SPACE
 477         bool
 478
 479 config SYS_MIPS_CACHE_INIT_RAM_LOAD
 480         bool
 481
 482 config MIPS_INIT_STACK_IN_SRAM
 483         bool
 484         help
 485           Select this if the initial stack frame could be setup in SRAM.
 486           Normally the initial stack frame is set up in DRAM which is often
 487           only available after lowlevel_init. With this option the initial
 488           stack frame and the early C environment is set up before
 489           lowlevel_init. Thus lowlevel_init does not need to be implemented
 490           in assembler.
 491
 492 config MIPS_SRAM_INIT
 493         bool
 494         depends on MIPS_INIT_STACK_IN_SRAM
 495         help
 496           Select this if the SRAM for initial stack needs to be initialized
 497           before it can be used. If enabled, a function mips_sram_init() will
 498           be called just before setup_stack_gd.
 499
 500 config DMA_ADDR_T_64BIT
 501         bool
 502         help
 503          Select this to enable 64-bit DMA addressing
 504
 505 config SYS_DCACHE_SIZE
 506         int
 507         default 0
 508         help
 509           The total size of the L1 Dcache, if known at compile time.
 510
 511 config SYS_DCACHE_LINE_SIZE
 512         int
 513         default 0
 514         help
 515           The size of L1 Dcache lines, if known at compile time.
 516
 517 config SYS_ICACHE_SIZE
 518         int
 519         default 0
 520         help
 521           The total size of the L1 ICache, if known at compile time.
 522
 523 config SYS_ICACHE_LINE_SIZE
 524         int
 525         default 0
 526         help
 527           The size of L1 Icache lines, if known at compile time.
 528
 529 config SYS_SCACHE_LINE_SIZE
 530         int
 531         default 0
 532         help
 533           The size of L2 cache lines, if known at compile time.
 534
 535
 536 config SYS_CACHE_SIZE_AUTO
 537         def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
 538                 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
 539                 SYS_SCACHE_LINE_SIZE = 0
 540         help
 541           Select this (or let it be auto-selected by not defining any cache
 542           sizes) in order to allow U-Boot to automatically detect the sizes
 543           of caches at runtime. This has a small cost in code size & runtime
 544           so if you know the cache configuration for your system at compile
 545           time it would be beneficial to configure it.
 546
 547 config MIPS_L2_CACHE
 548         bool
 549         help
 550           Select this if your system includes an L2 cache and you want U-Boot
 551           to initialise & maintain it.
 552
 553 config DYNAMIC_IO_PORT_BASE
 554         bool
 555
 556 config MIPS_CM
 557         bool
 558         help
 559           Select this if your system contains a MIPS Coherence Manager and you
 560           wish U-Boot to configure it or make use of it to retrieve system
 561           information such as cache configuration.
 562
 563 config MIPS_INSERT_BOOT_CONFIG
 564         bool
 565         help
 566           Enable this to insert some board-specific boot configuration in
 567           the U-Boot binary at offset 0x10.
 568
 569 config MIPS_BOOT_CONFIG_WORD0
 570         hex
 571         depends on MIPS_INSERT_BOOT_CONFIG
 572         default 0x420 if TARGET_MALTA
 573         default 0x0
 574         help
 575           Value which is inserted as boot config word 0.
 576
 577 config MIPS_BOOT_CONFIG_WORD1
 578         hex
 579         depends on MIPS_INSERT_BOOT_CONFIG
 580         default 0x0
 581         help
 582           Value which is inserted as boot config word 1.
 583
 584 endif
 585
 586 endmenu