1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2
9 default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2
12 prompt "Target select"
15 config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
17 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
26 select DYNAMIC_IO_PORT_BASE
27 select SUPPORTS_BIG_ENDIAN
28 select SUPPORTS_LITTLE_ENDIAN
29 select SUPPORTS_CPU_MIPS32_R1
30 select SUPPORTS_CPU_MIPS32_R2
32 select MIPS_L1_CACHE_SHIFT_6
36 select SUPPORTS_BIG_ENDIAN
37 select SUPPORTS_CPU_MIPS32_R1
38 select SUPPORTS_CPU_MIPS32_R2
39 select SYS_MIPS_CACHE_INIT_RAM_LOAD
41 config TARGET_DBAU1X00
42 bool "Support dbau1x00"
43 select SUPPORTS_BIG_ENDIAN
44 select SUPPORTS_LITTLE_ENDIAN
45 select SUPPORTS_CPU_MIPS32_R1
46 select SUPPORTS_CPU_MIPS32_R2
47 select SYS_MIPS_CACHE_INIT_RAM_LOAD
52 select SUPPORTS_LITTLE_ENDIAN
53 select SUPPORTS_CPU_MIPS32_R1
54 select SUPPORTS_CPU_MIPS32_R2
55 select SYS_MIPS_CACHE_INIT_RAM_LOAD
59 bool "Support Microchip PIC32"
65 source "board/dbau1x00/Kconfig"
66 source "board/imgtec/malta/Kconfig"
67 source "board/micronas/vct/Kconfig"
68 source "board/pb1x00/Kconfig"
69 source "board/qemu-mips/Kconfig"
70 source "arch/mips/mach-pic32/Kconfig"
75 prompt "Endianness selection"
77 Some MIPS boards can be configured for either little or big endian
78 byte order. These modes require different U-Boot images. In general there
79 is one preferred byteorder for a particular system but some systems are
80 just as commonly used in the one or the other endianness.
84 depends on SUPPORTS_BIG_ENDIAN
86 config SYS_LITTLE_ENDIAN
88 depends on SUPPORTS_LITTLE_ENDIAN
93 prompt "CPU selection"
97 bool "MIPS32 Release 1"
98 depends on SUPPORTS_CPU_MIPS32_R1
101 Choose this option to build an U-Boot for release 1 or later of the
105 bool "MIPS32 Release 2"
106 depends on SUPPORTS_CPU_MIPS32_R2
109 Choose this option to build an U-Boot for release 2 or later of the
113 bool "MIPS64 Release 1"
114 depends on SUPPORTS_CPU_MIPS64_R1
117 Choose this option to build a kernel for release 1 or later of the
121 bool "MIPS64 Release 2"
122 depends on SUPPORTS_CPU_MIPS64_R2
125 Choose this option to build a kernel for release 2 or later of the
130 menu "OS boot interface"
132 config MIPS_BOOT_CMDLINE_LEGACY
133 bool "Hand over legacy command line to Linux kernel"
136 Enable this option if you want U-Boot to hand over the Yamon-style
137 command line to the kernel. All bootargs will be prepared as argc/argv
138 compatible list. The argument count (argc) is stored in register $a0.
139 The address of the argument list (argv) is stored in register $a1.
141 config MIPS_BOOT_ENV_LEGACY
142 bool "Hand over legacy environment to Linux kernel"
145 Enable this option if you want U-Boot to hand over the Yamon-style
146 environment to the kernel. Information like memory size, initrd
147 address and size will be prepared as zero-terminated key/value list.
148 The address of the enviroment is stored in register $a2.
151 bool "Hand over a flattened device tree to Linux kernel"
154 Enable this option if you want U-Boot to hand over a flattened
155 device tree to the kernel. According to UHI register $a0 will be set
156 to -2 and the FDT address is stored in $a1.
160 config SUPPORTS_BIG_ENDIAN
163 config SUPPORTS_LITTLE_ENDIAN
166 config SUPPORTS_CPU_MIPS32_R1
169 config SUPPORTS_CPU_MIPS32_R2
172 config SUPPORTS_CPU_MIPS64_R1
175 config SUPPORTS_CPU_MIPS64_R2
180 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
184 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
189 config MIPS_TUNE_14KC
192 config MIPS_TUNE_24KC
204 config SYS_MIPS_CACHE_INIT_RAM_LOAD
207 config MIPS_L1_CACHE_SHIFT_4
210 config MIPS_L1_CACHE_SHIFT_5
213 config MIPS_L1_CACHE_SHIFT_6
216 config MIPS_L1_CACHE_SHIFT_7
219 config MIPS_L1_CACHE_SHIFT
221 default "7" if MIPS_L1_CACHE_SHIFT_7
222 default "6" if MIPS_L1_CACHE_SHIFT_6
223 default "5" if MIPS_L1_CACHE_SHIFT_5
224 default "4" if MIPS_L1_CACHE_SHIFT_4
227 config DYNAMIC_IO_PORT_BASE