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git.ipfire.org Git - thirdparty/u-boot.git/blob - arch/mips/cpu/mips32/au1x00/au1x00_eth.c
1 /* Only eth0 supported for now
4 * Thomas.Lange@corelatus.se
6 * SPDX-License-Identifier: GPL-2.0+
10 #if defined(CONFIG_SYS_DISCOVER_PHY)
11 #error "PHY not supported yet"
12 /* We just assume that we are running 100FD for now */
13 /* We all use switches, right? ;-) */
16 /* I assume ethernet behaves like au1000 */
18 #ifdef CONFIG_SOC_AU1000
19 /* Base address differ between cpu:s */
20 #define ETH0_BASE AU1000_ETH0_BASE
21 #define MAC0_ENABLE AU1000_MAC0_ENABLE
23 #ifdef CONFIG_SOC_AU1100
24 #define ETH0_BASE AU1100_ETH0_BASE
25 #define MAC0_ENABLE AU1100_MAC0_ENABLE
27 #ifdef CONFIG_SOC_AU1500
28 #define ETH0_BASE AU1500_ETH0_BASE
29 #define MAC0_ENABLE AU1500_MAC0_ENABLE
31 #ifdef CONFIG_SOC_AU1550
32 #define ETH0_BASE AU1550_ETH0_BASE
33 #define MAC0_ENABLE AU1550_MAC0_ENABLE
35 #error "No valid cpu set"
46 #include <asm/au1x00.h>
48 #if defined(CONFIG_CMD_MII)
52 /* Ethernet Transmit and Receive Buffers */
53 #define DBUF_LENGTH 1520
54 #define PKT_MAXBUF_SIZE 1518
56 static char txbuf
[DBUF_LENGTH
];
61 /* 4 rx and 4 tx fifos */
67 u32 len
; /* Only used for tx */
71 mac_fifo_t mac_fifo
[NO_OF_FIFOS
];
75 #if defined(CONFIG_CMD_MII)
76 int au1x00_miiphy_read(const char *devname
, unsigned char addr
,
77 unsigned char reg
, unsigned short * value
)
79 volatile u32
*mii_control_reg
= (volatile u32
*)(ETH0_BASE
+MAC_MII_CNTRL
);
80 volatile u32
*mii_data_reg
= (volatile u32
*)(ETH0_BASE
+MAC_MII_DATA
);
82 unsigned int timedout
= 20;
84 while (*mii_control_reg
& MAC_MII_BUSY
) {
86 if (--timedout
== 0) {
87 printf("au1x00_eth: miiphy_read busy timeout!!\n");
92 mii_control
= MAC_SET_MII_SELECT_REG(reg
) |
93 MAC_SET_MII_SELECT_PHY(addr
) | MAC_MII_READ
;
95 *mii_control_reg
= mii_control
;
98 while (*mii_control_reg
& MAC_MII_BUSY
) {
100 if (--timedout
== 0) {
101 printf("au1x00_eth: miiphy_read busy timeout!!\n");
105 *value
= *mii_data_reg
;
109 int au1x00_miiphy_write(const char *devname
, unsigned char addr
,
110 unsigned char reg
, unsigned short value
)
112 volatile u32
*mii_control_reg
= (volatile u32
*)(ETH0_BASE
+MAC_MII_CNTRL
);
113 volatile u32
*mii_data_reg
= (volatile u32
*)(ETH0_BASE
+MAC_MII_DATA
);
115 unsigned int timedout
= 20;
117 while (*mii_control_reg
& MAC_MII_BUSY
) {
119 if (--timedout
== 0) {
120 printf("au1x00_eth: miiphy_write busy timeout!!\n");
125 mii_control
= MAC_SET_MII_SELECT_REG(reg
) |
126 MAC_SET_MII_SELECT_PHY(addr
) | MAC_MII_WRITE
;
128 *mii_data_reg
= value
;
129 *mii_control_reg
= mii_control
;
134 static int au1x00_send(struct eth_device
*dev
, void *packet
, int length
)
136 volatile mac_fifo_t
*fifo_tx
=
137 (volatile mac_fifo_t
*)(MAC0_TX_DMA_ADDR
+MAC_TX_BUFF0_STATUS
);
141 /* tx fifo should always be idle */
142 fifo_tx
[next_tx
].len
= length
;
143 fifo_tx
[next_tx
].addr
= (virt_to_phys(packet
))|TX_DMA_ENABLE
;
148 while(!(fifo_tx
[next_tx
].addr
&TX_T_DONE
)){
150 printf("TX timeout\n");
158 fifo_tx
[next_tx
].addr
= 0;
159 fifo_tx
[next_tx
].len
= 0;
162 res
= fifo_tx
[next_tx
].status
;
165 if(next_tx
>=NO_OF_FIFOS
){
171 static int au1x00_recv(struct eth_device
* dev
){
172 volatile mac_fifo_t
*fifo_rx
=
173 (volatile mac_fifo_t
*)(MAC0_RX_DMA_ADDR
+MAC_RX_BUFF0_STATUS
);
179 if(!(fifo_rx
[next_rx
].addr
&RX_T_DONE
)){
180 /* Nothing has been received */
184 status
= fifo_rx
[next_rx
].status
;
186 length
= status
&0x3FFF;
189 printf("Rx error 0x%x\n", status
);
192 /* Pass the packet up to the protocol layers. */
193 NetReceive(NetRxPackets
[next_rx
], length
- 4);
196 fifo_rx
[next_rx
].addr
= (virt_to_phys(NetRxPackets
[next_rx
]))|RX_DMA_ENABLE
;
199 if(next_rx
>=NO_OF_FIFOS
){
204 return(0); /* Does anyone use this? */
207 static int au1x00_init(struct eth_device
* dev
, bd_t
* bd
){
209 volatile u32
*macen
= (volatile u32
*)MAC0_ENABLE
;
210 volatile u32
*mac_ctrl
= (volatile u32
*)(ETH0_BASE
+MAC_CONTROL
);
211 volatile u32
*mac_addr_high
= (volatile u32
*)(ETH0_BASE
+MAC_ADDRESS_HIGH
);
212 volatile u32
*mac_addr_low
= (volatile u32
*)(ETH0_BASE
+MAC_ADDRESS_LOW
);
213 volatile u32
*mac_mcast_high
= (volatile u32
*)(ETH0_BASE
+MAC_MCAST_HIGH
);
214 volatile u32
*mac_mcast_low
= (volatile u32
*)(ETH0_BASE
+MAC_MCAST_LOW
);
215 volatile mac_fifo_t
*fifo_tx
=
216 (volatile mac_fifo_t
*)(MAC0_TX_DMA_ADDR
+MAC_TX_BUFF0_STATUS
);
217 volatile mac_fifo_t
*fifo_rx
=
218 (volatile mac_fifo_t
*)(MAC0_RX_DMA_ADDR
+MAC_RX_BUFF0_STATUS
);
221 next_tx
= TX_GET_DMA_BUFFER(fifo_tx
[0].addr
);
222 next_rx
= RX_GET_DMA_BUFFER(fifo_rx
[0].addr
);
224 /* We have to enable clocks before releasing reset */
225 *macen
= MAC_EN_CLOCK_ENABLE
;
229 /* We have to release reset before accessing registers */
230 *macen
= MAC_EN_CLOCK_ENABLE
|MAC_EN_RESET0
|
231 MAC_EN_RESET1
|MAC_EN_RESET2
;
234 for(i
=0;i
<NO_OF_FIFOS
;i
++){
236 fifo_tx
[i
].addr
= virt_to_phys(&txbuf
[0]);
237 fifo_rx
[i
].addr
= (virt_to_phys(NetRxPackets
[i
]))|RX_DMA_ENABLE
;
240 /* Put mac addr in little endian */
241 #define ea eth_get_dev()->enetaddr
242 *mac_addr_high
= (ea
[5] << 8) | (ea
[4] ) ;
243 *mac_addr_low
= (ea
[3] << 24) | (ea
[2] << 16) |
244 (ea
[1] << 8) | (ea
[0] ) ;
249 /* Make sure the MAC buffer is in the correct endian mode */
250 #ifdef __LITTLE_ENDIAN
251 *mac_ctrl
= MAC_FULL_DUPLEX
;
253 *mac_ctrl
= MAC_FULL_DUPLEX
|MAC_RX_ENABLE
|MAC_TX_ENABLE
;
255 *mac_ctrl
= MAC_BIG_ENDIAN
|MAC_FULL_DUPLEX
;
257 *mac_ctrl
= MAC_BIG_ENDIAN
|MAC_FULL_DUPLEX
|MAC_RX_ENABLE
|MAC_TX_ENABLE
;
263 static void au1x00_halt(struct eth_device
* dev
){
264 volatile u32
*macen
= (volatile u32
*)MAC0_ENABLE
;
266 /* Put MAC0 in reset */
270 int au1x00_enet_initialize(bd_t
*bis
){
271 struct eth_device
* dev
;
273 if ((dev
= (struct eth_device
*)malloc(sizeof *dev
)) == NULL
) {
274 puts ("malloc failed\n");
278 memset(dev
, 0, sizeof *dev
);
280 sprintf(dev
->name
, "Au1X00 ethernet");
283 dev
->init
= au1x00_init
;
284 dev
->halt
= au1x00_halt
;
285 dev
->send
= au1x00_send
;
286 dev
->recv
= au1x00_recv
;
290 #if defined(CONFIG_CMD_MII)
291 miiphy_register(dev
->name
,
292 au1x00_miiphy_read
, au1x00_miiphy_write
);