arch/mips/cpu/start.S

   1 /*
   2  *  Startup Code for MIPS32 CPU-core
   3  *
   4  *  Copyright (c) 2003  Wolfgang Denk <wd@denx.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm-offsets.h>
  10 #include <config.h>
  11 #include <asm/asm.h>
  12 #include <asm/regdef.h>
  13 #include <asm/mipsregs.h>
  14
  15 #ifndef CONFIG_SYS_INIT_SP_ADDR
  16 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
  17                                 CONFIG_SYS_INIT_SP_OFFSET)
  18 #endif
  19
  20 #ifdef CONFIG_32BIT
  21 # define MIPS_RELOC     3
  22 # define STATUS_SET     0
  23 #endif
  24
  25 #ifdef CONFIG_64BIT
  26 # ifdef CONFIG_SYS_LITTLE_ENDIAN
  27 #  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
  28         (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
  29 # else
  30 #  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
  31         ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
  32 # endif
  33 # define MIPS_RELOC     MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
  34 # define STATUS_SET     ST0_KX
  35 #endif
  36
  37         /*
  38          * For the moment disable interrupts, mark the kernel mode and
  39          * set ST0_KX so that the CPU does not spit fire when using
  40          * 64-bit addresses.
  41          */
  42         .macro  setup_c0_status set clr
  43         .set    push
  44         mfc0    t0, CP0_STATUS
  45         or      t0, ST0_CU0 | \set | 0x1f | \clr
  46         xor     t0, 0x1f | \clr
  47         mtc0    t0, CP0_STATUS
  48         .set    noreorder
  49         sll     zero, 3                         # ehb
  50         .set    pop
  51         .endm
  52
  53         .set noreorder
  54
  55 ENTRY(_start)
  56         /* U-Boot entry point */
  57         b       reset
  58          nop
  59
  60         .org 0x10
  61 #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
  62         /*
  63          * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
  64          * access external NOR flashes. If the board boots from NOR flash the
  65          * internal BootROM does a blind read at address 0xB0000010 to read the
  66          * initial configuration for that EBU in order to access the flash
  67          * device with correct parameters. This config option is board-specific.
  68          */
  69         .word CONFIG_SYS_XWAY_EBU_BOOTCFG
  70         .word 0x0
  71 #elif defined(CONFIG_MALTA)
  72         /*
  73          * Linux expects the Board ID here.
  74          */
  75         .word 0x00000420        # 0x420 (Malta Board with CoreLV)
  76         .word 0x00000000
  77 #endif
  78
  79         .org 0x200
  80         /* TLB refill, 32 bit task */
  81 1:      b       1b
  82          nop
  83
  84         .org 0x280
  85         /* XTLB refill, 64 bit task */
  86 1:      b       1b
  87          nop
  88
  89         .org 0x300
  90         /* Cache error exception */
  91 1:      b       1b
  92          nop
  93
  94         .org 0x380
  95         /* General exception */
  96 1:      b       1b
  97          nop
  98
  99         .org 0x400
 100         /* Catch interrupt exceptions */
 101 1:      b       1b
 102          nop
 103
 104         .org 0x480
 105         /* EJTAG debug exception */
 106 1:      b       1b
 107          nop
 108
 109         .align 4
 110 reset:
 111
 112         /* Clear watch registers */
 113         MTC0    zero, CP0_WATCHLO
 114         mtc0    zero, CP0_WATCHHI
 115
 116         /* WP(Watch Pending), SW0/1 should be cleared */
 117         mtc0    zero, CP0_CAUSE
 118
 119         setup_c0_status STATUS_SET 0
 120
 121         /* Init Timer */
 122         mtc0    zero, CP0_COUNT
 123         mtc0    zero, CP0_COMPARE
 124
 125 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 126         /* CONFIG0 register */
 127         li      t0, CONF_CM_UNCACHED
 128         mtc0    t0, CP0_CONFIG
 129 #endif
 130
 131         /*
 132          * Initialize $gp, force pointer sized alignment of bal instruction to
 133          * forbid the compiler to put nop's between bal and _gp. This is
 134          * required to keep _gp and ra aligned to 8 byte.
 135          */
 136         .align  PTRLOG
 137         bal     1f
 138          nop
 139         PTR     _gp
 140 1:
 141         PTR_L   gp, 0(ra)
 142
 143 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 144         /* Initialize any external memory */
 145         PTR_LA  t9, lowlevel_init
 146         jalr    t9
 147          nop
 148
 149         /* Initialize caches... */
 150         PTR_LA  t9, mips_cache_reset
 151         jalr    t9
 152          nop
 153 #endif
 154
 155         /* Set up temporary stack */
 156         li      t0, -16
 157         PTR_LI  t1, CONFIG_SYS_INIT_SP_ADDR
 158         and     sp, t1, t0              # force 16 byte alignment
 159         PTR_SUBU \
 160                 sp, sp, GD_SIZE         # reserve space for gd
 161         and     sp, sp, t0              # force 16 byte alignment
 162         move    k0, sp                  # save gd pointer
 163 #ifdef CONFIG_SYS_MALLOC_F_LEN
 164         li      t2, CONFIG_SYS_MALLOC_F_LEN
 165         PTR_SUBU \
 166                 sp, sp, t2              # reserve space for early malloc
 167         and     sp, sp, t0              # force 16 byte alignment
 168 #endif
 169         move    fp, sp
 170
 171         /* Clear gd */
 172         move    t0, k0
 173 1:
 174         PTR_S   zero, 0(t0)
 175         blt     t0, t1, 1b
 176          PTR_ADDIU t0, PTRSIZE
 177
 178 #ifdef CONFIG_SYS_MALLOC_F_LEN
 179         PTR_S   sp, GD_MALLOC_BASE(k0)  # gd->malloc_base offset
 180 #endif
 181
 182         move    a0, zero                # a0 <-- boot_flags = 0
 183         PTR_LA  t9, board_init_f
 184         jr      t9
 185          move   ra, zero
 186
 187         END(_start)
 188
 189 /*
 190  * void relocate_code (addr_sp, gd, addr_moni)
 191  *
 192  * This "function" does not return, instead it continues in RAM
 193  * after relocating the monitor code.
 194  *
 195  * a0 = addr_sp
 196  * a1 = gd
 197  * a2 = destination address
 198  */
 199 ENTRY(relocate_code)
 200         move    sp, a0                  # set new stack pointer
 201         move    fp, sp
 202
 203         move    s0, a1                  # save gd in s0
 204         move    s2, a2                  # save destination address in s2
 205
 206         PTR_LI  t0, CONFIG_SYS_MONITOR_BASE
 207         PTR_SUB s1, s2, t0              # s1 <-- relocation offset
 208
 209         PTR_LA  t3, in_ram
 210         PTR_L   t2, -(3 * PTRSIZE)(t3)  # t2 <-- __image_copy_end
 211         move    t1, a2
 212
 213         PTR_ADD gp, s1                  # adjust gp
 214
 215         /*
 216          * t0 = source address
 217          * t1 = target address
 218          * t2 = source end address
 219          */
 220 1:
 221         PTR_L   t3, 0(t0)
 222         PTR_S   t3, 0(t1)
 223         PTR_ADDU t0, PTRSIZE
 224         blt     t0, t2, 1b
 225          PTR_ADDU t1, PTRSIZE
 226
 227         /* If caches were enabled, we would have to flush them here. */
 228         PTR_SUB a1, t1, s2              # a1 <-- size
 229         PTR_LA  t9, flush_cache
 230         jalr    t9
 231          move   a0, s2                  # a0 <-- destination address
 232
 233         /* Jump to where we've relocated ourselves */
 234         PTR_ADDIU t0, s2, in_ram - _start
 235         jr      t0
 236          nop
 237
 238         PTR     __rel_dyn_end
 239         PTR     __rel_dyn_start
 240         PTR     __image_copy_end
 241         PTR     _GLOBAL_OFFSET_TABLE_
 242         PTR     num_got_entries
 243
 244 in_ram:
 245         /*
 246          * Now we want to update GOT.
 247          *
 248          * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
 249          * generated by GNU ld. Skip these reserved entries from relocation.
 250          */
 251         PTR_L   t3, -(1 * PTRSIZE)(t0)  # t3 <-- num_got_entries
 252         PTR_L   t8, -(2 * PTRSIZE)(t0)  # t8 <-- _GLOBAL_OFFSET_TABLE_
 253         PTR_ADD t8, s1                  # t8 now holds relocated _G_O_T_
 254         PTR_ADDIU t8, t8, 2 * PTRSIZE   # skipping first two entries
 255         PTR_LI  t2, 2
 256 1:
 257         PTR_L   t1, 0(t8)
 258         beqz    t1, 2f
 259          PTR_ADD t1, s1
 260         PTR_S   t1, 0(t8)
 261 2:
 262         PTR_ADDIU t2, 1
 263         blt     t2, t3, 1b
 264          PTR_ADDIU t8, PTRSIZE
 265
 266         /* Update dynamic relocations */
 267         PTR_L   t1, -(4 * PTRSIZE)(t0)  # t1 <-- __rel_dyn_start
 268         PTR_L   t2, -(5 * PTRSIZE)(t0)  # t2 <-- __rel_dyn_end
 269
 270         b       2f                      # skip first reserved entry
 271          PTR_ADDIU t1, 2 * PTRSIZE
 272
 273 1:
 274         lw      t8, -4(t1)              # t8 <-- relocation info
 275
 276         PTR_LI  t3, MIPS_RELOC
 277         bne     t8, t3, 2f              # skip non-MIPS_RELOC entries
 278          nop
 279
 280         PTR_L   t3, -(2 * PTRSIZE)(t1)  # t3 <-- location to fix up in FLASH
 281
 282         PTR_L   t8, 0(t3)               # t8 <-- original pointer
 283         PTR_ADD t8, s1                  # t8 <-- adjusted pointer
 284
 285         PTR_ADD t3, s1                  # t3 <-- location to fix up in RAM
 286         PTR_S   t8, 0(t3)
 287
 288 2:
 289         blt     t1, t2, 1b
 290          PTR_ADDIU t1, 2 * PTRSIZE      # each rel.dyn entry is 2*PTRSIZE bytes
 291
 292         /*
 293          * Clear BSS
 294          *
 295          * GOT is now relocated. Thus __bss_start and __bss_end can be
 296          * accessed directly via $gp.
 297          */
 298         PTR_LA  t1, __bss_start         # t1 <-- __bss_start
 299         PTR_LA  t2, __bss_end           # t2 <-- __bss_end
 300
 301 1:
 302         PTR_S   zero, 0(t1)
 303         blt     t1, t2, 1b
 304          PTR_ADDIU t1, PTRSIZE
 305
 306         move    a0, s0                  # a0 <-- gd
 307         move    a1, s2
 308         PTR_LA  t9, board_init_r
 309         jr      t9
 310          move   ra, zero
 311
 312         END(relocate_code)