arch/mips/ddb5xxx/ddb5476/nile4_pic.c

   1 /*
   2  *  arch/mips/ddb5476/nile4.c --
   3  *      low-level PIC code for NEC Vrc-5476 (Nile 4)
   4  *
   5  *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
   6  *                     Sony Software Development Center Europe (SDCE), Brussels
   7  *
   8  *  Copyright 2001 MontaVista Software Inc.
   9  *  Author: jsun@mvista.com or jsun@junsun.net
  10  *
  11  */
  12 #include <linux/config.h>
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15
  16 #include <asm/addrspace.h>
  17
  18 #include <asm/ddb5xxx/ddb5xxx.h>
  19
  20
  21 /*
  22  *  Interrupt Programming
  23  */
  24 void nile4_map_irq(int nile4_irq, int cpu_irq)
  25 {
  26         u32 offset, t;
  27
  28         offset = DDB_INTCTRL;
  29         if (nile4_irq >= 8) {
  30                 offset += 4;
  31                 nile4_irq -= 8;
  32         }
  33         t = ddb_in32(offset);
  34         t &= ~(7 << (nile4_irq * 4));
  35         t |= cpu_irq << (nile4_irq * 4);
  36         ddb_out32(offset, t);
  37 }
  38
  39 void nile4_map_irq_all(int cpu_irq)
  40 {
  41         u32 all, t;
  42
  43         all = cpu_irq;
  44         all |= all << 4;
  45         all |= all << 8;
  46         all |= all << 16;
  47         t = ddb_in32(DDB_INTCTRL);
  48         t &= 0x88888888;
  49         t |= all;
  50         ddb_out32(DDB_INTCTRL, t);
  51         t = ddb_in32(DDB_INTCTRL + 4);
  52         t &= 0x88888888;
  53         t |= all;
  54         ddb_out32(DDB_INTCTRL + 4, t);
  55 }
  56
  57 void nile4_enable_irq(int nile4_irq)
  58 {
  59         u32 offset, t;
  60
  61         offset = DDB_INTCTRL;
  62         if (nile4_irq >= 8) {
  63                 offset += 4;
  64                 nile4_irq -= 8;
  65         }
  66         t = ddb_in32(offset);
  67         t |= 8 << (nile4_irq * 4);
  68         ddb_out32(offset, t);
  69 }
  70
  71 void nile4_disable_irq(int nile4_irq)
  72 {
  73         u32 offset, t;
  74
  75         offset = DDB_INTCTRL;
  76         if (nile4_irq >= 8) {
  77                 offset += 4;
  78                 nile4_irq -= 8;
  79         }
  80         t = ddb_in32(offset);
  81         t &= ~(8 << (nile4_irq * 4));
  82         ddb_out32(offset, t);
  83 }
  84
  85 void nile4_disable_irq_all(void)
  86 {
  87         ddb_out32(DDB_INTCTRL, 0);
  88         ddb_out32(DDB_INTCTRL + 4, 0);
  89 }
  90
  91 u16 nile4_get_irq_stat(int cpu_irq)
  92 {
  93         return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
  94 }
  95
  96 void nile4_enable_irq_output(int cpu_irq)
  97 {
  98         u32 t;
  99
 100         t = ddb_in32(DDB_INTSTAT1 + 4);
 101         t |= 1 << (16 + cpu_irq);
 102         ddb_out32(DDB_INTSTAT1, t);
 103 }
 104
 105 void nile4_disable_irq_output(int cpu_irq)
 106 {
 107         u32 t;
 108
 109         t = ddb_in32(DDB_INTSTAT1 + 4);
 110         t &= ~(1 << (16 + cpu_irq));
 111         ddb_out32(DDB_INTSTAT1, t);
 112 }
 113
 114 void nile4_set_pci_irq_polarity(int pci_irq, int high)
 115 {
 116         u32 t;
 117
 118         t = ddb_in32(DDB_INTPPES);
 119         if (high)
 120                 t &= ~(1 << (pci_irq * 2));
 121         else
 122                 t |= 1 << (pci_irq * 2);
 123         ddb_out32(DDB_INTPPES, t);
 124 }
 125
 126 void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
 127 {
 128         u32 t;
 129
 130         t = ddb_in32(DDB_INTPPES);
 131         if (level)
 132                 t |= 2 << (pci_irq * 2);
 133         else
 134                 t &= ~(2 << (pci_irq * 2));
 135         ddb_out32(DDB_INTPPES, t);
 136 }
 137
 138 void nile4_clear_irq(int nile4_irq)
 139 {
 140         ddb_out32(DDB_INTCLR, 1 << nile4_irq);
 141 }
 142
 143 void nile4_clear_irq_mask(u32 mask)
 144 {
 145         ddb_out32(DDB_INTCLR, mask);
 146 }
 147
 148 u8 nile4_i8259_iack(void)
 149 {
 150         u8 irq;
 151         u32 reg;
 152
 153         /* Set window 0 for interrupt acknowledge */
 154         reg = ddb_in32(DDB_PCIINIT0);
 155
 156         ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
 157         irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
 158         /* restore window 0 for PCI I/O space */
 159         // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
 160         ddb_out32(DDB_PCIINIT0, reg);
 161
 162         /* i8269.c set the base vector to be 0x0 */
 163         return irq + I8259_IRQ_BASE;
 164 }
 165
 166 #if defined(CONFIG_RUNTIME_DEBUG)
 167 void nile4_dump_irq_status(void)
 168 {
 169         printk(KERN_DEBUG "
 170                CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
 171                (void *) ddb_in32(DDB_CPUSTAT));
 172         printk(KERN_DEBUG "
 173                INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
 174                (void *) ddb_in32(DDB_INTCTRL));
 175         printk(KERN_DEBUG
 176                "INTSTAT0 = %p:%p\n",
 177                (void *) ddb_in32(DDB_INTSTAT0 + 4),
 178                (void *) ddb_in32(DDB_INTSTAT0));
 179         printk(KERN_DEBUG
 180                "INTSTAT1 = %p:%p\n",
 181                (void *) ddb_in32(DDB_INTSTAT1 + 4),
 182                (void *) ddb_in32(DDB_INTSTAT1));
 183         printk(KERN_DEBUG
 184                "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
 185                (void *) ddb_in32(DDB_INTCLR));
 186         printk(KERN_DEBUG
 187                "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
 188                (void *) ddb_in32(DDB_INTPPES));
 189 }
 190 #endif