arch/mips/dts/mrvl,cn73xx.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Marvell / Cavium Inc. CN73xx
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/clock/octeon-clock.h>
   9
  10 / {
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         soc0: soc@0 {
  15                 interrupt-parent = <&ciu3>;
  16                 compatible = "simple-bus";
  17                 #address-cells = <2>;
  18                 #size-cells = <2>;
  19                 ranges; /* Direct mapping */
  20
  21                 ciu3: interrupt-controller@1010000000000 {
  22                         compatible = "cavium,octeon-7890-ciu3";
  23                         interrupt-controller;
  24                         /*
  25                          * Interrupts are specified by two parts:
  26                          * 1) Source number (20 significant bits)
  27                          * 2) Trigger type: (4 == level, 1 == edge)
  28                          */
  29                         #address-cells = <0>;
  30                         #interrupt-cells = <2>;
  31                         reg = <0x10100 0x00000000 0x0 0xb0000000>;
  32                 };
  33
  34                 bootbus: bootbus@1180000000000 {
  35                         compatible = "cavium,octeon-3860-bootbus","simple-bus";
  36                         reg = <0x11800 0x00000000 0x0 0x200>;
  37                         /* The chip select number and offset */
  38                         #address-cells = <2>;
  39                         /* The size of the chip select region */
  40                         #size-cells = <1>;
  41                 };
  42
  43                 clk: clock {
  44                         compatible = "mrvl,octeon-clk";
  45                         #clock-cells = <1>;
  46                         bootph-all;
  47                 };
  48
  49                 gpio: gpio-controller@1070000000800 {
  50                         #gpio-cells = <2>;
  51                         compatible = "cavium,octeon-7890-gpio";
  52                         reg = <0x10700 0x00000800 0x0 0x100>;
  53                         gpio-controller;
  54                         nr-gpios = <32>;
  55                         /* Interrupts are specified by two parts:
  56                          * 1) GPIO pin number (0..15)
  57                          * 2) Triggering (1 - edge rising
  58                          *                2 - edge falling
  59                          *                4 - level active high
  60                          *                8 - level active low)
  61                          */
  62                         interrupt-controller;
  63                         #interrupt-cells = <2>;
  64                         /* The GPIO pins connect to 16 consecutive CUI bits */
  65                         interrupts = <0x03000 4>, <0x03001 4>,
  66                                      <0x03002 4>, <0x03003 4>,
  67                                      <0x03004 4>, <0x03005 4>,
  68                                      <0x03006 4>, <0x03007 4>,
  69                                      <0x03008 4>, <0x03009 4>,
  70                                      <0x0300a 4>, <0x0300b 4>,
  71                                      <0x0300c 4>, <0x0300d 4>,
  72                                      <0x0300e 4>, <0x0300f 4>;
  73                 };
  74
  75                 l2c: l2c@1180080000000 {
  76                         #address-cells = <1>;
  77                         #size-cells = <0>;
  78                         compatible = "cavium,octeon-7xxx-l2c";
  79                         reg = <0x11800 0x80000000 0x0 0x01000000>;
  80                         bootph-all;
  81                 };
  82
  83                 lmc: lmc@1180088000000 {
  84                         #address-cells = <1>;
  85                         #size-cells = <0>;
  86                         compatible = "cavium,octeon-7xxx-ddr4";
  87                         reg = <0x11800 0x88000000 0x0 0x02000000>; // 2 IFs
  88                         bootph-all;
  89                         l2c-handle = <&l2c>;
  90                 };
  91
  92                 reset: reset@1180006001600 {
  93                         compatible = "mrvl,cn7xxx-rst";
  94                         reg = <0x11800 0x06001600 0x0 0x200>;
  95                 };
  96
  97                 uart0: serial@1180000000800 {
  98                         compatible = "cavium,octeon-3860-uart","ns16550";
  99                         reg = <0x11800 0x00000800 0x0 0x400>;
 100                         clocks = <&clk OCTEON_CLK_IO>;
 101                         clock-frequency = <0>;
 102                         current-speed = <115200>;
 103                         reg-shift = <3>;
 104                         interrupts = <0x08000 4>;
 105                 };
 106
 107                 uart1: serial@1180000000c00 {
 108                         compatible = "cavium,octeon-3860-uart","ns16550";
 109                         reg = <0x11800 0x00000c00 0x0 0x400>;
 110                         clocks = <&clk OCTEON_CLK_IO>;
 111                         clock-frequency = <0>;
 112                         current-speed = <115200>;
 113                         reg-shift = <3>;
 114                         interrupts = <0x08040 4>;
 115                 };
 116
 117                 i2c0: i2c@1180000001000 {
 118                         #address-cells = <1>;
 119                         #size-cells = <0>;
 120                         compatible = "cavium,octeon-7890-twsi";
 121                         reg = <0x11800 0x00001000 0x0 0x200>;
 122                         /* INT_ST, INT_TS, INT_CORE */
 123                         interrupts = <0x0b000 1>, <0x0b001 1>, <0x0b002 1>;
 124                         clock-frequency = <100000>;
 125                         clocks = <&clk OCTEON_CLK_IO>;
 126                 };
 127
 128                 i2c1: i2c@1180000001200 {
 129                         #address-cells = <1>;
 130                         #size-cells = <0>;
 131                         compatible = "cavium,octeon-7890-twsi";
 132                         reg = <0x11800 0x00001200 0x0 0x200>;
 133                         /* INT_ST, INT_TS, INT_CORE */
 134                         interrupts = <0x0b100 1>, <0x0b101 1>, <0x0b102 1>;
 135                         clock-frequency = <100000>;
 136                         clocks = <&clk OCTEON_CLK_IO>;
 137                 };
 138
 139                 mmc: mmc@1180000002000 {
 140                         compatible = "cavium,octeon-7890-mmc",
 141                                      "cavium,octeon-7360-mmc";
 142                         reg = <0x11800 0x00000000 0x0 0x2100>;
 143                         #address-cells = <1>;
 144                         #size-cells = <0>;
 145                         /* EMM_INT_BUF_DONE,
 146                            EMM_INT_CMD_DONE,
 147                            EMM_INT_DMA_DONE,
 148                            EMM_INT_CMD_ERR,
 149                            EMM_INT_DMA_ERR,
 150                            EMM_INT_SWITCH_DONE,
 151                            EMM_INT_SWITCH_ERR,
 152                            EMM_DMA_DONE,
 153                            EMM_DMA_FIFO*/
 154                         interrupts = <0x09040 1>,
 155                                      <0x09041 1>,
 156                                      <0x09042 1>,
 157                                      <0x09043 1>,
 158                                      <0x09044 1>,
 159                                      <0x09045 1>,
 160                                      <0x09046 1>,
 161                                      <0x09000 1>,
 162                                      <0x09001 1>;
 163                         clocks = <&clk OCTEON_CLK_IO>;
 164                 };
 165
 166                 spi: spi@1070000001000 {
 167                         compatible = "cavium,octeon-3010-spi";
 168                         reg = <0x10700 0x00001000 0x0 0x100>;
 169                         interrupts = <0x05001 1>;
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172                         spi-max-frequency = <25000000>;
 173                         clocks = <&clk OCTEON_CLK_IO>;
 174                 };
 175
 176                 /* USB 0 */
 177                 usb0: uctl@1180068000000 {
 178                         compatible = "cavium,octeon-7130-usb-uctl";
 179                         reg = <0x11800 0x68000000 0x0 0x100>;
 180                         ranges; /* Direct mapping */
 181                         #address-cells = <2>;
 182                         #size-cells = <2>;
 183                         /* Only 100MHz allowed */
 184                         refclk-frequency = <100000000>;
 185                         /* Only "dlmc_ref_clk0" is supported for 73xx */
 186                         refclk-type-ss = "dlmc_ref_clk0";
 187                         /* Only "dlmc_ref_clk0" is supported for 73xx */
 188                         refclk-type-hs = "dlmc_ref_clk0";
 189
 190                         /*
 191                          * Power is specified by three parts:
 192                          * 1) GPIO handle (must be &gpio)
 193                          * 2) GPIO pin number
 194                          * 3) Active high (0) or active low (1)
 195                          */
 196                         xhci@1680000000000 {
 197                                 compatible = "cavium,octeon-7130-xhci","synopsys,dwc3","snps,dwc3";
 198                                 reg = <0x16800 0x00000000 0x10 0x0>;
 199                                 interrupts = <0x68080 4>; /* UAHC_IMAN, level */
 200                                 maximum-speed = "super-speed";
 201                                 dr_mode = "host";
 202                                 snps,dis_u3_susphy_quirk;
 203                                 snps,dis_u2_susphy_quirk;
 204                                 snps,dis_enblslpm_quirk;
 205                         };
 206                 };
 207
 208                 /* USB 1 */
 209                 usb1: uctl@1180069000000 {
 210                         compatible = "cavium,octeon-7130-usb-uctl";
 211                         reg = <0x11800 0x69000000 0x0 0x100>;
 212                         ranges; /* Direct mapping */
 213                         #address-cells = <2>;
 214                         #size-cells = <2>;
 215                         /* 50MHz, 100MHz and 125MHz allowed */
 216                         refclk-frequency = <100000000>;
 217                         /* Either "dlmc_ref_clk0" or "dlmc_ref_clk0" */
 218                         refclk-type-ss = "dlmc_ref_clk0";
 219                         /* Either "dlmc_ref_clk0" "dlmc_ref_clk1" or "pll_ref_clk" */
 220                         refclk-type-hs = "dlmc_ref_clk0";
 221
 222                         /*
 223                          * Power is specified by three parts:
 224                          * 1) GPIO handle (must be &gpio)
 225                          * 2) GPIO pin number
 226                          * 3) Active high (0) or active low (1)
 227                          */
 228                         xhci@1690000000000 {
 229                                 compatible = "cavium,octeon-7130-xhci","synopsys,dwc3","snps,dwc3";
 230                                 reg = <0x16900 0x00000000 0x10 0x0>;
 231                                 interrupts = <0x69080 4>; /* UAHC_IMAN, level */
 232                                 dr_mode = "host";
 233                         };
 234                 };
 235
 236                 /* PCIe 0 */
 237                 pcie0: pcie@1180069000000 {
 238                         compatible =  "marvell,pcie-host-octeon";
 239                         reg = <0 0xf2600000 0 0x10000>;
 240                         #address-cells = <3>;
 241                         #size-cells = <2>;
 242                         device_type = "pci";
 243                         dma-coherent;
 244
 245                         bus-range = <0 0xff>;
 246                         marvell,pcie-port = <0>;
 247                         ranges = <0x81000000 0x00000000 0xd0000000 0x00011a00 0xd0000000 0x00000000 0x01000000 /* IO */
 248                                   0x02000000 0x00000000 0xe0000000 0x00011b00 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
 249                                   0x43000000 0x00011c00 0x00000000 0x00011c00 0x00000000 0x00000010 0x00000000>;/* prefetchable memory */
 250                 };
 251
 252                 uctl@118006c000000 {
 253                         compatible = "cavium,octeon-7130-sata-uctl", "simple-bus";
 254                         reg = <0x11800 0x6c000000 0x0 0x100>;
 255                         ranges; /* Direct mapping */
 256                         #address-cells = <2>;
 257                         #size-cells = <2>;
 258                         portmap = <0x3>;
 259                         staggered-spinup;
 260                         cavium,qlm-trim = "4,sata";
 261
 262                         sata: sata@16c0000000000 {
 263                                 compatible = "cavium,octeon-7130-ahci";
 264                                 reg = <0x16c00 0x00000000 0x0 0x200>;
 265                                 #address-cells = <2>;
 266                                 #size-cells = <2>;
 267                                 interrupts = <0x6c010 4>;
 268                         };
 269                 };
 270
 271                 /* SMI1 */
 272                 smi1: mdio@1180000003880 {
 273                         compatible = "cavium,octeon-3860-mdio";
 274                         reg = <0x11800 0x00003880 0x0 0x40>;
 275                         #address-cells = <1>;
 276                         #size-cells = <0>;
 277                 };
 278
 279                 /* BGX 0 */
 280                 bgx0: ethernet-mac-nexus@11800e0000000 {
 281                         compatible = "cavium,octeon-7890-bgx";
 282                         reg = <0x11800 0xe0000000 0x0 0x1000000>;
 283                         #address-cells = <1>;
 284                         #size-cells = <0>;
 285                         status = "disabled";
 286                 };
 287
 288                 /* BGX 1 */
 289                 bgx1: ethernet-mac-nexus@11800e1000000 {
 290                         compatible = "cavium,octeon-7890-bgx";
 291                         reg = <0x11800 0xe1000000 0x0 0x1000000>;
 292                         #address-cells = <1>;
 293                         #size-cells = <0>;
 294                         status = "disabled";
 295                 };
 296
 297                 /* BGX 2*/
 298                 bgx2: ethernet-mac-nexus@11800e2000000 {
 299                         compatible = "cavium,octeon-7890-bgx";
 300                         reg = <0x11800 0xe2000000 0x0 0x1000000>;
 301                         #address-cells = <1>;
 302                         #size-cells = <0>;
 303                         status = "disabled";
 304                 };
 305         };
 306 };