arch/mips/kernel/r4k_switch.S

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
   7  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   8  * Copyright (C) 1994, 1995, 1996, by Andreas Busse
   9  * Copyright (C) 1999 Silicon Graphics, Inc.
  10  * Copyright (C) 2000 MIPS Technologies, Inc.
  11  *    written by Carsten Langgaard, carstenl@mips.com
  12  */
  13 #include <linux/config.h>
  14 #include <asm/asm.h>
  15 #include <asm/cachectl.h>
  16 #include <asm/fpregdef.h>
  17 #include <asm/mipsregs.h>
  18 #include <asm/offset.h>
  19 #include <asm/page.h>
  20 #include <asm/pgtable-bits.h>
  21 #include <asm/regdef.h>
  22 #include <asm/stackframe.h>
  23 #include <asm/thread_info.h>
  24
  25 #include <asm/asmmacro.h>
  26
  27 /*
  28  * Offset to the current process status flags, the first 32 bytes of the
  29  * stack are not used.
  30  */
  31 #define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
  32
  33 /*
  34  * FPU context is saved iff the process has used it's FPU in the current
  35  * time slice as indicated by _TIF_USEDFPU.  In any case, the CU1 bit for user
  36  * space STATUS register should be 0, so that a process *always* starts its
  37  * userland with FPU disabled after each context switch.
  38  *
  39  * FPU will be enabled as soon as the process accesses FPU again, through
  40  * do_cpu() trap.
  41  */
  42
  43 /*
  44  * task_struct *resume(task_struct *prev, task_struct *next,
  45  *                     struct thread_info *next_ti)
  46  */
  47         .align  5
  48         LEAF(resume)
  49 #ifndef CONFIG_CPU_HAS_LLSC
  50         sw      zero, ll_bit
  51 #endif
  52         mfc0    t1, CP0_STATUS
  53         LONG_S  t1, THREAD_STATUS(a0)
  54         cpu_save_nonscratch a0
  55         LONG_S  ra, THREAD_REG31(a0)
  56
  57         /*
  58          * check if we need to save FPU registers
  59          */
  60         PTR_L   t3, TASK_THREAD_INFO(a0)
  61         LONG_L  t0, TI_FLAGS(t3)
  62         li      t1, _TIF_USEDFPU
  63         and     t2, t0, t1
  64         beqz    t2, 1f
  65         nor     t1, zero, t1
  66
  67         and     t0, t0, t1
  68         LONG_S  t0, TI_FLAGS(t3)
  69
  70         /*
  71          * clear saved user stack CU1 bit
  72          */
  73         LONG_L  t0, ST_OFF(t3)
  74         li      t1, ~ST0_CU1
  75         and     t0, t0, t1
  76         LONG_S  t0, ST_OFF(t3)
  77
  78         fpu_save_double a0 t1 t0 t2             # c0_status passed in t1
  79                                                 # clobbers t0 and t2
  80 1:
  81
  82         /*
  83          * The order of restoring the registers takes care of the race
  84          * updating $28, $29 and kernelsp without disabling ints.
  85          */
  86         move    $28, a2
  87         cpu_restore_nonscratch a1
  88
  89         PTR_ADDIU       t0, $28, _THREAD_SIZE - 32
  90         set_saved_sp    t0, t1, t2
  91
  92         mfc0    t1, CP0_STATUS          /* Do we really need this? */
  93         li      a3, 0xff01
  94         and     t1, a3
  95         LONG_L  a2, THREAD_STATUS(a1)
  96         nor     a3, $0, a3
  97         and     a2, a3
  98         or      a2, t1
  99         mtc0    a2, CP0_STATUS
 100         move    v0, a0
 101         jr      ra
 102         END(resume)
 103
 104 /*
 105  * Save a thread's fp context.
 106  */
 107 LEAF(_save_fp)
 108 #ifdef CONFIG_MIPS64
 109         mfc0    t1, CP0_STATUS
 110 #endif
 111         fpu_save_double a0 t1 t0 t2             # clobbers t1
 112         jr      ra
 113         END(_save_fp)
 114
 115 /*
 116  * Restore a thread's fp context.
 117  */
 118 LEAF(_restore_fp)
 119         fpu_restore_double a0, t1               # clobbers t1
 120         jr      ra
 121         END(_restore_fp)
 122
 123 /*
 124  * Load the FPU with signalling NANS.  This bit pattern we're using has
 125  * the property that no matter whether considered as single or as double
 126  * precision represents signaling NANS.
 127  *
 128  * We initialize fcr31 to rounding to nearest, no exceptions.
 129  */
 130
 131 #define FPU_DEFAULT  0x00000000
 132
 133 LEAF(_init_fpu)
 134         mfc0    t0, CP0_STATUS
 135         li      t1, ST0_CU1
 136         or      t0, t1
 137         mtc0    t0, CP0_STATUS
 138         fpu_enable_hazard
 139
 140         li      t1, FPU_DEFAULT
 141         ctc1    t1, fcr31
 142
 143         li      t1, -1                          # SNaN
 144
 145 #ifdef CONFIG_MIPS64
 146         sll     t0, t0, 5
 147         bgez    t0, 1f                          # 16 / 32 register mode?
 148
 149         dmtc1   t1, $f1
 150         dmtc1   t1, $f3
 151         dmtc1   t1, $f5
 152         dmtc1   t1, $f7
 153         dmtc1   t1, $f9
 154         dmtc1   t1, $f11
 155         dmtc1   t1, $f13
 156         dmtc1   t1, $f15
 157         dmtc1   t1, $f17
 158         dmtc1   t1, $f19
 159         dmtc1   t1, $f21
 160         dmtc1   t1, $f23
 161         dmtc1   t1, $f25
 162         dmtc1   t1, $f27
 163         dmtc1   t1, $f29
 164         dmtc1   t1, $f31
 165 1:
 166 #endif
 167
 168 #ifdef CONFIG_CPU_MIPS32
 169         mtc1    t1, $f0
 170         mtc1    t1, $f1
 171         mtc1    t1, $f2
 172         mtc1    t1, $f3
 173         mtc1    t1, $f4
 174         mtc1    t1, $f5
 175         mtc1    t1, $f6
 176         mtc1    t1, $f7
 177         mtc1    t1, $f8
 178         mtc1    t1, $f9
 179         mtc1    t1, $f10
 180         mtc1    t1, $f11
 181         mtc1    t1, $f12
 182         mtc1    t1, $f13
 183         mtc1    t1, $f14
 184         mtc1    t1, $f15
 185         mtc1    t1, $f16
 186         mtc1    t1, $f17
 187         mtc1    t1, $f18
 188         mtc1    t1, $f19
 189         mtc1    t1, $f20
 190         mtc1    t1, $f21
 191         mtc1    t1, $f22
 192         mtc1    t1, $f23
 193         mtc1    t1, $f24
 194         mtc1    t1, $f25
 195         mtc1    t1, $f26
 196         mtc1    t1, $f27
 197         mtc1    t1, $f28
 198         mtc1    t1, $f29
 199         mtc1    t1, $f30
 200         mtc1    t1, $f31
 201 #else
 202         .set    mips3
 203         dmtc1   t1, $f0
 204         dmtc1   t1, $f2
 205         dmtc1   t1, $f4
 206         dmtc1   t1, $f6
 207         dmtc1   t1, $f8
 208         dmtc1   t1, $f10
 209         dmtc1   t1, $f12
 210         dmtc1   t1, $f14
 211         dmtc1   t1, $f16
 212         dmtc1   t1, $f18
 213         dmtc1   t1, $f20
 214         dmtc1   t1, $f22
 215         dmtc1   t1, $f24
 216         dmtc1   t1, $f26
 217         dmtc1   t1, $f28
 218         dmtc1   t1, $f30
 219 #endif
 220         jr      ra
 221         END(_init_fpu)