3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/cacheops.h>
10 #ifdef CONFIG_MIPS_L2_CACHE
13 #include <asm/mipsregs.h>
15 DECLARE_GLOBAL_DATA_PTR
;
17 static void probe_l2(void)
19 #ifdef CONFIG_MIPS_L2_CACHE
20 unsigned long conf2
, sl
;
23 if (!(read_c0_config1() & MIPS_CONF_M
))
26 conf2
= read_c0_config2();
28 if (__mips_isa_rev
>= 6) {
29 l2c
= conf2
& MIPS_CONF_M
;
31 l2c
= read_c0_config3() & MIPS_CONF_M
;
33 l2c
= read_c0_config4() & MIPS_CONF_M
;
35 l2c
= read_c0_config5() & MIPS_CONF5_L2C
;
38 if (l2c
&& config_enabled(CONFIG_MIPS_CM
)) {
39 gd
->arch
.l2_line_size
= mips_cm_l2_line_size();
41 /* We don't know how to retrieve L2 config on this system */
44 sl
= (conf2
& MIPS_CONF2_SL
) >> MIPS_CONF2_SL_SHF
;
45 gd
->arch
.l2_line_size
= sl
? (2 << sl
) : 0;
50 void mips_cache_probe(void)
52 #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
53 unsigned long conf1
, il
, dl
;
55 conf1
= read_c0_config1();
57 il
= (conf1
& MIPS_CONF1_IL
) >> MIPS_CONF1_IL_SHF
;
58 dl
= (conf1
& MIPS_CONF1_DL
) >> MIPS_CONF1_DL_SHF
;
60 gd
->arch
.l1i_line_size
= il
? (2 << il
) : 0;
61 gd
->arch
.l1d_line_size
= dl
? (2 << dl
) : 0;
66 static inline unsigned long icache_line_size(void)
68 #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
69 return gd
->arch
.l1i_line_size
;
71 return CONFIG_SYS_ICACHE_LINE_SIZE
;
75 static inline unsigned long dcache_line_size(void)
77 #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
78 return gd
->arch
.l1d_line_size
;
80 return CONFIG_SYS_DCACHE_LINE_SIZE
;
84 static inline unsigned long scache_line_size(void)
86 #ifdef CONFIG_MIPS_L2_CACHE
87 return gd
->arch
.l2_line_size
;
93 #define cache_loop(start, end, lsize, ops...) do { \
94 const void *addr = (const void *)(start & ~(lsize - 1)); \
95 const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \
96 const unsigned int cache_ops[] = { ops }; \
99 for (; addr <= aend; addr += lsize) { \
100 for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
101 mips_cache(cache_ops[i], addr); \
105 void flush_cache(ulong start_addr
, ulong size
)
107 unsigned long ilsize
= icache_line_size();
108 unsigned long dlsize
= dcache_line_size();
109 unsigned long slsize
= scache_line_size();
111 /* aend will be miscalculated when size is zero, so we return here */
115 if ((ilsize
== dlsize
) && !slsize
) {
116 /* flush I-cache & D-cache simultaneously */
117 cache_loop(start_addr
, start_addr
+ size
, ilsize
,
118 HIT_WRITEBACK_INV_D
, HIT_INVALIDATE_I
);
123 cache_loop(start_addr
, start_addr
+ size
, dlsize
, HIT_WRITEBACK_INV_D
);
127 cache_loop(start_addr
, start_addr
+ size
, slsize
,
128 HIT_WRITEBACK_INV_SD
);
131 cache_loop(start_addr
, start_addr
+ size
, ilsize
, HIT_INVALIDATE_I
);
134 void flush_dcache_range(ulong start_addr
, ulong stop
)
136 unsigned long lsize
= dcache_line_size();
137 unsigned long slsize
= scache_line_size();
139 /* aend will be miscalculated when size is zero, so we return here */
140 if (start_addr
== stop
)
143 cache_loop(start_addr
, stop
, lsize
, HIT_WRITEBACK_INV_D
);
147 cache_loop(start_addr
, stop
, slsize
, HIT_WRITEBACK_INV_SD
);
150 void invalidate_dcache_range(ulong start_addr
, ulong stop
)
152 unsigned long lsize
= dcache_line_size();
153 unsigned long slsize
= scache_line_size();
155 /* aend will be miscalculated when size is zero, so we return here */
156 if (start_addr
== stop
)
159 /* invalidate L2 cache */
161 cache_loop(start_addr
, stop
, slsize
, HIT_INVALIDATE_SD
);
163 cache_loop(start_addr
, stop
, lsize
, HIT_INVALIDATE_D
);