arch/mips/lib/cache.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/cacheops.h>
  10 #include <asm/mipsregs.h>
  11
  12 DECLARE_GLOBAL_DATA_PTR;
  13
  14 void mips_cache_probe(void)
  15 {
  16 #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
  17         unsigned long conf1, il, dl;
  18
  19         conf1 = read_c0_config1();
  20
  21         il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
  22         dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
  23
  24         gd->arch.l1i_line_size = il ? (2 << il) : 0;
  25         gd->arch.l1d_line_size = dl ? (2 << dl) : 0;
  26 #endif
  27 }
  28
  29 static inline unsigned long icache_line_size(void)
  30 {
  31 #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
  32         return gd->arch.l1i_line_size;
  33 #else
  34         return CONFIG_SYS_ICACHE_LINE_SIZE;
  35 #endif
  36 }
  37
  38 static inline unsigned long dcache_line_size(void)
  39 {
  40 #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
  41         return gd->arch.l1d_line_size;
  42 #else
  43         return CONFIG_SYS_DCACHE_LINE_SIZE;
  44 #endif
  45 }
  46
  47 #define cache_loop(start, end, lsize, ops...) do {                      \
  48         const void *addr = (const void *)(start & ~(lsize - 1));        \
  49         const void *aend = (const void *)((end - 1) & ~(lsize - 1));    \
  50         const unsigned int cache_ops[] = { ops };                       \
  51         unsigned int i;                                                 \
  52                                                                         \
  53         for (; addr <= aend; addr += lsize) {                           \
  54                 for (i = 0; i < ARRAY_SIZE(cache_ops); i++)             \
  55                         mips_cache(cache_ops[i], addr);                 \
  56         }                                                               \
  57 } while (0)
  58
  59 void flush_cache(ulong start_addr, ulong size)
  60 {
  61         unsigned long ilsize = icache_line_size();
  62         unsigned long dlsize = dcache_line_size();
  63
  64         /* aend will be miscalculated when size is zero, so we return here */
  65         if (size == 0)
  66                 return;
  67
  68         if (ilsize == dlsize) {
  69                 /* flush I-cache & D-cache simultaneously */
  70                 cache_loop(start_addr, start_addr + size, ilsize,
  71                            HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
  72                 return;
  73         }
  74
  75         /* flush D-cache */
  76         cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
  77
  78         /* flush I-cache */
  79         cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
  80 }
  81
  82 void flush_dcache_range(ulong start_addr, ulong stop)
  83 {
  84         unsigned long lsize = dcache_line_size();
  85
  86         /* aend will be miscalculated when size is zero, so we return here */
  87         if (start_addr == stop)
  88                 return;
  89
  90         cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
  91 }
  92
  93 void invalidate_dcache_range(ulong start_addr, ulong stop)
  94 {
  95         unsigned long lsize = dcache_line_size();
  96
  97         /* aend will be miscalculated when size is zero, so we return here */
  98         if (start_addr == stop)
  99                 return;
 100
 101         cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
 102 }