]>
git.ipfire.org Git - people/ms/u-boot.git/blob - arch/mips/mach-pic32/cpu.c
f15b58d849128061e15fdd8cc95de744807017a3
3 * Purna Chandra Mandal <purna.mandal@microchip.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <mach/pic32.h>
13 #include <dt-bindings/clock/microchip,clock.h>
22 #define CLK_MHZ(x) ((x) / 1000000)
24 DECLARE_GLOBAL_DATA_PTR
;
26 static ulong
rate(int id
)
33 ret
= uclass_get_device(UCLASS_CLK
, 0, &dev
);
35 printf("clk-uclass not found\n");
40 ret
= clk_request(dev
, &clk
);
44 rate
= clk_get_rate(&clk
);
51 static ulong
clk_get_cpu_rate(void)
56 /* initialize prefetch module related to cpu_clk */
57 static void prefetch_init(void)
59 struct pic32_reg_atomic
*regs
;
60 const void __iomem
*base
;
64 /* cpu frequency in MHZ */
65 rate
= clk_get_cpu_rate() / 1000000;
67 /* get flash ECC type */
68 base
= pic32_get_syscfg_base();
69 v
= (readl(base
+ CFGCON
) >> ECC_SHIFT
) & ECC_MASK
;
87 regs
= ioremap(PREFETCH_BASE
+ PRECON
, sizeof(*regs
));
88 writel(nr_waits
, ®s
->raw
);
90 /* Enable prefetch for all */
91 writel(0x30, ®s
->set
);
95 /* arch specific CPU init after DM */
96 int arch_cpu_init_dm(void)
103 /* Un-gate DDR2 modules (gated by default) */
104 static void ddr2_pmd_ungate(void)
108 regs
= pic32_get_syscfg_base();
109 writel(0, regs
+ PMD7
);
112 /* initialize the DDR2 Controller and DDR2 PHY */
113 phys_size_t
initdram(void)
118 return ddr2_calculate_size();
121 int misc_init_r(void)
127 #ifdef CONFIG_DISPLAY_BOARDINFO
128 const char *get_core_name(void)
133 proc_id
= read_c0_prid();
145 #ifdef CONFIG_CMD_CLK
147 int soc_clk_dump(void)
151 printf("PLL Speed: %lu MHz\n",
152 CLK_MHZ(rate(PLLCLK
)));
154 printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK
)));
156 printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL
)));
158 for (i
= PB1CLK
; i
<= PB7CLK
; i
++)
159 printf("PB%d Clock Speed: %lu MHz\n", i
- PB1CLK
+ 1,
162 for (i
= REF1CLK
; i
<= REF5CLK
; i
++)
163 printf("REFO%d Clock Speed: %lu MHz\n", i
- REF1CLK
+ 1,