arch/mips/ralink/rt3883.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify it
   3  * under the terms of the GNU General Public License version 2 as published
   4  * by the Free Software Foundation.
   5  *
   6  * Parts of this file are based on Ralink's 2.6.21 BSP
   7  *
   8  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   9  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  10  * Copyright (C) 2013 John Crispin <john@phrozen.org>
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15
  16 #include <asm/mipsregs.h>
  17 #include <asm/mach-ralink/ralink_regs.h>
  18 #include <asm/mach-ralink/rt3883.h>
  19 #include <asm/mach-ralink/pinmux.h>
  20
  21 #include "common.h"
  22
  23 static struct rt2880_pmx_func i2c_func[] =  { FUNC("i2c", 0, 1, 2) };
  24 static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
  25 static struct rt2880_pmx_func uartf_func[] = {
  26         FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
  27         FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
  28         FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
  29         FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
  30         FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
  31         FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
  32         FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
  33 };
  34 static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
  35 static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
  36 static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
  37 static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
  38 static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna g", 0, 35, 3) };
  39 static struct rt2880_pmx_func pci_func[] = {
  40         FUNC("pci-dev", 0, 40, 32),
  41         FUNC("pci-host2", 1, 40, 32),
  42         FUNC("pci-host1", 2, 40, 32),
  43         FUNC("pci-fnc", 3, 40, 32)
  44 };
  45 static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
  46 static struct rt2880_pmx_func ge2_func[] = { FUNC("ge2", 0, 84, 12) };
  47
  48 static struct rt2880_pmx_group rt3883_pinmux_data[] = {
  49         GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
  50         GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
  51         GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
  52                 RT3883_GPIO_MODE_UART0_SHIFT),
  53         GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
  54         GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
  55         GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
  56         GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
  57         GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
  58         GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
  59                 RT3883_GPIO_MODE_PCI_SHIFT),
  60         GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
  61         GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
  62         { 0 }
  63 };
  64
  65 void __init ralink_clk_init(void)
  66 {
  67         unsigned long cpu_rate, sys_rate;
  68         u32 syscfg0;
  69         u32 clksel;
  70         u32 ddr2;
  71
  72         syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
  73         clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
  74                 RT3883_SYSCFG0_CPUCLK_MASK);
  75         ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
  76
  77         switch (clksel) {
  78         case RT3883_SYSCFG0_CPUCLK_250:
  79                 cpu_rate = 250000000;
  80                 sys_rate = (ddr2) ? 125000000 : 83000000;
  81                 break;
  82         case RT3883_SYSCFG0_CPUCLK_384:
  83                 cpu_rate = 384000000;
  84                 sys_rate = (ddr2) ? 128000000 : 96000000;
  85                 break;
  86         case RT3883_SYSCFG0_CPUCLK_480:
  87                 cpu_rate = 480000000;
  88                 sys_rate = (ddr2) ? 160000000 : 120000000;
  89                 break;
  90         case RT3883_SYSCFG0_CPUCLK_500:
  91                 cpu_rate = 500000000;
  92                 sys_rate = (ddr2) ? 166000000 : 125000000;
  93                 break;
  94         }
  95
  96         ralink_clk_add("cpu", cpu_rate);
  97         ralink_clk_add("10000100.timer", sys_rate);
  98         ralink_clk_add("10000120.watchdog", sys_rate);
  99         ralink_clk_add("10000500.uart", 40000000);
 100         ralink_clk_add("10000900.i2c", 40000000);
 101         ralink_clk_add("10000a00.i2s", 40000000);
 102         ralink_clk_add("10000b00.spi", sys_rate);
 103         ralink_clk_add("10000b40.spi", sys_rate);
 104         ralink_clk_add("10000c00.uartlite", 40000000);
 105         ralink_clk_add("10100000.ethernet", sys_rate);
 106         ralink_clk_add("10180000.wmac", 40000000);
 107 }
 108
 109 void __init ralink_of_remap(void)
 110 {
 111         rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
 112         rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
 113
 114         if (!rt_sysc_membase || !rt_memc_membase)
 115                 panic("Failed to remap core resources");
 116 }
 117
 118 void prom_soc_init(struct ralink_soc_info *soc_info)
 119 {
 120         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
 121         const char *name;
 122         u32 n0;
 123         u32 n1;
 124         u32 id;
 125
 126         n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
 127         n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
 128         id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
 129
 130         if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
 131                 soc_info->compatible = "ralink,rt3883-soc";
 132                 name = "RT3883";
 133         } else {
 134                 panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
 135         }
 136
 137         snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 138                 "Ralink %s ver:%u eco:%u",
 139                 name,
 140                 (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
 141                 (id & RT3883_REVID_ECO_ID_MASK));
 142
 143         soc_info->mem_base = RT3883_SDRAM_BASE;
 144         soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
 145         soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
 146
 147         rt2880_pinmux_data = rt3883_pinmux_data;
 148
 149         ralink_soc = RT3883_SOC;
 150 }