arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011 Andes Technology Corporation
   4  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   5  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   6  */
   7
   8 .pic
   9
  10 .text
  11
  12 #include <common.h>
  13 #include <config.h>
  14
  15 #include <asm/macro.h>
  16 #include <generated/asm-offsets.h>
  17
  18 /*
  19  * parameters for the SDRAM controller
  20  */
  21 #define SDMC_TP1_A              (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
  22 #define SDMC_TP2_A              (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
  23 #define SDMC_CR1_A              (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
  24 #define SDMC_CR2_A              (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
  25 #define SDMC_B0_BSR_A           (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
  26 #define SDMC_B1_BSR_A           (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
  27
  28 #define SDMC_TP1_D              CONFIG_SYS_FTSDMC021_TP1
  29 #define SDMC_TP2_D              CONFIG_SYS_FTSDMC021_TP2
  30 #define SDMC_CR1_D              CONFIG_SYS_FTSDMC021_CR1
  31 #define SDMC_CR2_D              CONFIG_SYS_FTSDMC021_CR2
  32
  33 #define SDMC_B0_BSR_D           CONFIG_SYS_FTSDMC021_BANK0_BSR
  34 #define SDMC_B1_BSR_D           CONFIG_SYS_FTSDMC021_BANK1_BSR
  35
  36
  37 /*
  38  * for Orca and Emerald
  39  */
  40 #define BOARD_ID_REG            0x104
  41 #define BOARD_ID_FAMILY_MASK    0xfff000
  42 #define BOARD_ID_FAMILY_V5      0x556000
  43 #define BOARD_ID_FAMILY_K7      0x74b000
  44
  45 /*
  46  * parameters for the static memory controller
  47  */
  48 #define SMC_BANK0_CR_A          (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
  49 #define SMC_BANK0_TPR_A         (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
  50
  51 #define SMC_BANK0_CR_D          FTSMC020_BANK0_LOWLV_CONFIG
  52 #define SMC_BANK0_TPR_D         FTSMC020_BANK0_LOWLV_TIMING
  53
  54 /*
  55  * for Orca and Emerald
  56  */
  57 #define AHBC_BSR4_A     (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
  58 #define AHBC_BSR6_D             CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
  59
  60 /*
  61  * parameters for the pmu controoler
  62  */
  63 #define PMU_PDLLCR0_A           (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
  64
  65 /*
  66  * numeric 7 segment display
  67  */
  68 .macro  led, num
  69         write32 CONFIG_DEBUG_LED, \num
  70 .endm
  71
  72 /*
  73  * Waiting for SDRAM to set up
  74  */
  75 .macro  wait_sdram
  76         li      $r0, CONFIG_FTSDMC021_BASE
  77 1:
  78         lwi     $r1, [$r0+FTSDMC021_CR2]
  79         bnez    $r1, 1b
  80 .endm
  81
  82 .globl  mem_init
  83 mem_init:
  84         move    $r11, $lp
  85         li      $r0, SMC_BANK0_CR_A
  86         lwi $r1, [$r0+#0x00]
  87         ori $r1, $r1, 0x8f0
  88         xori $r1, $r1, 0x8f0
  89         /* 16-bit mode */
  90         ori       $r1, $r1, 0x60
  91         li        $r2, 0x00153153
  92         swi     $r1, [$r0+#0x00]
  93         swi       $r2, [$r0+#0x04]
  94         move      $lp, $r11
  95         ret
  96
  97 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  98 .globl  lowlevel_init
  99 lowlevel_init:
 100         move    $r10, $lp
 101         jal     remap
 102
 103 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
 104         jal     enable_fpu
 105 #endif
 106         ret     $r10
 107
 108 remap:
 109         move    $r11, $lp
 110 relo_base:
 111         mfusr   $r0, $pc
 112
 113 #ifdef CONFIG_MEM_REMAP
 114         li      $r4, 0x00000000
 115         li      $r5, 0x80000000
 116         la  $r6, _end@GOTOFF
 117 1:
 118         lmw.bim $r12, [$r5], $r19
 119         smw.bim $r12, [$r4], $r19
 120         blt     $r5, $r6, 1b
 121 #endif /* #ifdef CONFIG_MEM_REMAP */
 122         move $lp, $r11
 123 2:
 124         ret
 125
 126         /*
 127          * enable_fpu:
 128          *  Some of Andes CPU version support FPU coprocessor, if so,
 129          *  and toolchain support FPU instruction set, we should enable it.
 130          */
 131 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
 132 enable_fpu:
 133         mfsr    $r0, $CPU_VER     /* enable FPU if it exists */
 134         srli    $r0, $r0, 3
 135         andi    $r0, $r0, 1
 136         beqz    $r0, 1f           /* skip if no COP */
 137         mfsr    $r0, $FUCOP_EXIST
 138         srli    $r0, $r0, 31
 139         beqz    $r0, 1f           /* skip if no FPU */
 140         mfsr    $r0, $FUCOP_CTL
 141         ori     $r0, $r0, 1
 142         mtsr    $r0, $FUCOP_CTL
 143 1:
 144         ret
 145 #endif
 146
 147 #endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */