arch/nds32/cpu/n1213/ag102/asm-offsets.c

   1 /*
   2  * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
   3  *
   4  * Generate definitions needed by assembly language modules.
   5  * This code generates raw asm output which is post-processed to extract
   6  * and format the required data.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <common.h>
  13
  14 #include <linux/kbuild.h>
  15
  16 int main(void)
  17 {
  18 #ifdef CONFIG_FTSMC020
  19         OFFSET(FTSMC020_BANK0_CR,       ftsmc020, bank[0].cr);
  20         OFFSET(FTSMC020_BANK0_TPR,      ftsmc020, bank[0].tpr);
  21 #endif
  22         BLANK();
  23 #ifdef CONFIG_FTAHBC020S
  24         OFFSET(FTAHBC020S_SLAVE_BSR_6,  ftahbc02s, s_bsr[6]);
  25         OFFSET(FTAHBC020S_CR,           ftahbc02s, cr);
  26 #endif
  27         BLANK();
  28 #ifdef CONFIG_ANDES_PCU
  29         OFFSET(ANDES_PCU_PCS4,          andes_pcu, pcs4.parm);  /* 0x104 */
  30 #endif
  31         BLANK();
  32 #ifdef CONFIG_DWCDDR21MCTL
  33         OFFSET(DWCDDR21MCTL_CCR,        dwcddr21mctl, ccr);     /* 0x04 */
  34         OFFSET(DWCDDR21MCTL_DCR,        dwcddr21mctl, dcr);     /* 0x04 */
  35         OFFSET(DWCDDR21MCTL_IOCR,       dwcddr21mctl, iocr);    /* 0x08 */
  36         OFFSET(DWCDDR21MCTL_CSR,        dwcddr21mctl, csr);     /* 0x0c */
  37         OFFSET(DWCDDR21MCTL_DRR,        dwcddr21mctl, drr);     /* 0x10 */
  38         OFFSET(DWCDDR21MCTL_DLLCR0,     dwcddr21mctl, dllcr[0]); /* 0x24 */
  39         OFFSET(DWCDDR21MCTL_DLLCR1,     dwcddr21mctl, dllcr[1]); /* 0x28 */
  40         OFFSET(DWCDDR21MCTL_DLLCR2,     dwcddr21mctl, dllcr[2]); /* 0x2c */
  41         OFFSET(DWCDDR21MCTL_DLLCR3,     dwcddr21mctl, dllcr[3]); /* 0x30 */
  42         OFFSET(DWCDDR21MCTL_DLLCR4,     dwcddr21mctl, dllcr[4]); /* 0x34 */
  43         OFFSET(DWCDDR21MCTL_DLLCR5,     dwcddr21mctl, dllcr[5]); /* 0x38 */
  44         OFFSET(DWCDDR21MCTL_DLLCR6,     dwcddr21mctl, dllcr[6]); /* 0x3c */
  45         OFFSET(DWCDDR21MCTL_DLLCR7,     dwcddr21mctl, dllcr[7]); /* 0x40 */
  46         OFFSET(DWCDDR21MCTL_DLLCR8,     dwcddr21mctl, dllcr[8]); /* 0x44 */
  47         OFFSET(DWCDDR21MCTL_DLLCR9,     dwcddr21mctl, dllcr[9]); /* 0x48 */
  48         OFFSET(DWCDDR21MCTL_RSLR0,      dwcddr21mctl, rslr[0]); /* 0x4c */
  49         OFFSET(DWCDDR21MCTL_RDGR0,      dwcddr21mctl, rdgr[0]); /* 0x5c */
  50         OFFSET(DWCDDR21MCTL_DTAR,       dwcddr21mctl, dtar);    /* 0xa4 */
  51         OFFSET(DWCDDR21MCTL_MR,         dwcddr21mctl, mr);      /* 0x1f0 */
  52 #endif
  53         return 0;
  54 }