arch/parisc/include/asm/assembly.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
   4  * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org>
   5  * Copyright (C) 1999 SuSE GmbH
   6  * Copyright (C) 2021 Helge Deller <deller@gmx.de>
   7  */
   8
   9 #ifndef _PARISC_ASSEMBLY_H
  10 #define _PARISC_ASSEMBLY_H
  11
  12 #ifdef CONFIG_64BIT
  13 #define RP_OFFSET       16
  14 #define FRAME_SIZE      128
  15 #define CALLEE_REG_FRAME_SIZE   144
  16 #define REG_SZ          8
  17 #define ASM_ULONG_INSN  .dword
  18 #else   /* CONFIG_64BIT */
  19 #define RP_OFFSET       20
  20 #define FRAME_SIZE      64
  21 #define CALLEE_REG_FRAME_SIZE   128
  22 #define REG_SZ          4
  23 #define ASM_ULONG_INSN  .word
  24 #endif
  25
  26 /* Frame alignment for 32- and 64-bit */
  27 #define FRAME_ALIGN     64
  28
  29 #define CALLEE_FLOAT_FRAME_SIZE 80
  30 #define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
  31
  32 #ifdef CONFIG_PA20
  33 #define LDCW            ldcw,co
  34 #define BL              b,l
  35 # ifdef CONFIG_64BIT
  36 #  define PA_ASM_LEVEL  2.0w
  37 # else
  38 #  define PA_ASM_LEVEL  2.0
  39 # endif
  40 #else
  41 #define LDCW            ldcw
  42 #define BL              bl
  43 #define PA_ASM_LEVEL    1.1
  44 #endif
  45
  46 /* Privilege level field in the rightmost two bits of the IA queues */
  47 #define PRIV_USER       3
  48 #define PRIV_KERNEL     0
  49
  50 /* Space register used inside kernel */
  51 #define SR_KERNEL       0
  52 #define SR_TEMP1        1
  53 #define SR_TEMP2        2
  54 #define SR_USER         3
  55
  56 #ifdef __ASSEMBLY__
  57
  58 #ifdef CONFIG_64BIT
  59 #define LDREG   ldd
  60 #define STREG   std
  61 #define LDREGX  ldd,s
  62 #define LDREGM  ldd,mb
  63 #define STREGM  std,ma
  64 #define SHRREG  shrd
  65 #define SHLREG  shld
  66 #define ANDCM   andcm,*
  67 #define COND(x) * ## x
  68 #else   /* CONFIG_64BIT */
  69 #define LDREG   ldw
  70 #define STREG   stw
  71 #define LDREGX  ldwx,s
  72 #define LDREGM  ldwm
  73 #define STREGM  stwm
  74 #define SHRREG  shr
  75 #define SHLREG  shlw
  76 #define ANDCM   andcm
  77 #define COND(x) x
  78 #endif
  79
  80 #ifdef CONFIG_64BIT
  81 /* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so
  82  * work around that for now... */
  83         .level 2.0w
  84 #endif
  85
  86 #include <asm/asm-offsets.h>
  87 #include <asm/page.h>
  88 #include <asm/types.h>
  89
  90 #include <asm/asmregs.h>
  91 #include <asm/psw.h>
  92
  93         /*
  94          * We provide two versions of each macro to convert from physical
  95          * to virtual and vice versa. The "_r1" versions take one argument
  96          * register, but trashes r1 to do the conversion. The other
  97          * version takes two arguments: a src and destination register.
  98          * However, the source and destination registers can not be
  99          * the same register.
 100          */
 101
 102         .macro  tophys  grvirt, grphys
 103         ldil    L%(__PAGE_OFFSET), \grphys
 104         sub     \grvirt, \grphys, \grphys
 105         .endm
 106
 107         .macro  tovirt  grphys, grvirt
 108         ldil    L%(__PAGE_OFFSET), \grvirt
 109         add     \grphys, \grvirt, \grvirt
 110         .endm
 111
 112         .macro  tophys_r1  gr
 113         ldil    L%(__PAGE_OFFSET), %r1
 114         sub     \gr, %r1, \gr
 115         .endm
 116
 117         .macro  tovirt_r1  gr
 118         ldil    L%(__PAGE_OFFSET), %r1
 119         add     \gr, %r1, \gr
 120         .endm
 121
 122         .macro delay value
 123         ldil    L%\value, 1
 124         ldo     R%\value(1), 1
 125         addib,UV,n -1,1,.
 126         addib,NUV,n -1,1,.+8
 127         nop
 128         .endm
 129
 130         .macro  debug value
 131         .endm
 132
 133         .macro shlw r, sa, t
 134         zdep    \r, 31-(\sa), 32-(\sa), \t
 135         .endm
 136
 137         /* And the PA 2.0W shift left */
 138         .macro shld r, sa, t
 139         depd,z  \r, 63-(\sa), 64-(\sa), \t
 140         .endm
 141
 142         /* Shift Right for 32-bit. Clobbers upper 32-bit on PA2.0. */
 143         .macro shr r, sa, t
 144         extru \r, 31-(\sa), 32-(\sa), \t
 145         .endm
 146
 147         /* pa20w version of shift right */
 148         .macro shrd r, sa, t
 149         extrd,u \r, 63-(\sa), 64-(\sa), \t
 150         .endm
 151
 152         /* Extract unsigned for 32- and 64-bit
 153          * The extru instruction leaves the most significant 32 bits of the
 154          * target register in an undefined state on PA 2.0 systems. */
 155         .macro extru_safe r, p, len, t
 156 #ifdef CONFIG_64BIT
 157         extrd,u \r, 32+(\p), \len, \t
 158 #else
 159         extru   \r, \p, \len, \t
 160 #endif
 161         .endm
 162
 163         /* The depi instruction leaves the most significant 32 bits of the
 164          * target register in an undefined state on PA 2.0 systems. */
 165         .macro depi_safe i, p, len, t
 166 #ifdef CONFIG_64BIT
 167         depdi   \i, 32+(\p), \len, \t
 168 #else
 169         depi    \i, \p, \len, \t
 170 #endif
 171         .endm
 172
 173         /* The depw instruction leaves the most significant 32 bits of the
 174          * target register in an undefined state on PA 2.0 systems. */
 175         .macro dep_safe i, p, len, t
 176 #ifdef CONFIG_64BIT
 177         depd    \i, 32+(\p), \len, \t
 178 #else
 179         depw    \i, \p, \len, \t
 180 #endif
 181         .endm
 182
 183         /* load 32-bit 'value' into 'reg' compensating for the ldil
 184          * sign-extension when running in wide mode.
 185          * WARNING!! neither 'value' nor 'reg' can be expressions
 186          * containing '.'!!!! */
 187         .macro  load32 value, reg
 188         ldil    L%\value, \reg
 189         ldo     R%\value(\reg), \reg
 190         .endm
 191
 192         .macro loadgp
 193 #ifdef CONFIG_64BIT
 194         ldil            L%__gp, %r27
 195         ldo             R%__gp(%r27), %r27
 196 #else
 197         ldil            L%$global$, %r27
 198         ldo             R%$global$(%r27), %r27
 199 #endif
 200         .endm
 201
 202 #define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where
 203 #define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r
 204 #define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
 205 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
 206
 207         .macro  save_general    regs
 208         STREG %r1, PT_GR1 (\regs)
 209         STREG %r2, PT_GR2 (\regs)
 210         STREG %r3, PT_GR3 (\regs)
 211         STREG %r4, PT_GR4 (\regs)
 212         STREG %r5, PT_GR5 (\regs)
 213         STREG %r6, PT_GR6 (\regs)
 214         STREG %r7, PT_GR7 (\regs)
 215         STREG %r8, PT_GR8 (\regs)
 216         STREG %r9, PT_GR9 (\regs)
 217         STREG %r10, PT_GR10(\regs)
 218         STREG %r11, PT_GR11(\regs)
 219         STREG %r12, PT_GR12(\regs)
 220         STREG %r13, PT_GR13(\regs)
 221         STREG %r14, PT_GR14(\regs)
 222         STREG %r15, PT_GR15(\regs)
 223         STREG %r16, PT_GR16(\regs)
 224         STREG %r17, PT_GR17(\regs)
 225         STREG %r18, PT_GR18(\regs)
 226         STREG %r19, PT_GR19(\regs)
 227         STREG %r20, PT_GR20(\regs)
 228         STREG %r21, PT_GR21(\regs)
 229         STREG %r22, PT_GR22(\regs)
 230         STREG %r23, PT_GR23(\regs)
 231         STREG %r24, PT_GR24(\regs)
 232         STREG %r25, PT_GR25(\regs)
 233         /* r26 is saved in get_stack and used to preserve a value across virt_map */
 234         STREG %r27, PT_GR27(\regs)
 235         STREG %r28, PT_GR28(\regs)
 236         /* r29 is saved in get_stack and used to point to saved registers */
 237         /* r30 stack pointer saved in get_stack */
 238         STREG %r31, PT_GR31(\regs)
 239         .endm
 240
 241         .macro  rest_general    regs
 242         /* r1 used as a temp in rest_stack and is restored there */
 243         LDREG PT_GR2 (\regs), %r2
 244         LDREG PT_GR3 (\regs), %r3
 245         LDREG PT_GR4 (\regs), %r4
 246         LDREG PT_GR5 (\regs), %r5
 247         LDREG PT_GR6 (\regs), %r6
 248         LDREG PT_GR7 (\regs), %r7
 249         LDREG PT_GR8 (\regs), %r8
 250         LDREG PT_GR9 (\regs), %r9
 251         LDREG PT_GR10(\regs), %r10
 252         LDREG PT_GR11(\regs), %r11
 253         LDREG PT_GR12(\regs), %r12
 254         LDREG PT_GR13(\regs), %r13
 255         LDREG PT_GR14(\regs), %r14
 256         LDREG PT_GR15(\regs), %r15
 257         LDREG PT_GR16(\regs), %r16
 258         LDREG PT_GR17(\regs), %r17
 259         LDREG PT_GR18(\regs), %r18
 260         LDREG PT_GR19(\regs), %r19
 261         LDREG PT_GR20(\regs), %r20
 262         LDREG PT_GR21(\regs), %r21
 263         LDREG PT_GR22(\regs), %r22
 264         LDREG PT_GR23(\regs), %r23
 265         LDREG PT_GR24(\regs), %r24
 266         LDREG PT_GR25(\regs), %r25
 267         LDREG PT_GR26(\regs), %r26
 268         LDREG PT_GR27(\regs), %r27
 269         LDREG PT_GR28(\regs), %r28
 270         /* r29 points to register save area, and is restored in rest_stack */
 271         /* r30 stack pointer restored in rest_stack */
 272         LDREG PT_GR31(\regs), %r31
 273         .endm
 274
 275         .macro  save_fp         regs
 276         fstd,ma  %fr0, 8(\regs)
 277         fstd,ma  %fr1, 8(\regs)
 278         fstd,ma  %fr2, 8(\regs)
 279         fstd,ma  %fr3, 8(\regs)
 280         fstd,ma  %fr4, 8(\regs)
 281         fstd,ma  %fr5, 8(\regs)
 282         fstd,ma  %fr6, 8(\regs)
 283         fstd,ma  %fr7, 8(\regs)
 284         fstd,ma  %fr8, 8(\regs)
 285         fstd,ma  %fr9, 8(\regs)
 286         fstd,ma %fr10, 8(\regs)
 287         fstd,ma %fr11, 8(\regs)
 288         fstd,ma %fr12, 8(\regs)
 289         fstd,ma %fr13, 8(\regs)
 290         fstd,ma %fr14, 8(\regs)
 291         fstd,ma %fr15, 8(\regs)
 292         fstd,ma %fr16, 8(\regs)
 293         fstd,ma %fr17, 8(\regs)
 294         fstd,ma %fr18, 8(\regs)
 295         fstd,ma %fr19, 8(\regs)
 296         fstd,ma %fr20, 8(\regs)
 297         fstd,ma %fr21, 8(\regs)
 298         fstd,ma %fr22, 8(\regs)
 299         fstd,ma %fr23, 8(\regs)
 300         fstd,ma %fr24, 8(\regs)
 301         fstd,ma %fr25, 8(\regs)
 302         fstd,ma %fr26, 8(\regs)
 303         fstd,ma %fr27, 8(\regs)
 304         fstd,ma %fr28, 8(\regs)
 305         fstd,ma %fr29, 8(\regs)
 306         fstd,ma %fr30, 8(\regs)
 307         fstd    %fr31, 0(\regs)
 308         .endm
 309
 310         .macro  rest_fp         regs
 311         fldd    0(\regs),        %fr31
 312         fldd,mb -8(\regs),       %fr30
 313         fldd,mb -8(\regs),       %fr29
 314         fldd,mb -8(\regs),       %fr28
 315         fldd,mb -8(\regs),       %fr27
 316         fldd,mb -8(\regs),       %fr26
 317         fldd,mb -8(\regs),       %fr25
 318         fldd,mb -8(\regs),       %fr24
 319         fldd,mb -8(\regs),       %fr23
 320         fldd,mb -8(\regs),       %fr22
 321         fldd,mb -8(\regs),       %fr21
 322         fldd,mb -8(\regs),       %fr20
 323         fldd,mb -8(\regs),       %fr19
 324         fldd,mb -8(\regs),       %fr18
 325         fldd,mb -8(\regs),       %fr17
 326         fldd,mb -8(\regs),       %fr16
 327         fldd,mb -8(\regs),       %fr15
 328         fldd,mb -8(\regs),       %fr14
 329         fldd,mb -8(\regs),       %fr13
 330         fldd,mb -8(\regs),       %fr12
 331         fldd,mb -8(\regs),       %fr11
 332         fldd,mb -8(\regs),       %fr10
 333         fldd,mb -8(\regs),       %fr9
 334         fldd,mb -8(\regs),       %fr8
 335         fldd,mb -8(\regs),       %fr7
 336         fldd,mb -8(\regs),       %fr6
 337         fldd,mb -8(\regs),       %fr5
 338         fldd,mb -8(\regs),       %fr4
 339         fldd,mb -8(\regs),       %fr3
 340         fldd,mb -8(\regs),       %fr2
 341         fldd,mb -8(\regs),       %fr1
 342         fldd,mb -8(\regs),       %fr0
 343         .endm
 344
 345         .macro  callee_save_float
 346         fstd,ma  %fr12, 8(%r30)
 347         fstd,ma  %fr13, 8(%r30)
 348         fstd,ma  %fr14, 8(%r30)
 349         fstd,ma  %fr15, 8(%r30)
 350         fstd,ma  %fr16, 8(%r30)
 351         fstd,ma  %fr17, 8(%r30)
 352         fstd,ma  %fr18, 8(%r30)
 353         fstd,ma  %fr19, 8(%r30)
 354         fstd,ma  %fr20, 8(%r30)
 355         fstd,ma  %fr21, 8(%r30)
 356         .endm
 357
 358         .macro  callee_rest_float
 359         fldd,mb -8(%r30),   %fr21
 360         fldd,mb -8(%r30),   %fr20
 361         fldd,mb -8(%r30),   %fr19
 362         fldd,mb -8(%r30),   %fr18
 363         fldd,mb -8(%r30),   %fr17
 364         fldd,mb -8(%r30),   %fr16
 365         fldd,mb -8(%r30),   %fr15
 366         fldd,mb -8(%r30),   %fr14
 367         fldd,mb -8(%r30),   %fr13
 368         fldd,mb -8(%r30),   %fr12
 369         .endm
 370
 371 #ifdef CONFIG_64BIT
 372         .macro  callee_save
 373         std,ma    %r3,   CALLEE_REG_FRAME_SIZE(%r30)
 374         mfctl     %cr27, %r3
 375         std       %r4,  -136(%r30)
 376         std       %r5,  -128(%r30)
 377         std       %r6,  -120(%r30)
 378         std       %r7,  -112(%r30)
 379         std       %r8,  -104(%r30)
 380         std       %r9,   -96(%r30)
 381         std      %r10,   -88(%r30)
 382         std      %r11,   -80(%r30)
 383         std      %r12,   -72(%r30)
 384         std      %r13,   -64(%r30)
 385         std      %r14,   -56(%r30)
 386         std      %r15,   -48(%r30)
 387         std      %r16,   -40(%r30)
 388         std      %r17,   -32(%r30)
 389         std      %r18,   -24(%r30)
 390         std       %r3,   -16(%r30)
 391         .endm
 392
 393         .macro  callee_rest
 394         ldd      -16(%r30),    %r3
 395         ldd      -24(%r30),   %r18
 396         ldd      -32(%r30),   %r17
 397         ldd      -40(%r30),   %r16
 398         ldd      -48(%r30),   %r15
 399         ldd      -56(%r30),   %r14
 400         ldd      -64(%r30),   %r13
 401         ldd      -72(%r30),   %r12
 402         ldd      -80(%r30),   %r11
 403         ldd      -88(%r30),   %r10
 404         ldd      -96(%r30),    %r9
 405         ldd     -104(%r30),    %r8
 406         ldd     -112(%r30),    %r7
 407         ldd     -120(%r30),    %r6
 408         ldd     -128(%r30),    %r5
 409         ldd     -136(%r30),    %r4
 410         mtctl   %r3, %cr27
 411         ldd,mb  -CALLEE_REG_FRAME_SIZE(%r30),    %r3
 412         .endm
 413
 414 #else /* ! CONFIG_64BIT */
 415
 416         .macro  callee_save
 417         stw,ma   %r3,   CALLEE_REG_FRAME_SIZE(%r30)
 418         mfctl    %cr27, %r3
 419         stw      %r4,   -124(%r30)
 420         stw      %r5,   -120(%r30)
 421         stw      %r6,   -116(%r30)
 422         stw      %r7,   -112(%r30)
 423         stw      %r8,   -108(%r30)
 424         stw      %r9,   -104(%r30)
 425         stw      %r10,  -100(%r30)
 426         stw      %r11,   -96(%r30)
 427         stw      %r12,   -92(%r30)
 428         stw      %r13,   -88(%r30)
 429         stw      %r14,   -84(%r30)
 430         stw      %r15,   -80(%r30)
 431         stw      %r16,   -76(%r30)
 432         stw      %r17,   -72(%r30)
 433         stw      %r18,   -68(%r30)
 434         stw       %r3,   -64(%r30)
 435         .endm
 436
 437         .macro  callee_rest
 438         ldw      -64(%r30),    %r3
 439         ldw      -68(%r30),   %r18
 440         ldw      -72(%r30),   %r17
 441         ldw      -76(%r30),   %r16
 442         ldw      -80(%r30),   %r15
 443         ldw      -84(%r30),   %r14
 444         ldw      -88(%r30),   %r13
 445         ldw      -92(%r30),   %r12
 446         ldw      -96(%r30),   %r11
 447         ldw     -100(%r30),   %r10
 448         ldw     -104(%r30),   %r9
 449         ldw     -108(%r30),   %r8
 450         ldw     -112(%r30),   %r7
 451         ldw     -116(%r30),   %r6
 452         ldw     -120(%r30),   %r5
 453         ldw     -124(%r30),   %r4
 454         mtctl   %r3, %cr27
 455         ldw,mb  -CALLEE_REG_FRAME_SIZE(%r30),   %r3
 456         .endm
 457 #endif /* ! CONFIG_64BIT */
 458
 459         .macro  save_specials   regs
 460
 461         SAVE_SP  (%sr0, PT_SR0 (\regs))
 462         SAVE_SP  (%sr1, PT_SR1 (\regs))
 463         SAVE_SP  (%sr2, PT_SR2 (\regs))
 464         SAVE_SP  (%sr3, PT_SR3 (\regs))
 465         SAVE_SP  (%sr4, PT_SR4 (\regs))
 466         SAVE_SP  (%sr5, PT_SR5 (\regs))
 467         SAVE_SP  (%sr6, PT_SR6 (\regs))
 468
 469         SAVE_CR  (%cr17, PT_IASQ0(\regs))
 470         mtctl    %r0,   %cr17
 471         SAVE_CR  (%cr17, PT_IASQ1(\regs))
 472
 473         SAVE_CR  (%cr18, PT_IAOQ0(\regs))
 474         mtctl    %r0,   %cr18
 475         SAVE_CR  (%cr18, PT_IAOQ1(\regs))
 476
 477 #ifdef CONFIG_64BIT
 478         /* cr11 (sar) is a funny one.  5 bits on PA1.1 and 6 bit on PA2.0
 479          * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
 480          * reads 5 bits.  Use mfctl,w to read all six bits.  Otherwise
 481          * we lose the 6th bit on a save/restore over interrupt.
 482          */
 483         mfctl,w  %cr11, %r1
 484         STREG    %r1, PT_SAR (\regs)
 485 #else
 486         SAVE_CR  (%cr11, PT_SAR  (\regs))
 487 #endif
 488         SAVE_CR  (%cr19, PT_IIR  (\regs))
 489
 490         /*
 491          * Code immediately following this macro (in intr_save) relies
 492          * on r8 containing ipsw.
 493          */
 494         mfctl    %cr22, %r8
 495         STREG    %r8,   PT_PSW(\regs)
 496         .endm
 497
 498         .macro  rest_specials   regs
 499
 500         REST_SP  (%sr0, PT_SR0 (\regs))
 501         REST_SP  (%sr1, PT_SR1 (\regs))
 502         REST_SP  (%sr2, PT_SR2 (\regs))
 503         REST_SP  (%sr3, PT_SR3 (\regs))
 504         REST_SP  (%sr4, PT_SR4 (\regs))
 505         REST_SP  (%sr5, PT_SR5 (\regs))
 506         REST_SP  (%sr6, PT_SR6 (\regs))
 507         REST_SP  (%sr7, PT_SR7 (\regs))
 508
 509         REST_CR (%cr17, PT_IASQ0(\regs))
 510         REST_CR (%cr17, PT_IASQ1(\regs))
 511
 512         REST_CR (%cr18, PT_IAOQ0(\regs))
 513         REST_CR (%cr18, PT_IAOQ1(\regs))
 514
 515         REST_CR (%cr11, PT_SAR  (\regs))
 516
 517         REST_CR (%cr22, PT_PSW  (\regs))
 518         .endm
 519
 520
 521         /* First step to create a "relied upon translation"
 522          * See PA 2.0 Arch. page F-4 and F-5.
 523          *
 524          * The ssm was originally necessary due to a "PCxT bug".
 525          * But someone decided it needed to be added to the architecture
 526          * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
 527          * It's been carried forward into PA 2.0 Arch as well. :^(
 528          *
 529          * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
 530          * rsm/ssm prevents the ifetch unit from speculatively fetching
 531          * instructions past this line in the code stream.
 532          * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
 533          */
 534         .macro  pcxt_ssm_bug
 535         rsm     PSW_SM_I,%r0
 536         nop     /* 1 */
 537         nop     /* 2 */
 538         nop     /* 3 */
 539         nop     /* 4 */
 540         nop     /* 5 */
 541         nop     /* 6 */
 542         nop     /* 7 */
 543         .endm
 544
 545         /* Switch to virtual mapping, trashing only %r1 */
 546         .macro  virt_map
 547         /* pcxt_ssm_bug */
 548         rsm     PSW_SM_I, %r0           /* barrier for "Relied upon Translation */
 549         mtsp    %r0, %sr4
 550         mtsp    %r0, %sr5
 551         mtsp    %r0, %sr6
 552         tovirt_r1 %r29
 553         load32  KERNEL_PSW, %r1
 554
 555         rsm     PSW_SM_QUIET,%r0        /* second "heavy weight" ctl op */
 556         mtctl   %r0, %cr17              /* Clear IIASQ tail */
 557         mtctl   %r0, %cr17              /* Clear IIASQ head */
 558         mtctl   %r1, %ipsw
 559         load32  4f, %r1
 560         mtctl   %r1, %cr18              /* Set IIAOQ tail */
 561         ldo     4(%r1), %r1
 562         mtctl   %r1, %cr18              /* Set IIAOQ head */
 563         rfir
 564         nop
 565 4:
 566         .endm
 567
 568
 569         /*
 570          * ASM_EXCEPTIONTABLE_ENTRY
 571          *
 572          * Creates an exception table entry.
 573          * Do not convert to a assembler macro. This won't work.
 574          */
 575 #define ASM_EXCEPTIONTABLE_ENTRY(fault_addr, except_addr)       \
 576         .section __ex_table,"aw"                        !       \
 577         .word (fault_addr - .), (except_addr - .)       !       \
 578         .previous
 579
 580
 581 #endif /* __ASSEMBLY__ */
 582 #endif