arch/powerpc/cpu/74xx_7xx/start.S

   1 /*
   2  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   3  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   4  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
   5  *  Copyright (C) 2001  Josh Huber <huber@mclx.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*  U-Boot - Startup Code for PowerPC based Embedded Boards
  11  *
  12  *
  13  *  The processor starts at 0xfff00100 and the code is executed
  14  *  from flash. The code is organized to be at an other address
  15  *  in memory, but as long we don't jump around before relocating.
  16  *  board_init lies at a quite high address and when the cpu has
  17  *  jumped there, everything is ok.
  18  */
  19 #include <asm-offsets.h>
  20 #include <config.h>
  21 #include <74xx_7xx.h>
  22 #include <version.h>
  23
  24 #include <ppc_asm.tmpl>
  25 #include <ppc_defs.h>
  26
  27 #include <asm/cache.h>
  28 #include <asm/mmu.h>
  29 #include <asm/u-boot.h>
  30
  31 /* We don't want the  MMU yet.
  32 */
  33 #undef  MSR_KERNEL
  34 /* Machine Check and Recoverable Interr. */
  35 #define MSR_KERNEL ( MSR_ME | MSR_RI )
  36
  37 /*
  38  * Set up GOT: Global Offset Table
  39  *
  40  * Use r12 to access the GOT
  41  */
  42         START_GOT
  43         GOT_ENTRY(_GOT2_TABLE_)
  44         GOT_ENTRY(_FIXUP_TABLE_)
  45
  46         GOT_ENTRY(_start)
  47         GOT_ENTRY(_start_of_vectors)
  48         GOT_ENTRY(_end_of_vectors)
  49         GOT_ENTRY(transfer_to_handler)
  50
  51         GOT_ENTRY(__init_end)
  52         GOT_ENTRY(__bss_end)
  53         GOT_ENTRY(__bss_start)
  54         END_GOT
  55
  56 /*
  57  * r3 - 1st arg to board_init(): IMMP pointer
  58  * r4 - 2nd arg to board_init(): boot flag
  59  */
  60         .text
  61         .long   0x27051956              /* U-Boot Magic Number          */
  62         .globl  version_string
  63 version_string:
  64         .ascii U_BOOT_VERSION_STRING, "\0"
  65
  66         . = EXC_OFF_SYS_RESET
  67         .globl  _start
  68 _start:
  69         b       boot_cold
  70
  71         /* the boot code is located below the exception table */
  72
  73         .globl  _start_of_vectors
  74 _start_of_vectors:
  75
  76 /* Machine check */
  77         STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  78
  79 /* Data Storage exception.  "Never" generated on the 860. */
  80         STD_EXCEPTION(0x300, DataStorage, UnknownException)
  81
  82 /* Instruction Storage exception.  "Never" generated on the 860. */
  83         STD_EXCEPTION(0x400, InstStorage, UnknownException)
  84
  85 /* External Interrupt exception. */
  86         STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
  87
  88 /* Alignment exception. */
  89         . = 0x600
  90 Alignment:
  91         EXCEPTION_PROLOG(SRR0, SRR1)
  92         mfspr   r4,DAR
  93         stw     r4,_DAR(r21)
  94         mfspr   r5,DSISR
  95         stw     r5,_DSISR(r21)
  96         addi    r3,r1,STACK_FRAME_OVERHEAD
  97         EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
  98
  99 /* Program check exception */
 100         . = 0x700
 101 ProgramCheck:
 102         EXCEPTION_PROLOG(SRR0, SRR1)
 103         addi    r3,r1,STACK_FRAME_OVERHEAD
 104         EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
 105                 MSR_KERNEL, COPY_EE)
 106
 107         /* No FPU on MPC8xx.  This exception is not supposed to happen.
 108         */
 109         STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 110
 111         /* I guess we could implement decrementer, and may have
 112          * to someday for timekeeping.
 113          */
 114         STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
 115         STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
 116         STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
 117         STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 118         STD_EXCEPTION(0xd00, SingleStep, UnknownException)
 119
 120         STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
 121         STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
 122
 123         /*
 124          * On the MPC8xx, this is a software emulation interrupt. It
 125          * occurs for all unimplemented and illegal instructions.
 126          */
 127         STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
 128
 129         STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
 130         STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
 131         STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
 132         STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
 133
 134         STD_EXCEPTION(0x1500, Reserved5, UnknownException)
 135         STD_EXCEPTION(0x1600, Reserved6, UnknownException)
 136         STD_EXCEPTION(0x1700, Reserved7, UnknownException)
 137         STD_EXCEPTION(0x1800, Reserved8, UnknownException)
 138         STD_EXCEPTION(0x1900, Reserved9, UnknownException)
 139         STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
 140         STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
 141
 142         STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
 143         STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
 144         STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
 145         STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
 146
 147         .globl  _end_of_vectors
 148 _end_of_vectors:
 149
 150         . = 0x2000
 151
 152 boot_cold:
 153         /* disable everything */
 154         li      r0, 0
 155         mtspr   HID0, r0
 156         sync
 157         mtmsr   0
 158         bl      invalidate_bats
 159         sync
 160
 161 #ifdef CONFIG_SYS_L2
 162         /* init the L2 cache */
 163         addis   r3, r0, L2_INIT@h
 164         ori     r3, r3, L2_INIT@l
 165         sync
 166         mtspr   l2cr, r3
 167 #endif
 168 #if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
 169         .long   0x7e00066c
 170                 /*
 171                  * dssall instruction, gas doesn't have it yet
 172                  * ...for altivec, data stream stop all this probably
 173                  * isn't needed unless we warm (software) reboot U-Boot
 174                  */
 175 #endif
 176
 177 #ifdef CONFIG_SYS_L2
 178         /* invalidate the L2 cache */
 179         bl      l2cache_invalidate
 180         sync
 181 #endif
 182 #ifdef CONFIG_SYS_BOARD_ASM_INIT
 183         /* do early init */
 184         bl      board_asm_init
 185 #endif
 186
 187         /*
 188          * Calculate absolute address in FLASH and jump there
 189          *------------------------------------------------------*/
 190         lis     r3, CONFIG_SYS_MONITOR_BASE@h
 191         ori     r3, r3, CONFIG_SYS_MONITOR_BASE@l
 192         addi    r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
 193         mtlr    r3
 194         blr
 195
 196 in_flash:
 197         /* let the C-code set up the rest                       */
 198         /*                                                      */
 199         /* Be careful to keep code relocatable !                */
 200         /*------------------------------------------------------*/
 201
 202         /* perform low-level init */
 203         /* sdram init, galileo init, etc */
 204         /* r3:  NHR bit from HID0 */
 205
 206         /* setup the bats */
 207         bl      setup_bats
 208         sync
 209
 210         /*
 211          * Cache must be enabled here for stack-in-cache trick.
 212          * This means we need to enable the BATS.
 213          * This means:
 214          *   1) for the EVB, original gt regs need to be mapped
 215          *   2) need to have an IBAT for the 0xf region,
 216          *      we are running there!
 217          * Cache should be turned on after BATs, since by default
 218          * everything is write-through.
 219          * The init-mem BAT can be reused after reloc. The old
 220          * gt-regs BAT can be reused after board_init_f calls
 221          * board_early_init_f (EVB only).
 222          */
 223 #if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx)
 224         /* enable address translation */
 225         bl      enable_addr_trans
 226         sync
 227
 228         /* enable and invalidate the data cache */
 229         bl      l1dcache_enable
 230         sync
 231 #endif
 232 #ifdef CONFIG_SYS_INIT_RAM_LOCK
 233         bl      lock_ram_in_cache
 234         sync
 235 #endif
 236
 237         /* set up the stack pointer in our newly created
 238          * cache-ram (r1) */
 239         lis     r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
 240         ori     r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
 241
 242         li      r0, 0           /* Make room for stack frame header and */
 243         stwu    r0, -4(r1)      /* clear final stack frame so that      */
 244         stwu    r0, -4(r1)      /* stack backtraces terminate cleanly   */
 245
 246         GET_GOT                 /* initialize GOT access        */
 247
 248         /* run low-level CPU init code     (from Flash) */
 249         bl      cpu_init_f
 250         sync
 251
 252         /* run 1st part of board init code (from Flash)   */
 253         bl      board_init_f
 254         sync
 255
 256         /* NOTREACHED - board_init_f() does not return */
 257
 258         .globl  invalidate_bats
 259 invalidate_bats:
 260         /* invalidate BATs */
 261         mtspr   IBAT0U, r0
 262         mtspr   IBAT1U, r0
 263         mtspr   IBAT2U, r0
 264         mtspr   IBAT3U, r0
 265 #ifdef CONFIG_HIGH_BATS
 266         mtspr   IBAT4U, r0
 267         mtspr   IBAT5U, r0
 268         mtspr   IBAT6U, r0
 269         mtspr   IBAT7U, r0
 270 #endif
 271         isync
 272         mtspr   DBAT0U, r0
 273         mtspr   DBAT1U, r0
 274         mtspr   DBAT2U, r0
 275         mtspr   DBAT3U, r0
 276 #ifdef CONFIG_HIGH_BATS
 277         mtspr   DBAT4U, r0
 278         mtspr   DBAT5U, r0
 279         mtspr   DBAT6U, r0
 280         mtspr   DBAT7U, r0
 281 #endif
 282         isync
 283         sync
 284         blr
 285
 286         /* setup_bats - set them up to some initial state */
 287         .globl  setup_bats
 288 setup_bats:
 289         addis   r0, r0, 0x0000
 290
 291         /* IBAT 0 */
 292         addis   r4, r0, CONFIG_SYS_IBAT0L@h
 293         ori     r4, r4, CONFIG_SYS_IBAT0L@l
 294         addis   r3, r0, CONFIG_SYS_IBAT0U@h
 295         ori     r3, r3, CONFIG_SYS_IBAT0U@l
 296         mtspr   IBAT0L, r4
 297         mtspr   IBAT0U, r3
 298         isync
 299
 300         /* DBAT 0 */
 301         addis   r4, r0, CONFIG_SYS_DBAT0L@h
 302         ori     r4, r4, CONFIG_SYS_DBAT0L@l
 303         addis   r3, r0, CONFIG_SYS_DBAT0U@h
 304         ori     r3, r3, CONFIG_SYS_DBAT0U@l
 305         mtspr   DBAT0L, r4
 306         mtspr   DBAT0U, r3
 307         isync
 308
 309         /* IBAT 1 */
 310         addis   r4, r0, CONFIG_SYS_IBAT1L@h
 311         ori     r4, r4, CONFIG_SYS_IBAT1L@l
 312         addis   r3, r0, CONFIG_SYS_IBAT1U@h
 313         ori     r3, r3, CONFIG_SYS_IBAT1U@l
 314         mtspr   IBAT1L, r4
 315         mtspr   IBAT1U, r3
 316         isync
 317
 318         /* DBAT 1 */
 319         addis   r4, r0, CONFIG_SYS_DBAT1L@h
 320         ori     r4, r4, CONFIG_SYS_DBAT1L@l
 321         addis   r3, r0, CONFIG_SYS_DBAT1U@h
 322         ori     r3, r3, CONFIG_SYS_DBAT1U@l
 323         mtspr   DBAT1L, r4
 324         mtspr   DBAT1U, r3
 325         isync
 326
 327         /* IBAT 2 */
 328         addis   r4, r0, CONFIG_SYS_IBAT2L@h
 329         ori     r4, r4, CONFIG_SYS_IBAT2L@l
 330         addis   r3, r0, CONFIG_SYS_IBAT2U@h
 331         ori     r3, r3, CONFIG_SYS_IBAT2U@l
 332         mtspr   IBAT2L, r4
 333         mtspr   IBAT2U, r3
 334         isync
 335
 336         /* DBAT 2 */
 337         addis   r4, r0, CONFIG_SYS_DBAT2L@h
 338         ori     r4, r4, CONFIG_SYS_DBAT2L@l
 339         addis   r3, r0, CONFIG_SYS_DBAT2U@h
 340         ori     r3, r3, CONFIG_SYS_DBAT2U@l
 341         mtspr   DBAT2L, r4
 342         mtspr   DBAT2U, r3
 343         isync
 344
 345         /* IBAT 3 */
 346         addis   r4, r0, CONFIG_SYS_IBAT3L@h
 347         ori     r4, r4, CONFIG_SYS_IBAT3L@l
 348         addis   r3, r0, CONFIG_SYS_IBAT3U@h
 349         ori     r3, r3, CONFIG_SYS_IBAT3U@l
 350         mtspr   IBAT3L, r4
 351         mtspr   IBAT3U, r3
 352         isync
 353
 354         /* DBAT 3 */
 355         addis   r4, r0, CONFIG_SYS_DBAT3L@h
 356         ori     r4, r4, CONFIG_SYS_DBAT3L@l
 357         addis   r3, r0, CONFIG_SYS_DBAT3U@h
 358         ori     r3, r3, CONFIG_SYS_DBAT3U@l
 359         mtspr   DBAT3L, r4
 360         mtspr   DBAT3U, r3
 361         isync
 362
 363 #ifdef CONFIG_HIGH_BATS
 364         /* IBAT 4 */
 365         addis   r4, r0, CONFIG_SYS_IBAT4L@h
 366         ori     r4, r4, CONFIG_SYS_IBAT4L@l
 367         addis   r3, r0, CONFIG_SYS_IBAT4U@h
 368         ori     r3, r3, CONFIG_SYS_IBAT4U@l
 369         mtspr   IBAT4L, r4
 370         mtspr   IBAT4U, r3
 371         isync
 372
 373         /* DBAT 4 */
 374         addis   r4, r0, CONFIG_SYS_DBAT4L@h
 375         ori     r4, r4, CONFIG_SYS_DBAT4L@l
 376         addis   r3, r0, CONFIG_SYS_DBAT4U@h
 377         ori     r3, r3, CONFIG_SYS_DBAT4U@l
 378         mtspr   DBAT4L, r4
 379         mtspr   DBAT4U, r3
 380         isync
 381
 382         /* IBAT 5 */
 383         addis   r4, r0, CONFIG_SYS_IBAT5L@h
 384         ori     r4, r4, CONFIG_SYS_IBAT5L@l
 385         addis   r3, r0, CONFIG_SYS_IBAT5U@h
 386         ori     r3, r3, CONFIG_SYS_IBAT5U@l
 387         mtspr   IBAT5L, r4
 388         mtspr   IBAT5U, r3
 389         isync
 390
 391         /* DBAT 5 */
 392         addis   r4, r0, CONFIG_SYS_DBAT5L@h
 393         ori     r4, r4, CONFIG_SYS_DBAT5L@l
 394         addis   r3, r0, CONFIG_SYS_DBAT5U@h
 395         ori     r3, r3, CONFIG_SYS_DBAT5U@l
 396         mtspr   DBAT5L, r4
 397         mtspr   DBAT5U, r3
 398         isync
 399
 400         /* IBAT 6 */
 401         addis   r4, r0, CONFIG_SYS_IBAT6L@h
 402         ori     r4, r4, CONFIG_SYS_IBAT6L@l
 403         addis   r3, r0, CONFIG_SYS_IBAT6U@h
 404         ori     r3, r3, CONFIG_SYS_IBAT6U@l
 405         mtspr   IBAT6L, r4
 406         mtspr   IBAT6U, r3
 407         isync
 408
 409         /* DBAT 6 */
 410         addis   r4, r0, CONFIG_SYS_DBAT6L@h
 411         ori     r4, r4, CONFIG_SYS_DBAT6L@l
 412         addis   r3, r0, CONFIG_SYS_DBAT6U@h
 413         ori     r3, r3, CONFIG_SYS_DBAT6U@l
 414         mtspr   DBAT6L, r4
 415         mtspr   DBAT6U, r3
 416         isync
 417
 418         /* IBAT 7 */
 419         addis   r4, r0, CONFIG_SYS_IBAT7L@h
 420         ori     r4, r4, CONFIG_SYS_IBAT7L@l
 421         addis   r3, r0, CONFIG_SYS_IBAT7U@h
 422         ori     r3, r3, CONFIG_SYS_IBAT7U@l
 423         mtspr   IBAT7L, r4
 424         mtspr   IBAT7U, r3
 425         isync
 426
 427         /* DBAT 7 */
 428         addis   r4, r0, CONFIG_SYS_DBAT7L@h
 429         ori     r4, r4, CONFIG_SYS_DBAT7L@l
 430         addis   r3, r0, CONFIG_SYS_DBAT7U@h
 431         ori     r3, r3, CONFIG_SYS_DBAT7U@l
 432         mtspr   DBAT7L, r4
 433         mtspr   DBAT7U, r3
 434         isync
 435 #endif
 436
 437         /* bats are done, now invalidate the TLBs */
 438
 439         addis   r3, 0, 0x0000
 440         addis   r5, 0, 0x4    /* upper bound of 0x00040000 for 7400/750 */
 441
 442         isync
 443
 444 tlblp:
 445         tlbie   r3
 446         sync
 447         addi    r3, r3, 0x1000
 448         cmp     0, 0, r3, r5
 449         blt tlblp
 450
 451         blr
 452
 453         .globl enable_addr_trans
 454 enable_addr_trans:
 455         /* enable address translation */
 456         mfmsr   r5
 457         ori     r5, r5, (MSR_IR | MSR_DR)
 458         mtmsr   r5
 459         isync
 460         blr
 461
 462         .globl disable_addr_trans
 463 disable_addr_trans:
 464         /* disable address translation */
 465         mflr    r4
 466         mfmsr   r3
 467         andi.   r0, r3, (MSR_IR | MSR_DR)
 468         beqlr
 469         andc    r3, r3, r0
 470         mtspr   SRR0, r4
 471         mtspr   SRR1, r3
 472         rfi
 473
 474 /*
 475  * This code finishes saving the registers to the exception frame
 476  * and jumps to the appropriate handler for the exception.
 477  * Register r21 is pointer into trap frame, r1 has new stack pointer.
 478  */
 479         .globl  transfer_to_handler
 480 transfer_to_handler:
 481         stw     r22,_NIP(r21)
 482         lis     r22,MSR_POW@h
 483         andc    r23,r23,r22
 484         stw     r23,_MSR(r21)
 485         SAVE_GPR(7, r21)
 486         SAVE_4GPRS(8, r21)
 487         SAVE_8GPRS(12, r21)
 488         SAVE_8GPRS(24, r21)
 489         mflr    r23
 490         andi.   r24,r23,0x3f00          /* get vector offset */
 491         stw     r24,TRAP(r21)
 492         li      r22,0
 493         stw     r22,RESULT(r21)
 494         mtspr   SPRG2,r22               /* r1 is now kernel sp */
 495         lwz     r24,0(r23)              /* virtual address of handler */
 496         lwz     r23,4(r23)              /* where to go when done */
 497         mtspr   SRR0,r24
 498         mtspr   SRR1,r20
 499         mtlr    r23
 500         SYNC
 501         rfi                             /* jump to handler, enable MMU */
 502
 503 int_return:
 504         mfmsr   r28             /* Disable interrupts */
 505         li      r4,0
 506         ori     r4,r4,MSR_EE
 507         andc    r28,r28,r4
 508         SYNC                    /* Some chip revs need this... */
 509         mtmsr   r28
 510         SYNC
 511         lwz     r2,_CTR(r1)
 512         lwz     r0,_LINK(r1)
 513         mtctr   r2
 514         mtlr    r0
 515         lwz     r2,_XER(r1)
 516         lwz     r0,_CCR(r1)
 517         mtspr   XER,r2
 518         mtcrf   0xFF,r0
 519         REST_10GPRS(3, r1)
 520         REST_10GPRS(13, r1)
 521         REST_8GPRS(23, r1)
 522         REST_GPR(31, r1)
 523         lwz     r2,_NIP(r1)     /* Restore environment */
 524         lwz     r0,_MSR(r1)
 525         mtspr   SRR0,r2
 526         mtspr   SRR1,r0
 527         lwz     r0,GPR0(r1)
 528         lwz     r2,GPR2(r1)
 529         lwz     r1,GPR1(r1)
 530         SYNC
 531         rfi
 532
 533         .globl  dc_read
 534 dc_read:
 535         blr
 536
 537         .globl get_pvr
 538 get_pvr:
 539         mfspr   r3, PVR
 540         blr
 541
 542 /*-----------------------------------------------------------------------*/
 543 /*
 544  * void relocate_code (addr_sp, gd, addr_moni)
 545  *
 546  * This "function" does not return, instead it continues in RAM
 547  * after relocating the monitor code.
 548  *
 549  * r3 = dest
 550  * r4 = src
 551  * r5 = length in bytes
 552  * r6 = cachelinesize
 553  */
 554         .globl  relocate_code
 555 relocate_code:
 556         mr      r1,  r3         /* Set new stack pointer                */
 557         mr      r9,  r4         /* Save copy of Global Data pointer     */
 558         mr      r10, r5         /* Save copy of Destination Address     */
 559
 560         GET_GOT
 561         mr      r3,  r5                         /* Destination Address  */
 562         lis     r4, CONFIG_SYS_MONITOR_BASE@h           /* Source      Address  */
 563         ori     r4, r4, CONFIG_SYS_MONITOR_BASE@l
 564         lwz     r5, GOT(__init_end)
 565         sub     r5, r5, r4
 566         li      r6, CONFIG_SYS_CACHELINE_SIZE           /* Cache Line Size      */
 567
 568         /*
 569          * Fix GOT pointer:
 570          *
 571          * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
 572          *
 573          * Offset:
 574          */
 575         sub     r15, r10, r4
 576
 577         /* First our own GOT */
 578         add     r12, r12, r15
 579         /* then the one used by the C code */
 580         add     r30, r30, r15
 581
 582         /*
 583          * Now relocate code
 584          */
 585 #ifdef CONFIG_ECC
 586         bl      board_relocate_rom
 587         sync
 588         mr      r3, r10                         /* Destination Address  */
 589         lis     r4, CONFIG_SYS_MONITOR_BASE@h           /* Source      Address  */
 590         ori     r4, r4, CONFIG_SYS_MONITOR_BASE@l
 591         lwz     r5, GOT(__init_end)
 592         sub     r5, r5, r4
 593         li      r6, CONFIG_SYS_CACHELINE_SIZE           /* Cache Line Size      */
 594 #else
 595         cmplw   cr1,r3,r4
 596         addi    r0,r5,3
 597         srwi.   r0,r0,2
 598         beq     cr1,4f          /* In place copy is not necessary       */
 599         beq     7f              /* Protect against 0 count              */
 600         mtctr   r0
 601         bge     cr1,2f
 602
 603         la      r8,-4(r4)
 604         la      r7,-4(r3)
 605 1:      lwzu    r0,4(r8)
 606         stwu    r0,4(r7)
 607         bdnz    1b
 608         b       4f
 609
 610 2:      slwi    r0,r0,2
 611         add     r8,r4,r0
 612         add     r7,r3,r0
 613 3:      lwzu    r0,-4(r8)
 614         stwu    r0,-4(r7)
 615         bdnz    3b
 616 #endif
 617 /*
 618  * Now flush the cache: note that we must start from a cache aligned
 619  * address. Otherwise we might miss one cache line.
 620  */
 621 4:      cmpwi   r6,0
 622         add     r5,r3,r5
 623         beq     7f              /* Always flush prefetch queue in any case */
 624         subi    r0,r6,1
 625         andc    r3,r3,r0
 626         mr      r4,r3
 627 5:      dcbst   0,r4
 628         add     r4,r4,r6
 629         cmplw   r4,r5
 630         blt     5b
 631         sync                    /* Wait for all dcbst to complete on bus */
 632         mr      r4,r3
 633 6:      icbi    0,r4
 634         add     r4,r4,r6
 635         cmplw   r4,r5
 636         blt     6b
 637 7:      sync                    /* Wait for all icbi to complete on bus */
 638         isync
 639
 640 /*
 641  * We are done. Do not return, instead branch to second part of board
 642  * initialization, now running from RAM.
 643  */
 644         addi    r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
 645         mtlr    r0
 646         blr
 647
 648 in_ram:
 649 #ifdef CONFIG_ECC
 650         bl      board_init_ecc
 651 #endif
 652         /*
 653          * Relocation Function, r12 point to got2+0x8000
 654          *
 655          * Adjust got2 pointers, no need to check for 0, this code
 656          * already puts a few entries in the table.
 657          */
 658         li      r0,__got2_entries@sectoff@l
 659         la      r3,GOT(_GOT2_TABLE_)
 660         lwz     r11,GOT(_GOT2_TABLE_)
 661         mtctr   r0
 662         sub     r11,r3,r11
 663         addi    r3,r3,-4
 664 1:      lwzu    r0,4(r3)
 665         cmpwi   r0,0
 666         beq-    2f
 667         add     r0,r0,r11
 668         stw     r0,0(r3)
 669 2:      bdnz    1b
 670
 671         /*
 672          * Now adjust the fixups and the pointers to the fixups
 673          * in case we need to move ourselves again.
 674          */
 675         li      r0,__fixup_entries@sectoff@l
 676         lwz     r3,GOT(_FIXUP_TABLE_)
 677         cmpwi   r0,0
 678         mtctr   r0
 679         addi    r3,r3,-4
 680         beq     4f
 681 3:      lwzu    r4,4(r3)
 682         lwzux   r0,r4,r11
 683         cmpwi   r0,0
 684         add     r0,r0,r11
 685         stw     r4,0(r3)
 686         beq-    5f
 687         stw     r0,0(r4)
 688 5:      bdnz    3b
 689 4:
 690 /* clear_bss: */
 691         /*
 692          * Now clear BSS segment
 693          */
 694         lwz     r3,GOT(__bss_start)
 695         lwz     r4,GOT(__bss_end)
 696
 697         cmplw   0, r3, r4
 698         beq     6f
 699
 700         li      r0, 0
 701 5:
 702         stw     r0, 0(r3)
 703         addi    r3, r3, 4
 704         cmplw   0, r3, r4
 705         bne     5b
 706 6:
 707         mr      r3, r10         /* Destination Address          */
 708 #if defined(CONFIG_PPMC7XX)
 709         mr      r4, r9          /* Use RAM copy of the global data */
 710 #endif
 711         bl      after_reloc
 712
 713         /* not reached - end relocate_code */
 714 /*-----------------------------------------------------------------------*/
 715
 716         /*
 717          * Copy exception vector code to low memory
 718          *
 719          * r3: dest_addr
 720          * r7: source address, r8: end address, r9: target address
 721          */
 722         .globl  trap_init
 723 trap_init:
 724         mflr    r4                      /* save link register           */
 725         GET_GOT
 726         lwz     r7, GOT(_start)
 727         lwz     r8, GOT(_end_of_vectors)
 728
 729         li      r9, 0x100               /* reset vector always at 0x100 */
 730
 731         cmplw   0, r7, r8
 732         bgelr                           /* return if r7>=r8 - just in case */
 733 1:
 734         lwz     r0, 0(r7)
 735         stw     r0, 0(r9)
 736         addi    r7, r7, 4
 737         addi    r9, r9, 4
 738         cmplw   0, r7, r8
 739         bne     1b
 740
 741         /*
 742          * relocate `hdlr' and `int_return' entries
 743          */
 744         li      r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
 745         li      r8, Alignment - _start + EXC_OFF_SYS_RESET
 746 2:
 747         bl      trap_reloc
 748         addi    r7, r7, 0x100           /* next exception vector        */
 749         cmplw   0, r7, r8
 750         blt     2b
 751
 752         li      r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
 753         bl      trap_reloc
 754
 755         li      r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
 756         bl      trap_reloc
 757
 758         li      r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
 759         li      r8, SystemCall - _start + EXC_OFF_SYS_RESET
 760 3:
 761         bl      trap_reloc
 762         addi    r7, r7, 0x100           /* next exception vector        */
 763         cmplw   0, r7, r8
 764         blt     3b
 765
 766         li      r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
 767         li      r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
 768 4:
 769         bl      trap_reloc
 770         addi    r7, r7, 0x100           /* next exception vector        */
 771         cmplw   0, r7, r8
 772         blt     4b
 773
 774         /* enable execptions from RAM vectors */
 775         mfmsr   r7
 776         li      r8,MSR_IP
 777         andc    r7,r7,r8
 778         mtmsr   r7
 779
 780         mtlr    r4                      /* restore link register        */
 781         blr
 782
 783 #ifdef CONFIG_SYS_INIT_RAM_LOCK
 784 lock_ram_in_cache:
 785         /* Allocate Initial RAM in data cache.
 786          */
 787         lis     r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
 788         ori     r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
 789         li      r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
 790                      (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
 791         mtctr   r4
 792 1:
 793         dcbz    r0, r3
 794         addi    r3, r3, 32
 795         bdnz    1b
 796
 797         /* Lock the data cache */
 798         mfspr   r0, HID0
 799         ori     r0, r0, 0x1000
 800         sync
 801         mtspr   HID0, r0
 802         sync
 803         blr
 804
 805 .globl unlock_ram_in_cache
 806 unlock_ram_in_cache:
 807         /* invalidate the INIT_RAM section */
 808         lis     r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
 809         ori     r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
 810         li      r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
 811                      (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
 812         mtctr   r4
 813 1:      icbi    r0, r3
 814         addi    r3, r3, 32
 815         bdnz    1b
 816         sync                    /* Wait for all icbi to complete on bus */
 817         isync
 818
 819         /* Unlock the data cache and invalidate it */
 820         mfspr   r0, HID0
 821         li      r3,0x1000
 822         andc    r0,r0,r3
 823         li      r3,0x0400
 824         or      r0,r0,r3
 825         sync
 826         mtspr   HID0, r0
 827         sync
 828         blr
 829 #endif