arch/powerpc/cpu/mpc512x/start.S

   1 /*
   2  * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   3  * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   4  * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
   5  * Copyright Freescale Semiconductor, Inc. 2004, 2006.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  *
  25  * Based on the MPC83xx code.
  26  */
  27
  28 /*
  29  *  U-Boot - Startup Code for MPC512x based Embedded Boards
  30  */
  31
  32 #include <asm-offsets.h>
  33 #include <config.h>
  34 #include <timestamp.h>
  35 #include <version.h>
  36
  37 #define CONFIG_521X     1               /* needed for Linux kernel header files*/
  38
  39 #include <asm/immap_512x.h>
  40 #include "asm-offsets.h"
  41
  42 #include <ppc_asm.tmpl>
  43 #include <ppc_defs.h>
  44
  45 #include <asm/cache.h>
  46 #include <asm/mmu.h>
  47 #include <asm/u-boot.h>
  48
  49 #ifndef  CONFIG_IDENT_STRING
  50 #define  CONFIG_IDENT_STRING "MPC512X"
  51 #endif
  52
  53 /*
  54  * Floating Point enable, Machine Check and Recoverable Interr.
  55  */
  56 #undef  MSR_KERNEL
  57 #ifdef DEBUG
  58 #define MSR_KERNEL (MSR_FP|MSR_RI)
  59 #else
  60 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
  61 #endif
  62
  63 /* Macros for manipulating CSx_START/STOP */
  64 #define START_REG(start)        ((start) >> 16)
  65 #define STOP_REG(start, size)   (((start) + (size) - 1) >> 16)
  66
  67 /*
  68  * Set up GOT: Global Offset Table
  69  *
  70  * Use r12 to access the GOT
  71  */
  72         START_GOT
  73         GOT_ENTRY(_GOT2_TABLE_)
  74         GOT_ENTRY(_FIXUP_TABLE_)
  75
  76         GOT_ENTRY(_start)
  77         GOT_ENTRY(_start_of_vectors)
  78         GOT_ENTRY(_end_of_vectors)
  79         GOT_ENTRY(transfer_to_handler)
  80
  81         GOT_ENTRY(__init_end)
  82         GOT_ENTRY(_end)
  83         GOT_ENTRY(__bss_start)
  84         END_GOT
  85
  86 /*
  87  * Magic number and version string
  88  */
  89         .long   0x27051956              /* U-Boot Magic Number */
  90         .globl  version_string
  91 version_string:
  92         .ascii U_BOOT_VERSION
  93         .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
  94         .ascii " ", CONFIG_IDENT_STRING, "\0"
  95
  96 /*
  97  * Vector Table
  98  */
  99         .text
 100         . = EXC_OFF_SYS_RESET
 101
 102         .globl  _start
 103         /* Start from here after reset/power on */
 104 _start:
 105         b       boot_cold
 106
 107         .globl  _start_of_vectors
 108 _start_of_vectors:
 109
 110 /* Machine check */
 111         STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 112
 113 /* Data Storage exception. */
 114         STD_EXCEPTION(0x300, DataStorage, UnknownException)
 115
 116 /* Instruction Storage exception. */
 117         STD_EXCEPTION(0x400, InstStorage, UnknownException)
 118
 119 /* External Interrupt exception. */
 120         STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
 121
 122 /* Alignment exception. */
 123         . = 0x600
 124 Alignment:
 125         EXCEPTION_PROLOG(SRR0, SRR1)
 126         mfspr   r4,DAR
 127         stw     r4,_DAR(r21)
 128         mfspr   r5,DSISR
 129         stw     r5,_DSISR(r21)
 130         addi    r3,r1,STACK_FRAME_OVERHEAD
 131         EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
 132
 133 /* Program check exception */
 134         . = 0x700
 135 ProgramCheck:
 136         EXCEPTION_PROLOG(SRR0, SRR1)
 137         addi    r3,r1,STACK_FRAME_OVERHEAD
 138         EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
 139                 MSR_KERNEL, COPY_EE)
 140
 141 /* Floating Point Unit unavailable exception */
 142         STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 143
 144 /* Decrementer */
 145         STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
 146
 147 /* Critical interrupt */
 148         STD_EXCEPTION(0xa00, Critical, UnknownException)
 149
 150 /* System Call */
 151         STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 152
 153 /* Trace interrupt */
 154         STD_EXCEPTION(0xd00, Trace, UnknownException)
 155
 156 /* Performance Monitor interrupt */
 157         STD_EXCEPTION(0xf00, PerfMon, UnknownException)
 158
 159 /* Intruction Translation Miss */
 160         STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
 161
 162 /* Data Load Translation Miss */
 163         STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
 164
 165 /* Data Store Translation Miss */
 166         STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
 167
 168 /* Instruction Address Breakpoint */
 169         STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
 170
 171 /* System Management interrupt */
 172         STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
 173
 174         .globl  _end_of_vectors
 175 _end_of_vectors:
 176
 177         . = 0x3000
 178 boot_cold:
 179         /* Save msr contents */
 180         mfmsr   r5
 181
 182         /* Set IMMR area to our preferred location */
 183         lis     r4, CONFIG_DEFAULT_IMMR@h
 184         lis     r3, CONFIG_SYS_IMMR@h
 185         ori     r3, r3, CONFIG_SYS_IMMR@l
 186         stw     r3, IMMRBAR(r4)
 187         mtspr   MBAR, r3                /* IMMRBAR is mirrored into the MBAR SPR (311) */
 188
 189         /* Initialise the machine */
 190         bl      cpu_early_init
 191
 192         /*
 193          * Set up Local Access Windows:
 194          *
 195          * 1) Boot/CS0 (boot FLASH)
 196          * 2) On-chip SRAM (initial stack purposes)
 197          */
 198
 199         /* Boot CS/CS0 window range */
 200         lis     r3, CONFIG_SYS_IMMR@h
 201         ori     r3, r3, CONFIG_SYS_IMMR@l
 202
 203         lis     r4, START_REG(CONFIG_SYS_FLASH_BASE)
 204         ori     r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
 205         stw     r4, LPCS0AW(r3)
 206
 207         /*
 208          * The SRAM window has a fixed size (256K), so only the start address
 209          * is necessary
 210          */
 211         lis     r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
 212         stw     r4, SRAMBAR(r3)
 213
 214         /*
 215          * According to MPC5121e RM, configuring local access windows should
 216          * be followed by a dummy read of the config register that was
 217          * modified last and an isync
 218          */
 219         lwz     r4, SRAMBAR(r3)
 220         isync
 221
 222         /*
 223          * Set configuration of the Boot/CS0, the SRAM window does not have a
 224          * config register so no params can be set for it
 225          */
 226         lis     r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
 227         ori     r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
 228
 229         lis     r4, CONFIG_SYS_CS0_CFG@h
 230         ori     r4, r4, CONFIG_SYS_CS0_CFG@l
 231         stw     r4, CS0_CONFIG(r3)
 232
 233         /* Master enable all CS's */
 234         lis     r4, CS_CTRL_ME@h
 235         ori     r4, r4, CS_CTRL_ME@l
 236         stw     r4, CS_CTRL(r3)
 237
 238         lis     r4, (CONFIG_SYS_MONITOR_BASE)@h
 239         ori     r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
 240         addi    r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
 241         mtlr    r5
 242         blr
 243
 244 in_flash:
 245         lis     r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
 246         ori     r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
 247
 248         li      r0, 0           /* Make room for stack frame header and */
 249         stwu    r0, -4(r1)      /* clear final stack frame so that      */
 250         stwu    r0, -4(r1)      /* stack backtraces terminate cleanly   */
 251
 252         /* let the C-code set up the rest                       */
 253         /*                                                      */
 254         /* Be careful to keep code relocatable & stack humble   */
 255         /*------------------------------------------------------*/
 256
 257         GET_GOT                 /* initialize GOT access        */
 258
 259         /* r3: IMMR */
 260         lis     r3, CONFIG_SYS_IMMR@h
 261         /* run low-level CPU init code (in Flash) */
 262         bl      cpu_init_f
 263
 264         /* run 1st part of board init code (in Flash) */
 265         bl      board_init_f
 266
 267         /* NOTREACHED - board_init_f() does not return */
 268
 269 /*
 270  * This code finishes saving the registers to the exception frame
 271  * and jumps to the appropriate handler for the exception.
 272  * Register r21 is pointer into trap frame, r1 has new stack pointer.
 273  */
 274         .globl  transfer_to_handler
 275 transfer_to_handler:
 276         stw     r22,_NIP(r21)
 277         lis     r22,MSR_POW@h
 278         andc    r23,r23,r22
 279         stw     r23,_MSR(r21)
 280         SAVE_GPR(7, r21)
 281         SAVE_4GPRS(8, r21)
 282         SAVE_8GPRS(12, r21)
 283         SAVE_8GPRS(24, r21)
 284         mflr    r23
 285         andi.   r24,r23,0x3f00          /* get vector offset */
 286         stw     r24,TRAP(r21)
 287         li      r22,0
 288         stw     r22,RESULT(r21)
 289         lwz     r24,0(r23)              /* virtual address of handler */
 290         lwz     r23,4(r23)              /* where to go when done */
 291         mtspr   SRR0,r24
 292         mtspr   SRR1,r20
 293         mtlr    r23
 294         SYNC
 295         rfi                             /* jump to handler, enable MMU */
 296
 297 int_return:
 298         mfmsr   r28             /* Disable interrupts */
 299         li      r4,0
 300         ori     r4,r4,MSR_EE
 301         andc    r28,r28,r4
 302         SYNC                    /* Some chip revs need this... */
 303         mtmsr   r28
 304         SYNC
 305         lwz     r2,_CTR(r1)
 306         lwz     r0,_LINK(r1)
 307         mtctr   r2
 308         mtlr    r0
 309         lwz     r2,_XER(r1)
 310         lwz     r0,_CCR(r1)
 311         mtspr   XER,r2
 312         mtcrf   0xFF,r0
 313         REST_10GPRS(3, r1)
 314         REST_10GPRS(13, r1)
 315         REST_8GPRS(23, r1)
 316         REST_GPR(31, r1)
 317         lwz     r2,_NIP(r1)     /* Restore environment */
 318         lwz     r0,_MSR(r1)
 319         mtspr   SRR0,r2
 320         mtspr   SRR1,r0
 321         lwz     r0,GPR0(r1)
 322         lwz     r2,GPR2(r1)
 323         lwz     r1,GPR1(r1)
 324         SYNC
 325         rfi
 326
 327 /*
 328  * This code initialises the machine, it expects original MSR contents to be in r5.
 329  */
 330 cpu_early_init:
 331         /* Initialize machine status; enable machine check interrupt */
 332         /*-----------------------------------------------------------*/
 333
 334         li      r3, MSR_KERNEL                  /* Set ME and RI flags */
 335         rlwimi  r3, r5, 0, 25, 25               /* preserve IP bit */
 336 #ifdef DEBUG
 337         rlwimi  r3, r5, 0, 21, 22               /* debugger might set SE, BE bits */
 338 #endif
 339         mtmsr   r3
 340         SYNC
 341         mtspr   SRR1, r3                        /* Mirror current MSR state in SRR1 */
 342
 343         lis     r3, CONFIG_SYS_IMMR@h
 344
 345 #if defined(CONFIG_WATCHDOG)
 346         /* Initialise the watchdog and reset it */
 347         /*--------------------------------------*/
 348         lis r4, CONFIG_SYS_WATCHDOG_VALUE
 349         ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
 350         stw r4, SWCRR(r3)
 351
 352         /* reset */
 353         li      r4, 0x556C
 354         sth     r4, SWSRR@l(r3)
 355         li      r4, 0x0
 356         ori     r4, r4, 0xAA39
 357         sth     r4, SWSRR@l(r3)
 358 #else
 359         /* Disable the watchdog */
 360         /*----------------------*/
 361         lwz r4, SWCRR(r3)
 362         /*
 363          * Check to see if it's enabled for disabling: once disabled by s/w
 364          * it's not possible to re-enable it
 365          */
 366         andi. r4, r4, 0x4
 367         beq 1f
 368         xor r4, r4, r4
 369         stw r4, SWCRR(r3)
 370 1:
 371 #endif /* CONFIG_WATCHDOG */
 372
 373         /* Initialize the Hardware Implementation-dependent Registers */
 374         /* HID0 also contains cache control                     */
 375         /*------------------------------------------------------*/
 376         lis     r3, CONFIG_SYS_HID0_INIT@h
 377         ori     r3, r3, CONFIG_SYS_HID0_INIT@l
 378         SYNC
 379         mtspr   HID0, r3
 380
 381         lis     r3, CONFIG_SYS_HID0_FINAL@h
 382         ori     r3, r3, CONFIG_SYS_HID0_FINAL@l
 383         SYNC
 384         mtspr   HID0, r3
 385
 386         lis     r3, CONFIG_SYS_HID2@h
 387         ori     r3, r3, CONFIG_SYS_HID2@l
 388         SYNC
 389         mtspr   HID2, r3
 390         sync
 391         blr
 392
 393
 394 /* Cache functions.
 395  *
 396  * Note: requires that all cache bits in
 397  * HID0 are in the low half word.
 398  */
 399         .globl  icache_enable
 400 icache_enable:
 401         mfspr   r3, HID0
 402         ori     r3, r3, HID0_ICE
 403         lis     r4, 0
 404         ori     r4, r4, HID0_ILOCK
 405         andc    r3, r3, r4
 406         ori     r4, r3, HID0_ICFI
 407         isync
 408         mtspr   HID0, r4    /* sets enable and invalidate, clears lock */
 409         isync
 410         mtspr   HID0, r3        /* clears invalidate */
 411         blr
 412
 413         .globl  icache_disable
 414 icache_disable:
 415         mfspr   r3, HID0
 416         lis     r4, 0
 417         ori     r4, r4, HID0_ICE|HID0_ILOCK
 418         andc    r3, r3, r4
 419         ori     r4, r3, HID0_ICFI
 420         isync
 421         mtspr   HID0, r4     /* sets invalidate, clears enable and lock*/
 422         isync
 423         mtspr   HID0, r3        /* clears invalidate */
 424         blr
 425
 426         .globl  icache_status
 427 icache_status:
 428         mfspr   r3, HID0
 429         rlwinm  r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
 430         blr
 431
 432         .globl  dcache_enable
 433 dcache_enable:
 434         mfspr   r3, HID0
 435         li      r5, HID0_DCFI|HID0_DLOCK
 436         andc    r3, r3, r5
 437         mtspr   HID0, r3                /* no invalidate, unlock */
 438         ori     r3, r3, HID0_DCE
 439         ori     r5, r3, HID0_DCFI
 440         mtspr   HID0, r5                /* enable + invalidate */
 441         mtspr   HID0, r3                /* enable */
 442         sync
 443         blr
 444
 445         .globl  dcache_disable
 446 dcache_disable:
 447         mfspr   r3, HID0
 448         lis     r4, 0
 449         ori     r4, r4, HID0_DCE|HID0_DLOCK
 450         andc    r3, r3, r4
 451         ori     r4, r3, HID0_DCI
 452         sync
 453         mtspr   HID0, r4        /* sets invalidate, clears enable and lock */
 454         sync
 455         mtspr   HID0, r3        /* clears invalidate */
 456         blr
 457
 458         .globl  dcache_status
 459 dcache_status:
 460         mfspr   r3, HID0
 461         rlwinm  r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
 462         blr
 463
 464         .globl get_pvr
 465 get_pvr:
 466         mfspr   r3, PVR
 467         blr
 468
 469 /*-------------------------------------------------------------------*/
 470
 471 /*
 472  * void relocate_code (addr_sp, gd, addr_moni)
 473  *
 474  * This "function" does not return, instead it continues in RAM
 475  * after relocating the monitor code.
 476  *
 477  * r3 = dest
 478  * r4 = src
 479  * r5 = length in bytes
 480  * r6 = cachelinesize
 481  */
 482         .globl  relocate_code
 483 relocate_code:
 484         mr      r1,  r3         /* Set new stack pointer        */
 485         mr      r9,  r4         /* Save copy of Global Data pointer */
 486         mr      r10, r5         /* Save copy of Destination Address */
 487
 488         GET_GOT
 489         mr      r3,  r5                         /* Destination Address */
 490         lis     r4, CONFIG_SYS_MONITOR_BASE@h           /* Source      Address */
 491         ori     r4, r4, CONFIG_SYS_MONITOR_BASE@l
 492         lwz     r5, GOT(__init_end)
 493         sub     r5, r5, r4
 494         li      r6, CONFIG_SYS_CACHELINE_SIZE           /* Cache Line Size */
 495
 496         /*
 497          * Fix GOT pointer:
 498          *
 499          * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
 500          *              + Destination Address
 501          *
 502          * Offset:
 503          */
 504         sub     r15, r10, r4
 505
 506         /* First our own GOT */
 507         add     r12, r12, r15
 508         /* then the one used by the C code */
 509         add     r30, r30, r15
 510
 511         /*
 512          * Now relocate code
 513          */
 514         cmplw   cr1,r3,r4
 515         addi    r0,r5,3
 516         srwi.   r0,r0,2
 517         beq     cr1,4f          /* In place copy is not necessary */
 518         beq     7f              /* Protect against 0 count        */
 519         mtctr   r0
 520         bge     cr1,2f
 521         la      r8,-4(r4)
 522         la      r7,-4(r3)
 523
 524         /* copy */
 525 1:      lwzu    r0,4(r8)
 526         stwu    r0,4(r7)
 527         bdnz    1b
 528
 529         addi    r0,r5,3
 530         srwi.   r0,r0,2
 531         mtctr   r0
 532         la      r8,-4(r4)
 533         la      r7,-4(r3)
 534
 535         /* and compare */
 536 20:     lwzu    r20,4(r8)
 537         lwzu    r21,4(r7)
 538         xor. r22, r20, r21
 539         bne  30f
 540         bdnz    20b
 541         b 4f
 542
 543         /* compare failed */
 544 30:     li r3, 0
 545         blr
 546
 547 2:      slwi    r0,r0,2 /* re copy in reverse order ... y do we needed it? */
 548         add     r8,r4,r0
 549         add     r7,r3,r0
 550 3:      lwzu    r0,-4(r8)
 551         stwu    r0,-4(r7)
 552         bdnz    3b
 553
 554 /*
 555  * Now flush the cache: note that we must start from a cache aligned
 556  * address. Otherwise we might miss one cache line.
 557  */
 558 4:      cmpwi   r6,0
 559         add     r5,r3,r5
 560         beq     7f              /* Always flush prefetch queue in any case */
 561         subi    r0,r6,1
 562         andc    r3,r3,r0
 563         mr      r4,r3
 564 5:      dcbst   0,r4
 565         add     r4,r4,r6
 566         cmplw   r4,r5
 567         blt     5b
 568         sync                    /* Wait for all dcbst to complete on bus */
 569         mr      r4,r3
 570 6:      icbi    0,r4
 571         add     r4,r4,r6
 572         cmplw   r4,r5
 573         blt     6b
 574 7:      sync                    /* Wait for all icbi to complete on bus */
 575         isync
 576
 577 /*
 578  * We are done. Do not return, instead branch to second part of board
 579  * initialization, now running from RAM.
 580  */
 581         addi    r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
 582         mtlr    r0
 583         blr
 584
 585 in_ram:
 586         /*
 587          * Relocation Function, r12 point to got2+0x8000
 588          *
 589          * Adjust got2 pointers, no need to check for 0, this code
 590          * already puts a few entries in the table.
 591          */
 592         li      r0,__got2_entries@sectoff@l
 593         la      r3,GOT(_GOT2_TABLE_)
 594         lwz     r11,GOT(_GOT2_TABLE_)
 595         mtctr   r0
 596         sub     r11,r3,r11
 597         addi    r3,r3,-4
 598 1:      lwzu    r0,4(r3)
 599         cmpwi   r0,0
 600         beq-    2f
 601         add     r0,r0,r11
 602         stw     r0,0(r3)
 603 2:      bdnz    1b
 604
 605         /*
 606          * Now adjust the fixups and the pointers to the fixups
 607          * in case we need to move ourselves again.
 608          */
 609         li      r0,__fixup_entries@sectoff@l
 610         lwz     r3,GOT(_FIXUP_TABLE_)
 611         cmpwi   r0,0
 612         mtctr   r0
 613         addi    r3,r3,-4
 614         beq     4f
 615 3:      lwzu    r4,4(r3)
 616         lwzux   r0,r4,r11
 617         cmpwi   r0,0
 618         add     r0,r0,r11
 619         stw     r4,0(r3)
 620         beq-    5f
 621         stw     r0,0(r4)
 622 5:      bdnz    3b
 623 4:
 624 clear_bss:
 625         /*
 626          * Now clear BSS segment
 627          */
 628         lwz     r3,GOT(__bss_start)
 629         lwz     r4,GOT(_end)
 630
 631         cmplw   0, r3, r4
 632         beq     6f
 633
 634         li      r0, 0
 635 5:
 636         stw     r0, 0(r3)
 637         addi    r3, r3, 4
 638         cmplw   0, r3, r4
 639         bne     5b
 640 6:
 641         mr      r3, r9          /* Global Data pointer          */
 642         mr      r4, r10         /* Destination Address          */
 643         bl      board_init_r
 644
 645         /*
 646          * Copy exception vector code to low memory
 647          *
 648          * r3: dest_addr
 649          * r7: source address, r8: end address, r9: target address
 650          */
 651         .globl  trap_init
 652 trap_init:
 653         mflr    r4              /* save link register */
 654         GET_GOT
 655         lwz     r7, GOT(_start)
 656         lwz     r8, GOT(_end_of_vectors)
 657
 658         li      r9, 0x100       /* reset vector at 0x100 */
 659
 660         cmplw   0, r7, r8
 661         bgelr                   /* return if r7>=r8 - just in case */
 662 1:
 663         lwz     r0, 0(r7)
 664         stw     r0, 0(r9)
 665         addi    r7, r7, 4
 666         addi    r9, r9, 4
 667         cmplw   0, r7, r8
 668         bne     1b
 669
 670         /*
 671          * relocate `hdlr' and `int_return' entries
 672          */
 673         li      r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
 674         li      r8, Alignment - _start + EXC_OFF_SYS_RESET
 675 2:
 676         bl      trap_reloc
 677         addi    r7, r7, 0x100           /* next exception vector */
 678         cmplw   0, r7, r8
 679         blt     2b
 680
 681         li      r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
 682         bl      trap_reloc
 683
 684         li      r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
 685         bl      trap_reloc
 686
 687         li      r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
 688         li      r8, SystemCall - _start + EXC_OFF_SYS_RESET
 689 3:
 690         bl      trap_reloc
 691         addi    r7, r7, 0x100           /* next exception vector */
 692         cmplw   0, r7, r8
 693         blt     3b
 694
 695         li      r7, .L_Trace - _start + EXC_OFF_SYS_RESET
 696         li      r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
 697 4:
 698         bl      trap_reloc
 699         addi    r7, r7, 0x100           /* next exception vector */
 700         cmplw   0, r7, r8
 701         blt     4b
 702
 703         mfmsr   r3                      /* now that the vectors have */
 704         lis     r7, MSR_IP@h            /* relocated into low memory */
 705         ori     r7, r7, MSR_IP@l        /* MSR[IP] can be turned off */
 706         andc    r3, r3, r7              /* (if it was on) */
 707         SYNC                            /* Some chip revs need this... */
 708         mtmsr   r3
 709         SYNC
 710
 711         mtlr    r4                      /* restore link register    */
 712         blr