arch/powerpc/cpu/mpc512x/start.S

   1 /*
   2  * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   3  * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   4  * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
   5  * Copyright Freescale Semiconductor, Inc. 2004, 2006.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  *
  25  * Based on the MPC83xx code.
  26  */
  27
  28 /*
  29  *  U-Boot - Startup Code for MPC512x based Embedded Boards
  30  */
  31
  32 #include <config.h>
  33 #include <timestamp.h>
  34 #include <version.h>
  35
  36 #define CONFIG_521X     1               /* needed for Linux kernel header files*/
  37
  38 #include <asm/immap_512x.h>
  39 #include "asm-offsets.h"
  40
  41 #include <ppc_asm.tmpl>
  42 #include <ppc_defs.h>
  43
  44 #include <asm/cache.h>
  45 #include <asm/mmu.h>
  46
  47 #ifndef  CONFIG_IDENT_STRING
  48 #define  CONFIG_IDENT_STRING "MPC512X"
  49 #endif
  50
  51 /*
  52  * Floating Point enable, Machine Check and Recoverable Interr.
  53  */
  54 #undef  MSR_KERNEL
  55 #ifdef DEBUG
  56 #define MSR_KERNEL (MSR_FP|MSR_RI)
  57 #else
  58 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
  59 #endif
  60
  61 /* Macros for manipulating CSx_START/STOP */
  62 #define START_REG(start)        ((start) >> 16)
  63 #define STOP_REG(start, size)   (((start) + (size) - 1) >> 16)
  64
  65 /*
  66  * Set up GOT: Global Offset Table
  67  *
  68  * Use r12 to access the GOT
  69  */
  70         START_GOT
  71         GOT_ENTRY(_GOT2_TABLE_)
  72         GOT_ENTRY(_FIXUP_TABLE_)
  73
  74         GOT_ENTRY(_start)
  75         GOT_ENTRY(_start_of_vectors)
  76         GOT_ENTRY(_end_of_vectors)
  77         GOT_ENTRY(transfer_to_handler)
  78
  79         GOT_ENTRY(__init_end)
  80         GOT_ENTRY(_end)
  81         GOT_ENTRY(__bss_start)
  82         END_GOT
  83
  84 /*
  85  * Magic number and version string
  86  */
  87         .long   0x27051956              /* U-Boot Magic Number */
  88         .globl  version_string
  89 version_string:
  90         .ascii U_BOOT_VERSION
  91         .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
  92         .ascii " ", CONFIG_IDENT_STRING, "\0"
  93
  94 /*
  95  * Vector Table
  96  */
  97         .text
  98         . = EXC_OFF_SYS_RESET
  99
 100         .globl  _start
 101         /* Start from here after reset/power on */
 102 _start:
 103         li      r21, BOOTFLAG_COLD  /* Normal Power-On: Boot from FLASH */
 104         b       boot_cold
 105
 106         .globl  _start_of_vectors
 107 _start_of_vectors:
 108
 109 /* Machine check */
 110         STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 111
 112 /* Data Storage exception. */
 113         STD_EXCEPTION(0x300, DataStorage, UnknownException)
 114
 115 /* Instruction Storage exception. */
 116         STD_EXCEPTION(0x400, InstStorage, UnknownException)
 117
 118 /* External Interrupt exception. */
 119         STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
 120
 121 /* Alignment exception. */
 122         . = 0x600
 123 Alignment:
 124         EXCEPTION_PROLOG(SRR0, SRR1)
 125         mfspr   r4,DAR
 126         stw     r4,_DAR(r21)
 127         mfspr   r5,DSISR
 128         stw     r5,_DSISR(r21)
 129         addi    r3,r1,STACK_FRAME_OVERHEAD
 130         EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
 131
 132 /* Program check exception */
 133         . = 0x700
 134 ProgramCheck:
 135         EXCEPTION_PROLOG(SRR0, SRR1)
 136         addi    r3,r1,STACK_FRAME_OVERHEAD
 137         EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
 138                 MSR_KERNEL, COPY_EE)
 139
 140 /* Floating Point Unit unavailable exception */
 141         STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 142
 143 /* Decrementer */
 144         STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
 145
 146 /* Critical interrupt */
 147         STD_EXCEPTION(0xa00, Critical, UnknownException)
 148
 149 /* System Call */
 150         STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 151
 152 /* Trace interrupt */
 153         STD_EXCEPTION(0xd00, Trace, UnknownException)
 154
 155 /* Performance Monitor interrupt */
 156         STD_EXCEPTION(0xf00, PerfMon, UnknownException)
 157
 158 /* Intruction Translation Miss */
 159         STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
 160
 161 /* Data Load Translation Miss */
 162         STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
 163
 164 /* Data Store Translation Miss */
 165         STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
 166
 167 /* Instruction Address Breakpoint */
 168         STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
 169
 170 /* System Management interrupt */
 171         STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
 172
 173         .globl  _end_of_vectors
 174 _end_of_vectors:
 175
 176         . = 0x3000
 177 boot_cold:
 178         /* Save msr contents */
 179         mfmsr   r5
 180
 181         /* Set IMMR area to our preferred location */
 182         lis     r4, CONFIG_DEFAULT_IMMR@h
 183         lis     r3, CONFIG_SYS_IMMR@h
 184         ori     r3, r3, CONFIG_SYS_IMMR@l
 185         stw     r3, IMMRBAR(r4)
 186         mtspr   MBAR, r3                /* IMMRBAR is mirrored into the MBAR SPR (311) */
 187
 188         /* Initialise the machine */
 189         bl      cpu_early_init
 190
 191         /*
 192          * Set up Local Access Windows:
 193          *
 194          * 1) Boot/CS0 (boot FLASH)
 195          * 2) On-chip SRAM (initial stack purposes)
 196          */
 197
 198         /* Boot CS/CS0 window range */
 199         lis     r3, CONFIG_SYS_IMMR@h
 200         ori     r3, r3, CONFIG_SYS_IMMR@l
 201
 202         lis     r4, START_REG(CONFIG_SYS_FLASH_BASE)
 203         ori     r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
 204         stw     r4, LPCS0AW(r3)
 205
 206         /*
 207          * The SRAM window has a fixed size (256K), so only the start address
 208          * is necessary
 209          */
 210         lis     r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
 211         stw     r4, SRAMBAR(r3)
 212
 213         /*
 214          * According to MPC5121e RM, configuring local access windows should
 215          * be followed by a dummy read of the config register that was
 216          * modified last and an isync
 217          */
 218         lwz     r4, SRAMBAR(r3)
 219         isync
 220
 221         /*
 222          * Set configuration of the Boot/CS0, the SRAM window does not have a
 223          * config register so no params can be set for it
 224          */
 225         lis     r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
 226         ori     r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
 227
 228         lis     r4, CONFIG_SYS_CS0_CFG@h
 229         ori     r4, r4, CONFIG_SYS_CS0_CFG@l
 230         stw     r4, CS0_CONFIG(r3)
 231
 232         /* Master enable all CS's */
 233         lis     r4, CS_CTRL_ME@h
 234         ori     r4, r4, CS_CTRL_ME@l
 235         stw     r4, CS_CTRL(r3)
 236
 237         lis     r4, (CONFIG_SYS_MONITOR_BASE)@h
 238         ori     r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
 239         addi    r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
 240         mtlr    r5
 241         blr
 242
 243 in_flash:
 244         lis     r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
 245         ori     r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
 246
 247         li      r0, 0           /* Make room for stack frame header and */
 248         stwu    r0, -4(r1)      /* clear final stack frame so that      */
 249         stwu    r0, -4(r1)      /* stack backtraces terminate cleanly   */
 250
 251         /* let the C-code set up the rest                       */
 252         /*                                                      */
 253         /* Be careful to keep code relocatable & stack humble   */
 254         /*------------------------------------------------------*/
 255
 256         GET_GOT                 /* initialize GOT access        */
 257
 258         /* r3: IMMR */
 259         lis     r3, CONFIG_SYS_IMMR@h
 260         /* run low-level CPU init code (in Flash) */
 261         bl      cpu_init_f
 262
 263         /* r3: BOOTFLAG */
 264         mr      r3, r21
 265         /* run 1st part of board init code (in Flash) */
 266         bl      board_init_f
 267
 268         /* NOTREACHED - board_init_f() does not return */
 269
 270 /*
 271  * This code finishes saving the registers to the exception frame
 272  * and jumps to the appropriate handler for the exception.
 273  * Register r21 is pointer into trap frame, r1 has new stack pointer.
 274  */
 275         .globl  transfer_to_handler
 276 transfer_to_handler:
 277         stw     r22,_NIP(r21)
 278         lis     r22,MSR_POW@h
 279         andc    r23,r23,r22
 280         stw     r23,_MSR(r21)
 281         SAVE_GPR(7, r21)
 282         SAVE_4GPRS(8, r21)
 283         SAVE_8GPRS(12, r21)
 284         SAVE_8GPRS(24, r21)
 285         mflr    r23
 286         andi.   r24,r23,0x3f00          /* get vector offset */
 287         stw     r24,TRAP(r21)
 288         li      r22,0
 289         stw     r22,RESULT(r21)
 290         lwz     r24,0(r23)              /* virtual address of handler */
 291         lwz     r23,4(r23)              /* where to go when done */
 292         mtspr   SRR0,r24
 293         mtspr   SRR1,r20
 294         mtlr    r23
 295         SYNC
 296         rfi                             /* jump to handler, enable MMU */
 297
 298 int_return:
 299         mfmsr   r28             /* Disable interrupts */
 300         li      r4,0
 301         ori     r4,r4,MSR_EE
 302         andc    r28,r28,r4
 303         SYNC                    /* Some chip revs need this... */
 304         mtmsr   r28
 305         SYNC
 306         lwz     r2,_CTR(r1)
 307         lwz     r0,_LINK(r1)
 308         mtctr   r2
 309         mtlr    r0
 310         lwz     r2,_XER(r1)
 311         lwz     r0,_CCR(r1)
 312         mtspr   XER,r2
 313         mtcrf   0xFF,r0
 314         REST_10GPRS(3, r1)
 315         REST_10GPRS(13, r1)
 316         REST_8GPRS(23, r1)
 317         REST_GPR(31, r1)
 318         lwz     r2,_NIP(r1)     /* Restore environment */
 319         lwz     r0,_MSR(r1)
 320         mtspr   SRR0,r2
 321         mtspr   SRR1,r0
 322         lwz     r0,GPR0(r1)
 323         lwz     r2,GPR2(r1)
 324         lwz     r1,GPR1(r1)
 325         SYNC
 326         rfi
 327
 328 /*
 329  * This code initialises the machine, it expects original MSR contents to be in r5.
 330  */
 331 cpu_early_init:
 332         /* Initialize machine status; enable machine check interrupt */
 333         /*-----------------------------------------------------------*/
 334
 335         li      r3, MSR_KERNEL                  /* Set ME and RI flags */
 336         rlwimi  r3, r5, 0, 25, 25               /* preserve IP bit */
 337 #ifdef DEBUG
 338         rlwimi  r3, r5, 0, 21, 22               /* debugger might set SE, BE bits */
 339 #endif
 340         mtmsr   r3
 341         SYNC
 342         mtspr   SRR1, r3                        /* Mirror current MSR state in SRR1 */
 343
 344         lis     r3, CONFIG_SYS_IMMR@h
 345
 346 #if defined(CONFIG_WATCHDOG)
 347         /* Initialise the watchdog and reset it */
 348         /*--------------------------------------*/
 349         lis r4, CONFIG_SYS_WATCHDOG_VALUE
 350         ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
 351         stw r4, SWCRR(r3)
 352
 353         /* reset */
 354         li      r4, 0x556C
 355         sth     r4, SWSRR@l(r3)
 356         li      r4, 0x0
 357         ori     r4, r4, 0xAA39
 358         sth     r4, SWSRR@l(r3)
 359 #else
 360         /* Disable the watchdog */
 361         /*----------------------*/
 362         lwz r4, SWCRR(r3)
 363         /*
 364          * Check to see if it's enabled for disabling: once disabled by s/w
 365          * it's not possible to re-enable it
 366          */
 367         andi. r4, r4, 0x4
 368         beq 1f
 369         xor r4, r4, r4
 370         stw r4, SWCRR(r3)
 371 1:
 372 #endif /* CONFIG_WATCHDOG */
 373
 374         /* Initialize the Hardware Implementation-dependent Registers */
 375         /* HID0 also contains cache control                     */
 376         /*------------------------------------------------------*/
 377         lis     r3, CONFIG_SYS_HID0_INIT@h
 378         ori     r3, r3, CONFIG_SYS_HID0_INIT@l
 379         SYNC
 380         mtspr   HID0, r3
 381
 382         lis     r3, CONFIG_SYS_HID0_FINAL@h
 383         ori     r3, r3, CONFIG_SYS_HID0_FINAL@l
 384         SYNC
 385         mtspr   HID0, r3
 386
 387         lis     r3, CONFIG_SYS_HID2@h
 388         ori     r3, r3, CONFIG_SYS_HID2@l
 389         SYNC
 390         mtspr   HID2, r3
 391         sync
 392         blr
 393
 394
 395 /* Cache functions.
 396  *
 397  * Note: requires that all cache bits in
 398  * HID0 are in the low half word.
 399  */
 400         .globl  icache_enable
 401 icache_enable:
 402         mfspr   r3, HID0
 403         ori     r3, r3, HID0_ICE
 404         lis     r4, 0
 405         ori     r4, r4, HID0_ILOCK
 406         andc    r3, r3, r4
 407         ori     r4, r3, HID0_ICFI
 408         isync
 409         mtspr   HID0, r4    /* sets enable and invalidate, clears lock */
 410         isync
 411         mtspr   HID0, r3        /* clears invalidate */
 412         blr
 413
 414         .globl  icache_disable
 415 icache_disable:
 416         mfspr   r3, HID0
 417         lis     r4, 0
 418         ori     r4, r4, HID0_ICE|HID0_ILOCK
 419         andc    r3, r3, r4
 420         ori     r4, r3, HID0_ICFI
 421         isync
 422         mtspr   HID0, r4     /* sets invalidate, clears enable and lock*/
 423         isync
 424         mtspr   HID0, r3        /* clears invalidate */
 425         blr
 426
 427         .globl  icache_status
 428 icache_status:
 429         mfspr   r3, HID0
 430         rlwinm  r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
 431         blr
 432
 433         .globl  dcache_enable
 434 dcache_enable:
 435         mfspr   r3, HID0
 436         li      r5, HID0_DCFI|HID0_DLOCK
 437         andc    r3, r3, r5
 438         mtspr   HID0, r3                /* no invalidate, unlock */
 439         ori     r3, r3, HID0_DCE
 440         ori     r5, r3, HID0_DCFI
 441         mtspr   HID0, r5                /* enable + invalidate */
 442         mtspr   HID0, r3                /* enable */
 443         sync
 444         blr
 445
 446         .globl  dcache_disable
 447 dcache_disable:
 448         mfspr   r3, HID0
 449         lis     r4, 0
 450         ori     r4, r4, HID0_DCE|HID0_DLOCK
 451         andc    r3, r3, r4
 452         ori     r4, r3, HID0_DCI
 453         sync
 454         mtspr   HID0, r4        /* sets invalidate, clears enable and lock */
 455         sync
 456         mtspr   HID0, r3        /* clears invalidate */
 457         blr
 458
 459         .globl  dcache_status
 460 dcache_status:
 461         mfspr   r3, HID0
 462         rlwinm  r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
 463         blr
 464
 465         .globl get_pvr
 466 get_pvr:
 467         mfspr   r3, PVR
 468         blr
 469
 470 /*-------------------------------------------------------------------*/
 471
 472 /*
 473  * void relocate_code (addr_sp, gd, addr_moni)
 474  *
 475  * This "function" does not return, instead it continues in RAM
 476  * after relocating the monitor code.
 477  *
 478  * r3 = dest
 479  * r4 = src
 480  * r5 = length in bytes
 481  * r6 = cachelinesize
 482  */
 483         .globl  relocate_code
 484 relocate_code:
 485         mr      r1,  r3         /* Set new stack pointer        */
 486         mr      r9,  r4         /* Save copy of Global Data pointer */
 487         mr      r10, r5         /* Save copy of Destination Address */
 488
 489         GET_GOT
 490         mr      r3,  r5                         /* Destination Address */
 491         lis     r4, CONFIG_SYS_MONITOR_BASE@h           /* Source      Address */
 492         ori     r4, r4, CONFIG_SYS_MONITOR_BASE@l
 493         lwz     r5, GOT(__init_end)
 494         sub     r5, r5, r4
 495         li      r6, CONFIG_SYS_CACHELINE_SIZE           /* Cache Line Size */
 496
 497         /*
 498          * Fix GOT pointer:
 499          *
 500          * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
 501          *              + Destination Address
 502          *
 503          * Offset:
 504          */
 505         sub     r15, r10, r4
 506
 507         /* First our own GOT */
 508         add     r12, r12, r15
 509         /* then the one used by the C code */
 510         add     r30, r30, r15
 511
 512         /*
 513          * Now relocate code
 514          */
 515         cmplw   cr1,r3,r4
 516         addi    r0,r5,3
 517         srwi.   r0,r0,2
 518         beq     cr1,4f          /* In place copy is not necessary */
 519         beq     7f              /* Protect against 0 count        */
 520         mtctr   r0
 521         bge     cr1,2f
 522         la      r8,-4(r4)
 523         la      r7,-4(r3)
 524
 525         /* copy */
 526 1:      lwzu    r0,4(r8)
 527         stwu    r0,4(r7)
 528         bdnz    1b
 529
 530         addi    r0,r5,3
 531         srwi.   r0,r0,2
 532         mtctr   r0
 533         la      r8,-4(r4)
 534         la      r7,-4(r3)
 535
 536         /* and compare */
 537 20:     lwzu    r20,4(r8)
 538         lwzu    r21,4(r7)
 539         xor. r22, r20, r21
 540         bne  30f
 541         bdnz    20b
 542         b 4f
 543
 544         /* compare failed */
 545 30:     li r3, 0
 546         blr
 547
 548 2:      slwi    r0,r0,2 /* re copy in reverse order ... y do we needed it? */
 549         add     r8,r4,r0
 550         add     r7,r3,r0
 551 3:      lwzu    r0,-4(r8)
 552         stwu    r0,-4(r7)
 553         bdnz    3b
 554
 555 /*
 556  * Now flush the cache: note that we must start from a cache aligned
 557  * address. Otherwise we might miss one cache line.
 558  */
 559 4:      cmpwi   r6,0
 560         add     r5,r3,r5
 561         beq     7f              /* Always flush prefetch queue in any case */
 562         subi    r0,r6,1
 563         andc    r3,r3,r0
 564         mr      r4,r3
 565 5:      dcbst   0,r4
 566         add     r4,r4,r6
 567         cmplw   r4,r5
 568         blt     5b
 569         sync                    /* Wait for all dcbst to complete on bus */
 570         mr      r4,r3
 571 6:      icbi    0,r4
 572         add     r4,r4,r6
 573         cmplw   r4,r5
 574         blt     6b
 575 7:      sync                    /* Wait for all icbi to complete on bus */
 576         isync
 577
 578 /*
 579  * We are done. Do not return, instead branch to second part of board
 580  * initialization, now running from RAM.
 581  */
 582         addi    r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
 583         mtlr    r0
 584         blr
 585
 586 in_ram:
 587         /*
 588          * Relocation Function, r12 point to got2+0x8000
 589          *
 590          * Adjust got2 pointers, no need to check for 0, this code
 591          * already puts a few entries in the table.
 592          */
 593         li      r0,__got2_entries@sectoff@l
 594         la      r3,GOT(_GOT2_TABLE_)
 595         lwz     r11,GOT(_GOT2_TABLE_)
 596         mtctr   r0
 597         sub     r11,r3,r11
 598         addi    r3,r3,-4
 599 1:      lwzu    r0,4(r3)
 600         cmpwi   r0,0
 601         beq-    2f
 602         add     r0,r0,r11
 603         stw     r0,0(r3)
 604 2:      bdnz    1b
 605
 606         /*
 607          * Now adjust the fixups and the pointers to the fixups
 608          * in case we need to move ourselves again.
 609          */
 610         li      r0,__fixup_entries@sectoff@l
 611         lwz     r3,GOT(_FIXUP_TABLE_)
 612         cmpwi   r0,0
 613         mtctr   r0
 614         addi    r3,r3,-4
 615         beq     4f
 616 3:      lwzu    r4,4(r3)
 617         lwzux   r0,r4,r11
 618         add     r0,r0,r11
 619         stw     r10,0(r3)
 620         stw     r0,0(r4)
 621         bdnz    3b
 622 4:
 623 clear_bss:
 624         /*
 625          * Now clear BSS segment
 626          */
 627         lwz     r3,GOT(__bss_start)
 628         lwz     r4,GOT(_end)
 629
 630         cmplw   0, r3, r4
 631         beq     6f
 632
 633         li      r0, 0
 634 5:
 635         stw     r0, 0(r3)
 636         addi    r3, r3, 4
 637         cmplw   0, r3, r4
 638         bne     5b
 639 6:
 640         mr      r3, r9          /* Global Data pointer          */
 641         mr      r4, r10         /* Destination Address          */
 642         bl      board_init_r
 643
 644         /*
 645          * Copy exception vector code to low memory
 646          *
 647          * r3: dest_addr
 648          * r7: source address, r8: end address, r9: target address
 649          */
 650         .globl  trap_init
 651 trap_init:
 652         mflr    r4              /* save link register */
 653         GET_GOT
 654         lwz     r7, GOT(_start)
 655         lwz     r8, GOT(_end_of_vectors)
 656
 657         li      r9, 0x100       /* reset vector at 0x100 */
 658
 659         cmplw   0, r7, r8
 660         bgelr                   /* return if r7>=r8 - just in case */
 661 1:
 662         lwz     r0, 0(r7)
 663         stw     r0, 0(r9)
 664         addi    r7, r7, 4
 665         addi    r9, r9, 4
 666         cmplw   0, r7, r8
 667         bne     1b
 668
 669         /*
 670          * relocate `hdlr' and `int_return' entries
 671          */
 672         li      r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
 673         li      r8, Alignment - _start + EXC_OFF_SYS_RESET
 674 2:
 675         bl      trap_reloc
 676         addi    r7, r7, 0x100           /* next exception vector */
 677         cmplw   0, r7, r8
 678         blt     2b
 679
 680         li      r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
 681         bl      trap_reloc
 682
 683         li      r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
 684         bl      trap_reloc
 685
 686         li      r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
 687         li      r8, SystemCall - _start + EXC_OFF_SYS_RESET
 688 3:
 689         bl      trap_reloc
 690         addi    r7, r7, 0x100           /* next exception vector */
 691         cmplw   0, r7, r8
 692         blt     3b
 693
 694         li      r7, .L_Trace - _start + EXC_OFF_SYS_RESET
 695         li      r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
 696 4:
 697         bl      trap_reloc
 698         addi    r7, r7, 0x100           /* next exception vector */
 699         cmplw   0, r7, r8
 700         blt     4b
 701
 702         mfmsr   r3                      /* now that the vectors have */
 703         lis     r7, MSR_IP@h            /* relocated into low memory */
 704         ori     r7, r7, MSR_IP@l        /* MSR[IP] can be turned off */
 705         andc    r3, r3, r7              /* (if it was on) */
 706         SYNC                            /* Some chip revs need this... */
 707         mtmsr   r3
 708         SYNC
 709
 710         mtlr    r4                      /* restore link register    */
 711         blr