arch/powerpc/cpu/mpc5xx/start.S

   1 /*
   2  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   3  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   4  *  Copyright (C) 2000, 2001, 2002 Wolfgang Denk <wd@denx.de>
   5  *  Copyright (C) 2003  Martin Winistoerfer, martinwinistoerfer@gmx.ch.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /*
  27  * File:                start.S
  28  *
  29  * Discription:         startup code
  30  *
  31  */
  32
  33 #include <asm-offsets.h>
  34 #include <config.h>
  35 #include <mpc5xx.h>
  36 #include <timestamp.h>
  37 #include <version.h>
  38
  39 #define CONFIG_5xx 1            /* needed for Linux kernel header files */
  40 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  41
  42 #include <ppc_asm.tmpl>
  43 #include <ppc_defs.h>
  44
  45 #include <linux/config.h>
  46 #include <asm/processor.h>
  47 #include <asm/u-boot.h>
  48
  49 #ifndef  CONFIG_IDENT_STRING
  50 #define  CONFIG_IDENT_STRING ""
  51 #endif
  52
  53 /* We don't have a MMU.
  54 */
  55 #undef  MSR_KERNEL
  56 #define MSR_KERNEL ( MSR_ME | MSR_RI )          /* Machine Check and Recoverable Interr. */
  57
  58 /*
  59  * Set up GOT: Global Offset Table
  60  *
  61  * Use r12 to access the GOT
  62  */
  63         START_GOT
  64         GOT_ENTRY(_GOT2_TABLE_)
  65         GOT_ENTRY(_FIXUP_TABLE_)
  66
  67         GOT_ENTRY(_start)
  68         GOT_ENTRY(_start_of_vectors)
  69         GOT_ENTRY(_end_of_vectors)
  70         GOT_ENTRY(transfer_to_handler)
  71
  72         GOT_ENTRY(__init_end)
  73         GOT_ENTRY(__bss_end__)
  74         GOT_ENTRY(__bss_start)
  75         END_GOT
  76
  77 /*
  78  * r3 - 1st arg to board_init(): IMMP pointer
  79  * r4 - 2nd arg to board_init(): boot flag
  80  */
  81         .text
  82         .long   0x27051956                      /* U-Boot Magic Number */
  83         .globl  version_string
  84 version_string:
  85         .ascii U_BOOT_VERSION
  86         .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
  87         .ascii CONFIG_IDENT_STRING, "\0"
  88
  89         . = EXC_OFF_SYS_RESET
  90         .globl  _start
  91 _start:
  92         mfspr   r3, 638
  93         li      r4, CONFIG_SYS_ISB                      /* Set ISB bit */
  94         or      r3, r3, r4
  95         mtspr   638, r3
  96
  97         /* Initialize machine status; enable machine check interrupt            */
  98         /*----------------------------------------------------------------------*/
  99         li      r3, MSR_KERNEL                  /* Set ME, RI flags */
 100         mtmsr   r3
 101         mtspr   SRR1, r3                        /* Make SRR1 match MSR */
 102
 103         /* Initialize debug port registers                                      */
 104         /*----------------------------------------------------------------------*/
 105         xor     r0, r0, r0                      /* Clear R0 */
 106         mtspr   LCTRL1, r0                      /* Initialize debug port regs */
 107         mtspr   LCTRL2, r0
 108         mtspr   COUNTA, r0
 109         mtspr   COUNTB, r0
 110
 111 #if defined(CONFIG_PATI)
 112         /* the external flash access on PATI fails if programming the PLL to 40MHz.
 113          * Copy the PLL programming code to the internal RAM and execute it
 114          *----------------------------------------------------------------------*/
 115         lis     r3, CONFIG_SYS_MONITOR_BASE@h
 116         ori     r3, r3, CONFIG_SYS_MONITOR_BASE@l
 117         addi    r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET
 118
 119         lis     r4, CONFIG_SYS_INIT_RAM_ADDR@h
 120         ori     r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l
 121         mtlr    r4
 122         addis   r5,0,0x0
 123         ori     r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2)
 124         mtctr   r5
 125         addi    r3, r3, -4
 126         addi    r4, r4, -4
 127 0:
 128         lwzu    r0,4(r3)
 129         stwu    r0,4(r4)
 130         bdnz    0b                /* copy loop */
 131         blrl
 132 #endif
 133
 134         /*
 135          * Calculate absolute address in FLASH and jump there
 136          *----------------------------------------------------------------------*/
 137
 138         lis     r3, CONFIG_SYS_MONITOR_BASE@h
 139         ori     r3, r3, CONFIG_SYS_MONITOR_BASE@l
 140         addi    r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
 141         mtlr    r3
 142         blr
 143
 144 in_flash:
 145
 146         /* Initialize some SPRs that are hard to access from C                  */
 147         /*----------------------------------------------------------------------*/
 148
 149         lis     r3, CONFIG_SYS_IMMR@h                   /* Pass IMMR as arg1 to C routine */
 150         lis     r2, CONFIG_SYS_INIT_SP_ADDR@h
 151         ori     r1, r2, CONFIG_SYS_INIT_SP_ADDR@l       /* Set up the stack in internal SRAM */
 152         /* Note: R0 is still 0 here */
 153         stwu    r0, -4(r1)                      /* Clear final stack frame so that      */
 154         stwu    r0, -4(r1)                      /* stack backtraces terminate cleanly   */
 155
 156         /*
 157          * Disable serialized ifetch and show cycles
 158          * (i.e. set processor to normal mode) for maximum
 159          * performance.
 160          */
 161
 162         li      r2, 0x0007
 163         mtspr   ICTRL, r2
 164
 165         /* Set up debug mode entry */
 166
 167         lis     r2, CONFIG_SYS_DER@h
 168         ori     r2, r2, CONFIG_SYS_DER@l
 169         mtspr   DER, r2
 170
 171         /* Let the C-code set up the rest                                       */
 172         /*                                                                      */
 173         /* Be careful to keep code relocatable !                                */
 174         /*----------------------------------------------------------------------*/
 175
 176         GET_GOT                 /* initialize GOT access                        */
 177 #if defined(__pic__) && __pic__ == 1
 178         /* Needed for upcoming -msingle-pic-base */
 179         bl      _GLOBAL_OFFSET_TABLE_@local-4
 180         mflr    r30
 181 #endif
 182         /* r3: IMMR */
 183         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 184
 185         bl      board_init_f    /* run 1st part of board init code (from Flash) */
 186
 187         /* NOTREACHED - board_init_f() does not return */
 188
 189
 190         .globl  _start_of_vectors
 191 _start_of_vectors:
 192
 193 /* Machine check */
 194         STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 195
 196 /* Data Storage exception.  "Never" generated on the 860. */
 197         STD_EXCEPTION(0x300, DataStorage, UnknownException)
 198
 199 /* Instruction Storage exception.  "Never" generated on the 860. */
 200         STD_EXCEPTION(0x400, InstStorage, UnknownException)
 201
 202 /* External Interrupt exception. */
 203         STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
 204
 205 /* Alignment exception. */
 206         . = 0x600
 207 Alignment:
 208         EXCEPTION_PROLOG(SRR0, SRR1)
 209         mfspr   r4,DAR
 210         stw     r4,_DAR(r21)
 211         mfspr   r5,DSISR
 212         stw     r5,_DSISR(r21)
 213         addi    r3,r1,STACK_FRAME_OVERHEAD
 214         EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
 215
 216 /* Program check exception */
 217         . = 0x700
 218 ProgramCheck:
 219         EXCEPTION_PROLOG(SRR0, SRR1)
 220         addi    r3,r1,STACK_FRAME_OVERHEAD
 221         EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
 222                 MSR_KERNEL, COPY_EE)
 223
 224         /* FPU on MPC5xx available. We will use it later.
 225         */
 226         STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 227
 228         /* I guess we could implement decrementer, and may have
 229          * to someday for timekeeping.
 230          */
 231         STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
 232         STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
 233         STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
 234         STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 235         STD_EXCEPTION(0xd00, SingleStep, UnknownException)
 236
 237         STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
 238         STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
 239
 240         /* On the MPC8xx, this is a software emulation interrupt.  It occurs
 241          * for all unimplemented and illegal instructions.
 242          */
 243         STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
 244         STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
 245         STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
 246         STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
 247         STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
 248
 249         STD_EXCEPTION(0x1500, Reserved5, UnknownException)
 250         STD_EXCEPTION(0x1600, Reserved6, UnknownException)
 251         STD_EXCEPTION(0x1700, Reserved7, UnknownException)
 252         STD_EXCEPTION(0x1800, Reserved8, UnknownException)
 253         STD_EXCEPTION(0x1900, Reserved9, UnknownException)
 254         STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
 255         STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
 256
 257         STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
 258         STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
 259         STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
 260         STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
 261
 262
 263         .globl  _end_of_vectors
 264 _end_of_vectors:
 265
 266
 267         . = 0x2000
 268
 269 /*
 270  * This code finishes saving the registers to the exception frame
 271  * and jumps to the appropriate handler for the exception.
 272  * Register r21 is pointer into trap frame, r1 has new stack pointer.
 273  */
 274         .globl  transfer_to_handler
 275 transfer_to_handler:
 276         stw     r22,_NIP(r21)
 277         lis     r22,MSR_POW@h
 278         andc    r23,r23,r22
 279         stw     r23,_MSR(r21)
 280         SAVE_GPR(7, r21)
 281         SAVE_4GPRS(8, r21)
 282         SAVE_8GPRS(12, r21)
 283         SAVE_8GPRS(24, r21)
 284         mflr    r23
 285         andi.   r24,r23,0x3f00          /* get vector offset */
 286         stw     r24,TRAP(r21)
 287         li      r22,0
 288         stw     r22,RESULT(r21)
 289         mtspr   SPRG2,r22               /* r1 is now kernel sp */
 290         lwz     r24,0(r23)              /* virtual address of handler */
 291         lwz     r23,4(r23)              /* where to go when done */
 292         mtspr   SRR0,r24
 293         mtspr   SRR1,r20
 294         mtlr    r23
 295         SYNC
 296         rfi                             /* jump to handler, enable MMU */
 297
 298 int_return:
 299         mfmsr   r28                     /* Disable interrupts */
 300         li      r4,0
 301         ori     r4,r4,MSR_EE
 302         andc    r28,r28,r4
 303         SYNC                            /* Some chip revs need this... */
 304         mtmsr   r28
 305         SYNC
 306         lwz     r2,_CTR(r1)
 307         lwz     r0,_LINK(r1)
 308         mtctr   r2
 309         mtlr    r0
 310         lwz     r2,_XER(r1)
 311         lwz     r0,_CCR(r1)
 312         mtspr   XER,r2
 313         mtcrf   0xFF,r0
 314         REST_10GPRS(3, r1)
 315         REST_10GPRS(13, r1)
 316         REST_8GPRS(23, r1)
 317         REST_GPR(31, r1)
 318         lwz     r2,_NIP(r1)             /* Restore environment */
 319         lwz     r0,_MSR(r1)
 320         mtspr   SRR0,r2
 321         mtspr   SRR1,r0
 322         lwz     r0,GPR0(r1)
 323         lwz     r2,GPR2(r1)
 324         lwz     r1,GPR1(r1)
 325         SYNC
 326         rfi
 327
 328
 329 /*
 330  * unsigned int get_immr (unsigned int mask)
 331  *
 332  * return (mask ? (IMMR & mask) : IMMR);
 333  */
 334         .globl  get_immr
 335 get_immr:
 336         mr      r4,r3           /* save mask */
 337         mfspr   r3, IMMR        /* IMMR */
 338         cmpwi   0,r4,0          /* mask != 0 ? */
 339         beq     4f
 340         and     r3,r3,r4        /* IMMR & mask */
 341 4:
 342         blr
 343
 344         .globl get_pvr
 345 get_pvr:
 346         mfspr   r3, PVR
 347         blr
 348
 349
 350 /*------------------------------------------------------------------------------*/
 351
 352 /*
 353  * void relocate_code (addr_sp, gd, addr_moni)
 354  *
 355  * This "function" does not return, instead it continues in RAM
 356  * after relocating the monitor code.
 357  *
 358  * r3 = dest
 359  * r4 = src
 360  * r5 = length in bytes
 361  * r6 = cachelinesize
 362  */
 363         .globl  relocate_code
 364 relocate_code:
 365         mr      r1,  r3         /* Set new stack pointer in SRAM        */
 366         mr      r9,  r4         /* Save copy of global data pointer in SRAM */
 367         mr      r10, r5         /* Save copy of monitor destination Address in SRAM */
 368
 369         GET_GOT
 370 #if defined(__pic__) && __pic__ == 1
 371         /* Needed for upcoming -msingle-pic-base */
 372         bl      _GLOBAL_OFFSET_TABLE_@local-4
 373         mflr    r30
 374 #endif
 375         mr      r3,  r5                         /* Destination Address  */
 376         lis     r4, CONFIG_SYS_MONITOR_BASE@h           /* Source      Address  */
 377         ori     r4, r4, CONFIG_SYS_MONITOR_BASE@l
 378         lwz     r5, GOT(__init_end)
 379         sub     r5, r5, r4
 380
 381         /*
 382          * Fix GOT pointer:
 383          *
 384          * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
 385          *
 386          * Offset:
 387          */
 388         sub     r15, r10, r4
 389
 390         /* First our own GOT */
 391         add     r12, r12, r15
 392         /* the the one used by the C code */
 393         add     r30, r30, r15
 394
 395         /*
 396          * Now relocate code
 397          */
 398
 399         cmplw   cr1,r3,r4
 400         addi    r0,r5,3
 401         srwi.   r0,r0,2
 402         beq     cr1,4f          /* In place copy is not necessary       */
 403         beq     4f              /* Protect against 0 count              */
 404         mtctr   r0
 405         bge     cr1,2f
 406
 407         la      r8,-4(r4)
 408         la      r7,-4(r3)
 409 1:      lwzu    r0,4(r8)
 410         stwu    r0,4(r7)
 411         bdnz    1b
 412         b       4f
 413
 414 2:      slwi    r0,r0,2
 415         add     r8,r4,r0
 416         add     r7,r3,r0
 417 3:      lwzu    r0,-4(r8)
 418         stwu    r0,-4(r7)
 419         bdnz    3b
 420
 421 4:      sync
 422         isync
 423
 424 /*
 425  * We are done. Do not return, instead branch to second part of board
 426  * initialization, now running from RAM.
 427  */
 428
 429         addi    r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
 430         mtlr    r0
 431         blr
 432
 433 in_ram:
 434
 435         /*
 436          * Relocation Function, r12 point to got2+0x8000
 437          *
 438          * Adjust got2 pointers, no need to check for 0, this code
 439          * already puts a few entries in the table.
 440          */
 441         li      r0,__got2_entries@sectoff@l
 442         la      r3,GOT(_GOT2_TABLE_)
 443         lwz     r11,GOT(_GOT2_TABLE_)
 444         mtctr   r0
 445         sub     r11,r3,r11
 446         addi    r3,r3,-4
 447 1:      lwzu    r0,4(r3)
 448         cmpwi   r0,0
 449         beq-    2f
 450         add     r0,r0,r11
 451         stw     r0,0(r3)
 452 2:      bdnz    1b
 453
 454         /*
 455          * Now adjust the fixups and the pointers to the fixups
 456          * in case we need to move ourselves again.
 457          */
 458         li      r0,__fixup_entries@sectoff@l
 459         lwz     r3,GOT(_FIXUP_TABLE_)
 460         cmpwi   r0,0
 461         mtctr   r0
 462         addi    r3,r3,-4
 463         beq     4f
 464 3:      lwzu    r4,4(r3)
 465         lwzux   r0,r4,r11
 466         cmpwi   r0,0
 467         add     r0,r0,r11
 468         stw     r4,0(r3)
 469         beq-    5f
 470         stw     r0,0(r4)
 471 5:      bdnz    3b
 472 4:
 473 clear_bss:
 474         /*
 475          * Now clear BSS segment
 476          */
 477         lwz     r3,GOT(__bss_start)
 478         lwz     r4,GOT(__bss_end__)
 479         cmplw   0, r3, r4
 480         beq     6f
 481
 482         li      r0, 0
 483 5:
 484         stw     r0, 0(r3)
 485         addi    r3, r3, 4
 486         cmplw   0, r3, r4
 487         bne     5b
 488 6:
 489
 490         mr      r3, r9          /* Global Data pointer          */
 491         mr      r4, r10         /* Destination Address          */
 492         bl      board_init_r
 493
 494         /*
 495          * Copy exception vector code to low memory
 496          *
 497          * r3: dest_addr
 498          * r7: source address, r8: end address, r9: target address
 499          */
 500         .globl  trap_init
 501 trap_init:
 502         mflr    r4                      /* save link register           */
 503         GET_GOT
 504         lwz     r7, GOT(_start)
 505         lwz     r8, GOT(_end_of_vectors)
 506
 507         li      r9, 0x100               /* reset vector always at 0x100 */
 508
 509         cmplw   0, r7, r8
 510         bgelr                           /* return if r7>=r8 - just in case */
 511 1:
 512         lwz     r0, 0(r7)
 513         stw     r0, 0(r9)
 514         addi    r7, r7, 4
 515         addi    r9, r9, 4
 516         cmplw   0, r7, r8
 517         bne     1b
 518
 519         /*
 520          * relocate `hdlr' and `int_return' entries
 521          */
 522         li      r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
 523         li      r8, Alignment - _start + EXC_OFF_SYS_RESET
 524 2:
 525         bl      trap_reloc
 526         addi    r7, r7, 0x100           /* next exception vector        */
 527         cmplw   0, r7, r8
 528         blt     2b
 529
 530         li      r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
 531         bl      trap_reloc
 532
 533         li      r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
 534         bl      trap_reloc
 535
 536         li      r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
 537         li      r8, SystemCall - _start + EXC_OFF_SYS_RESET
 538 3:
 539         bl      trap_reloc
 540         addi    r7, r7, 0x100           /* next exception vector        */
 541         cmplw   0, r7, r8
 542         blt     3b
 543
 544         li      r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
 545         li      r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
 546 4:
 547         bl      trap_reloc
 548         addi    r7, r7, 0x100           /* next exception vector        */
 549         cmplw   0, r7, r8
 550         blt     4b
 551
 552         mtlr    r4                      /* restore link register        */
 553         blr
 554
 555 #if defined(CONFIG_PATI)
 556 /* Program the PLL */
 557 pll_prog_code_start:
 558         lis     r4, (CONFIG_SYS_IMMR + 0x002fc384)@h
 559         ori     r4, r4, (CONFIG_SYS_IMMR + 0x002fc384)@l
 560         lis     r3, (0x55ccaa33)@h
 561         ori     r3, r3, (0x55ccaa33)@l
 562         stw     r3, 0(r4)
 563         lis     r4, (CONFIG_SYS_IMMR + 0x002fc284)@h
 564         ori     r4, r4, (CONFIG_SYS_IMMR + 0x002fc284)@l
 565         lis     r3, CONFIG_SYS_PLPRCR@h
 566         ori     r3, r3, CONFIG_SYS_PLPRCR@l
 567         stw     r3, 0(r4)
 568         addis   r3,0,0x0
 569         ori     r3,r3,0xA000
 570         mtctr   r3
 571 ..spinlp:
 572   bdnz    ..spinlp                /* spin loop */
 573         blr
 574 pll_prog_code_end:
 575         nop
 576         blr
 577 #endif