arch/powerpc/cpu/mpc8260/cpu.c

   1 /*
   2  * (C) Copyright 2000-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
  10  *
  11  * written or collected and sometimes rewritten by
  12  * Magnus Damm <damm@bitsmart.com>
  13  *
  14  * modified by
  15  * Wolfgang Denk <wd@denx.de>
  16  *
  17  * modified for 8260 by
  18  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
  19  *
  20  * added 8260 masks by
  21  * Marius Groeger <mag@sysgo.de>
  22  *
  23  * added HiP7 (824x/827x/8280) processors support by
  24  * Yuli Barcohen <yuli@arabellasw.com>
  25  */
  26
  27 #include <common.h>
  28 #include <watchdog.h>
  29 #include <command.h>
  30 #include <mpc8260.h>
  31 #include <netdev.h>
  32 #include <asm/processor.h>
  33 #include <asm/cpm_8260.h>
  34
  35 #if defined(CONFIG_OF_LIBFDT)
  36 #include <libfdt.h>
  37 #include <fdt_support.h>
  38 #endif
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 #if defined(CONFIG_GET_CPU_STR_F)
  43 extern int get_cpu_str_f (char *buf);
  44 #endif
  45
  46 int checkcpu (void)
  47 {
  48         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  49         ulong clock = gd->cpu_clk;
  50         uint pvr = get_pvr ();
  51         uint immr, rev, m, k;
  52         char buf[32];
  53
  54         puts ("CPU:   ");
  55
  56         switch (pvr) {
  57         case PVR_8260:
  58         case PVR_8260_HIP3:
  59                 k = 3;
  60                 break;
  61         case PVR_8260_HIP4:
  62                 k = 4;
  63                 break;
  64         case PVR_8260_HIP7R1:
  65         case PVR_8260_HIP7RA:
  66         case PVR_8260_HIP7:
  67                 k = 7;
  68                 break;
  69         default:
  70                 return -1;      /* whoops! not an MPC8260 */
  71         }
  72         rev = pvr & 0xff;
  73
  74         immr = immap->im_memctl.memc_immr;
  75         if ((immr & IMMR_ISB_MSK) != CONFIG_SYS_IMMR)
  76                 return -1;      /* whoops! someone moved the IMMR */
  77
  78 #if defined(CONFIG_GET_CPU_STR_F)
  79         get_cpu_str_f (buf);
  80         printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);
  81 #else
  82         printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
  83 #endif
  84
  85         /*
  86          * the bottom 16 bits of the immr are the Part Number and Mask Number
  87          * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
  88          * RISC Microcode Revision Number (13-10).
  89          * For the 8260, Motorola doesn't include the Microcode Revision
  90          * in the mask.
  91          */
  92         m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
  93         k = immap->im_dprambase16[PROFF_REVNUM / sizeof(u16)];
  94
  95         switch (m) {
  96         case 0x0000:
  97                 puts ("0.2 2J24M");
  98                 break;
  99         case 0x0010:
 100                 puts ("A.0 K22A");
 101                 break;
 102         case 0x0011:
 103                 puts ("A.1 1K22A-XC");
 104                 break;
 105         case 0x0001:
 106                 puts ("B.1 1K23A");
 107                 break;
 108         case 0x0021:
 109                 puts ("B.2 2K23A-XC");
 110                 break;
 111         case 0x0023:
 112                 puts ("B.3 3K23A");
 113                 break;
 114         case 0x0024:
 115                 puts ("C.2 6K23A");
 116                 break;
 117         case 0x0060:
 118                 puts ("A.0(A) 2K25A");
 119                 break;
 120         case 0x0062:
 121                 puts ("B.1 4K25A");
 122                 break;
 123         case 0x0064:
 124                 puts ("C.0 5K25A");
 125                 break;
 126         case 0x0A00:
 127                 puts ("0.0 0K49M");
 128                 break;
 129         case 0x0A01:
 130                 puts ("0.1 1K49M");
 131                 break;
 132         case 0x0A10:
 133                 puts ("1.0 1K49M");
 134                 break;
 135         case 0x0C00:
 136                 puts ("0.0 0K50M");
 137                 break;
 138         case 0x0C10:
 139                 puts ("1.0 1K50M");
 140                 break;
 141         case 0x0D00:
 142                 puts ("0.0 0K50M");
 143                 break;
 144         case 0x0D10:
 145                 puts ("1.0 1K50M");
 146                 break;
 147         default:
 148                 printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
 149                 break;
 150         }
 151
 152         printf (") at %s MHz\n", strmhz (buf, clock));
 153
 154         return 0;
 155 }
 156
 157 /* ------------------------------------------------------------------------- */
 158 /* configures a UPM by writing into the UPM RAM array                        */
 159 /* uses bank 11 and a dummy physical address (=BRx_BA_MSK)                   */
 160 /* NOTE: the physical address chosen must not overlap into any other area    */
 161 /* mapped by the memory controller because bank 11 has the lowest priority   */
 162
 163 void upmconfig (uint upm, uint * table, uint size)
 164 {
 165         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 166         volatile memctl8260_t *memctl = &immap->im_memctl;
 167         volatile uchar *dummy = (uchar *) BRx_BA_MSK;   /* set all BA bits */
 168         uint i;
 169
 170         /* first set up bank 11 to reference the correct UPM at a dummy address */
 171
 172         memctl->memc_or11 = ORxU_AM_MSK;        /* set all AM bits */
 173
 174         switch (upm) {
 175
 176         case UPMA:
 177                 memctl->memc_br11 =
 178                         ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA |
 179                         BRx_V;
 180                 memctl->memc_mamr = MxMR_OP_WARR;
 181                 break;
 182
 183         case UPMB:
 184                 memctl->memc_br11 =
 185                         ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB |
 186                         BRx_V;
 187                 memctl->memc_mbmr = MxMR_OP_WARR;
 188                 break;
 189
 190         case UPMC:
 191                 memctl->memc_br11 =
 192                         ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC |
 193                         BRx_V;
 194                 memctl->memc_mcmr = MxMR_OP_WARR;
 195                 break;
 196
 197         default:
 198                 panic ("upmconfig passed invalid UPM number (%u)\n", upm);
 199                 break;
 200
 201         }
 202
 203         /*
 204          * at this point, the dummy address is set up to access the selected UPM,
 205          * the MAD pointer is zero, and the MxMR OP is set for writing to RAM
 206          *
 207          * now we simply load the mdr with each word and poke the dummy address.
 208          * the MAD is incremented on each access.
 209          */
 210
 211         for (i = 0; i < size; i++) {
 212                 memctl->memc_mdr = table[i];
 213                 *dummy = 0;
 214         }
 215
 216         /* now kill bank 11 */
 217         memctl->memc_br11 = 0;
 218 }
 219
 220 /* ------------------------------------------------------------------------- */
 221
 222 #if !defined(CONFIG_HAVE_OWN_RESET)
 223 int
 224 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 225 {
 226         ulong msr, addr;
 227
 228         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 229
 230         immap->im_clkrst.car_rmr = RMR_CSRE;    /* Checkstop Reset enable */
 231
 232         /* Interrupts and MMU off */
 233         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 234
 235         msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
 236         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 237
 238         /*
 239          * Trying to execute the next instruction at a non-existing address
 240          * should cause a machine check, resulting in reset
 241          */
 242 #ifdef CONFIG_SYS_RESET_ADDRESS
 243         addr = CONFIG_SYS_RESET_ADDRESS;
 244 #else
 245         /*
 246          * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
 247          * - sizeof (ulong) is usually a valid address. Better pick an address
 248          * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
 249          */
 250         addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
 251 #endif
 252         ((void (*)(void)) addr) ();
 253         return 1;
 254
 255 }
 256 #endif  /* CONFIG_HAVE_OWN_RESET */
 257
 258 /* ------------------------------------------------------------------------- */
 259
 260 /*
 261  * Get timebase clock frequency (like cpu_clk in Hz)
 262  *
 263  */
 264 unsigned long get_tbclk (void)
 265 {
 266         ulong tbclk;
 267
 268         tbclk = (gd->bus_clk + 3L) / 4L;
 269
 270         return (tbclk);
 271 }
 272
 273 /* ------------------------------------------------------------------------- */
 274
 275 #if defined(CONFIG_WATCHDOG)
 276 void watchdog_reset (void)
 277 {
 278         int re_enable = disable_interrupts ();
 279
 280         reset_8260_watchdog ((immap_t *) CONFIG_SYS_IMMR);
 281         if (re_enable)
 282                 enable_interrupts ();
 283 }
 284 #endif /* CONFIG_WATCHDOG */
 285
 286 /* ------------------------------------------------------------------------- */
 287 #if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
 288 void ft_cpu_setup (void *blob, bd_t *bd)
 289 {
 290 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
 291     defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
 292         fdt_fixup_ethernet(blob);
 293 #endif
 294
 295         do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
 296                                "clock-frequency", bd->bi_brgfreq, 1);
 297
 298         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 299                 "bus-frequency", bd->bi_busfreq, 1);
 300         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 301                 "timebase-frequency", OF_TBCLK, 1);
 302         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 303                 "clock-frequency", bd->bi_intfreq, 1);
 304         fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 305 }
 306 #endif /* CONFIG_OF_LIBFDT */
 307
 308 /*
 309  * Initializes on-chip ethernet controllers.
 310  * to override, implement board_eth_init()
 311  */
 312 int cpu_eth_init(bd_t *bis)
 313 {
 314 #if defined(CONFIG_ETHER_ON_FCC)
 315         fec_initialize(bis);
 316 #endif
 317 #if defined(CONFIG_ETHER_ON_SCC)
 318         mpc82xx_scc_enet_initialize(bis);
 319 #endif
 320         return 0;
 321 }