arch/powerpc/cpu/mpc8260/cpu.c

   1 /*
   2  * (C) Copyright 2000-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
  26  *
  27  * written or collected and sometimes rewritten by
  28  * Magnus Damm <damm@bitsmart.com>
  29  *
  30  * modified by
  31  * Wolfgang Denk <wd@denx.de>
  32  *
  33  * modified for 8260 by
  34  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
  35  *
  36  * added 8260 masks by
  37  * Marius Groeger <mag@sysgo.de>
  38  *
  39  * added HiP7 (824x/827x/8280) processors support by
  40  * Yuli Barcohen <yuli@arabellasw.com>
  41  */
  42
  43 #include <common.h>
  44 #include <watchdog.h>
  45 #include <command.h>
  46 #include <mpc8260.h>
  47 #include <netdev.h>
  48 #include <asm/processor.h>
  49 #include <asm/cpm_8260.h>
  50
  51 #if defined(CONFIG_OF_LIBFDT)
  52 #include <libfdt.h>
  53 #include <libfdt_env.h>
  54 #include <fdt_support.h>
  55 #endif
  56
  57 DECLARE_GLOBAL_DATA_PTR;
  58
  59 #if defined(CONFIG_GET_CPU_STR_F)
  60 extern int get_cpu_str_f (char *buf);
  61 #endif
  62
  63 int checkcpu (void)
  64 {
  65         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  66         ulong clock = gd->cpu_clk;
  67         uint pvr = get_pvr ();
  68         uint immr, rev, m, k;
  69         char buf[32];
  70
  71         puts ("CPU:   ");
  72
  73         switch (pvr) {
  74         case PVR_8260:
  75         case PVR_8260_HIP3:
  76                 k = 3;
  77                 break;
  78         case PVR_8260_HIP4:
  79                 k = 4;
  80                 break;
  81         case PVR_8260_HIP7R1:
  82         case PVR_8260_HIP7RA:
  83         case PVR_8260_HIP7:
  84                 k = 7;
  85                 break;
  86         default:
  87                 return -1;      /* whoops! not an MPC8260 */
  88         }
  89         rev = pvr & 0xff;
  90
  91         immr = immap->im_memctl.memc_immr;
  92         if ((immr & IMMR_ISB_MSK) != CONFIG_SYS_IMMR)
  93                 return -1;      /* whoops! someone moved the IMMR */
  94
  95 #if defined(CONFIG_GET_CPU_STR_F)
  96         get_cpu_str_f (buf);
  97         printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);
  98 #else
  99         printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
 100 #endif
 101
 102         /*
 103          * the bottom 16 bits of the immr are the Part Number and Mask Number
 104          * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
 105          * RISC Microcode Revision Number (13-10).
 106          * For the 8260, Motorola doesn't include the Microcode Revision
 107          * in the mask.
 108          */
 109         m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
 110         k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]);
 111
 112         switch (m) {
 113         case 0x0000:
 114                 puts ("0.2 2J24M");
 115                 break;
 116         case 0x0010:
 117                 puts ("A.0 K22A");
 118                 break;
 119         case 0x0011:
 120                 puts ("A.1 1K22A-XC");
 121                 break;
 122         case 0x0001:
 123                 puts ("B.1 1K23A");
 124                 break;
 125         case 0x0021:
 126                 puts ("B.2 2K23A-XC");
 127                 break;
 128         case 0x0023:
 129                 puts ("B.3 3K23A");
 130                 break;
 131         case 0x0024:
 132                 puts ("C.2 6K23A");
 133                 break;
 134         case 0x0060:
 135                 puts ("A.0(A) 2K25A");
 136                 break;
 137         case 0x0062:
 138                 puts ("B.1 4K25A");
 139                 break;
 140         case 0x0064:
 141                 puts ("C.0 5K25A");
 142                 break;
 143         case 0x0A00:
 144                 puts ("0.0 0K49M");
 145                 break;
 146         case 0x0A01:
 147                 puts ("0.1 1K49M");
 148                 break;
 149         case 0x0A10:
 150                 puts ("1.0 1K49M");
 151                 break;
 152         case 0x0C00:
 153                 puts ("0.0 0K50M");
 154                 break;
 155         case 0x0C10:
 156                 puts ("1.0 1K50M");
 157                 break;
 158         case 0x0D00:
 159                 puts ("0.0 0K50M");
 160                 break;
 161         case 0x0D10:
 162                 puts ("1.0 1K50M");
 163                 break;
 164         default:
 165                 printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
 166                 break;
 167         }
 168
 169         printf (") at %s MHz\n", strmhz (buf, clock));
 170
 171         return 0;
 172 }
 173
 174 /* ------------------------------------------------------------------------- */
 175 /* configures a UPM by writing into the UPM RAM array                        */
 176 /* uses bank 11 and a dummy physical address (=BRx_BA_MSK)                   */
 177 /* NOTE: the physical address chosen must not overlap into any other area    */
 178 /* mapped by the memory controller because bank 11 has the lowest priority   */
 179
 180 void upmconfig (uint upm, uint * table, uint size)
 181 {
 182         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 183         volatile memctl8260_t *memctl = &immap->im_memctl;
 184         volatile uchar *dummy = (uchar *) BRx_BA_MSK;   /* set all BA bits */
 185         uint i;
 186
 187         /* first set up bank 11 to reference the correct UPM at a dummy address */
 188
 189         memctl->memc_or11 = ORxU_AM_MSK;        /* set all AM bits */
 190
 191         switch (upm) {
 192
 193         case UPMA:
 194                 memctl->memc_br11 =
 195                         ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA |
 196                         BRx_V;
 197                 memctl->memc_mamr = MxMR_OP_WARR;
 198                 break;
 199
 200         case UPMB:
 201                 memctl->memc_br11 =
 202                         ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB |
 203                         BRx_V;
 204                 memctl->memc_mbmr = MxMR_OP_WARR;
 205                 break;
 206
 207         case UPMC:
 208                 memctl->memc_br11 =
 209                         ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC |
 210                         BRx_V;
 211                 memctl->memc_mcmr = MxMR_OP_WARR;
 212                 break;
 213
 214         default:
 215                 panic ("upmconfig passed invalid UPM number (%u)\n", upm);
 216                 break;
 217
 218         }
 219
 220         /*
 221          * at this point, the dummy address is set up to access the selected UPM,
 222          * the MAD pointer is zero, and the MxMR OP is set for writing to RAM
 223          *
 224          * now we simply load the mdr with each word and poke the dummy address.
 225          * the MAD is incremented on each access.
 226          */
 227
 228         for (i = 0; i < size; i++) {
 229                 memctl->memc_mdr = table[i];
 230                 *dummy = 0;
 231         }
 232
 233         /* now kill bank 11 */
 234         memctl->memc_br11 = 0;
 235 }
 236
 237 /* ------------------------------------------------------------------------- */
 238
 239 #if !defined(CONFIG_HAVE_OWN_RESET)
 240 int
 241 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 242 {
 243         ulong msr, addr;
 244
 245         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 246
 247         immap->im_clkrst.car_rmr = RMR_CSRE;    /* Checkstop Reset enable */
 248
 249         /* Interrupts and MMU off */
 250         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 251
 252         msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
 253         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 254
 255         /*
 256          * Trying to execute the next instruction at a non-existing address
 257          * should cause a machine check, resulting in reset
 258          */
 259 #ifdef CONFIG_SYS_RESET_ADDRESS
 260         addr = CONFIG_SYS_RESET_ADDRESS;
 261 #else
 262         /*
 263          * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
 264          * - sizeof (ulong) is usually a valid address. Better pick an address
 265          * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
 266          */
 267         addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
 268 #endif
 269         ((void (*)(void)) addr) ();
 270         return 1;
 271
 272 }
 273 #endif  /* CONFIG_HAVE_OWN_RESET */
 274
 275 /* ------------------------------------------------------------------------- */
 276
 277 /*
 278  * Get timebase clock frequency (like cpu_clk in Hz)
 279  *
 280  */
 281 unsigned long get_tbclk (void)
 282 {
 283         ulong tbclk;
 284
 285         tbclk = (gd->bus_clk + 3L) / 4L;
 286
 287         return (tbclk);
 288 }
 289
 290 /* ------------------------------------------------------------------------- */
 291
 292 #if defined(CONFIG_WATCHDOG)
 293 void watchdog_reset (void)
 294 {
 295         int re_enable = disable_interrupts ();
 296
 297         reset_8260_watchdog ((immap_t *) CONFIG_SYS_IMMR);
 298         if (re_enable)
 299                 enable_interrupts ();
 300 }
 301 #endif /* CONFIG_WATCHDOG */
 302
 303 /* ------------------------------------------------------------------------- */
 304 #if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
 305 void ft_cpu_setup (void *blob, bd_t *bd)
 306 {
 307 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
 308     defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
 309         fdt_fixup_ethernet(blob);
 310 #endif
 311
 312         do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
 313                                "clock-frequency", bd->bi_brgfreq, 1);
 314
 315         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 316                 "bus-frequency", bd->bi_busfreq, 1);
 317         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 318                 "timebase-frequency", OF_TBCLK, 1);
 319         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 320                 "clock-frequency", bd->bi_intfreq, 1);
 321         fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 322 }
 323 #endif /* CONFIG_OF_LIBFDT */
 324
 325 /*
 326  * Initializes on-chip ethernet controllers.
 327  * to override, implement board_eth_init()
 328  */
 329 int cpu_eth_init(bd_t *bis)
 330 {
 331 #if defined(CONFIG_ETHER_ON_FCC)
 332         fec_initialize(bis);
 333 #endif
 334 #if defined(CONFIG_ETHER_ON_SCC)
 335         mpc82xx_scc_enet_initialize(bis);
 336 #endif
 337         return 0;
 338 }