2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/cpm_8260.h>
13 DECLARE_GLOBAL_DATA_PTR
;
15 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
16 extern unsigned long board_get_cpu_clk_f (void);
19 static void config_8260_ioports (volatile immap_t
* immr
)
23 for (portnum
= 0; portnum
< 4; portnum
++) {
30 iop_conf_t
*iopc
= (iop_conf_t
*) & iop_conf_tab
[portnum
][0];
31 iop_conf_t
*eiopc
= iopc
+ 32;
36 * index 0 refers to pin 31,
37 * index 31 refers to pin 0
39 while (iopc
< eiopc
) {
59 volatile ioport_t
*iop
= ioport_addr (immr
, portnum
);
63 * the (somewhat confused) paragraph at the
64 * bottom of page 35-5 warns that there might
65 * be "unknown behaviour" when programming
66 * PSORx and PDIRx, if PPARx = 1, so I
67 * decided this meant I had to disable the
68 * dedicated function first, and enable it
72 iop
->psor
= (iop
->psor
& tpmsk
) | psor
;
73 iop
->podr
= (iop
->podr
& tpmsk
) | podr
;
74 iop
->pdat
= (iop
->pdat
& tpmsk
) | pdat
;
75 iop
->pdir
= (iop
->pdir
& tpmsk
) | pdir
;
81 #define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask))
83 * Breath some life into the CPU...
85 * Set up the memory map,
86 * initialize a bunch of registers,
87 * initialize the UPM's
89 void cpu_init_f (volatile immap_t
* immr
)
92 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
93 unsigned long cpu_clk
;
95 volatile memctl8260_t
*memctl
= &immr
->im_memctl
;
96 extern void m8260_cpm_reset (void);
98 /* Pointer is writable since we allocated a register for it */
99 gd
= (gd_t
*) (CONFIG_SYS_INIT_RAM_ADDR
+ CONFIG_SYS_GBL_DATA_OFFSET
);
101 /* Clear initial global data */
102 memset ((void *) gd
, 0, sizeof (gd_t
));
104 /* RSR - Reset Status Register - clear all status (5-4) */
105 gd
->arch
.reset_status
= immr
->im_clkrst
.car_rsr
;
106 immr
->im_clkrst
.car_rsr
= RSR_ALLBITS
;
108 /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
109 immr
->im_clkrst
.car_rmr
= CONFIG_SYS_RMR
;
111 /* BCR - Bus Configuration Register (4-25) */
112 #if defined(CONFIG_SYS_BCR_60x) && (CONFIG_SYS_BCR_SINGLE)
113 if (immr
->im_siu_conf
.sc_bcr
& BCR_EBM
) {
114 immr
->im_siu_conf
.sc_bcr
= SET_VAL_MASK(immr
->im_siu_conf
.sc_bcr
, CONFIG_SYS_BCR_60x
, 0x80000010);
116 immr
->im_siu_conf
.sc_bcr
= SET_VAL_MASK(immr
->im_siu_conf
.sc_bcr
, CONFIG_SYS_BCR_SINGLE
, 0x80000010);
119 immr
->im_siu_conf
.sc_bcr
= CONFIG_SYS_BCR
;
122 /* SIUMCR - contains debug pin configuration (4-31) */
123 #if defined(CONFIG_SYS_SIUMCR_LOW) && (CONFIG_SYS_SIUMCR_HIGH)
124 cpu_clk
= board_get_cpu_clk_f ();
125 if (cpu_clk
>= 100000000) {
126 immr
->im_siu_conf
.sc_siumcr
= SET_VAL_MASK(immr
->im_siu_conf
.sc_siumcr
, CONFIG_SYS_SIUMCR_HIGH
, 0x9f3cc000);
128 immr
->im_siu_conf
.sc_siumcr
= SET_VAL_MASK(immr
->im_siu_conf
.sc_siumcr
, CONFIG_SYS_SIUMCR_LOW
, 0x9f3cc000);
131 immr
->im_siu_conf
.sc_siumcr
= CONFIG_SYS_SIUMCR
;
134 config_8260_ioports (immr
);
136 /* initialize time counter status and control register (4-40) */
137 immr
->im_sit
.sit_tmcntsc
= CONFIG_SYS_TMCNTSC
;
139 /* initialize the PIT (4-42) */
140 immr
->im_sit
.sit_piscr
= CONFIG_SYS_PISCR
;
142 /* System clock control register (9-8) */
143 sccr
= immr
->im_clkrst
.car_sccr
&
144 (SCCR_PCI_MODE
| SCCR_PCI_MODCK
| SCCR_PCIDF_MSK
);
145 immr
->im_clkrst
.car_sccr
= sccr
|
146 (CONFIG_SYS_SCCR
& ~(SCCR_PCI_MODE
| SCCR_PCI_MODCK
| SCCR_PCIDF_MSK
) );
152 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
153 * addresses - these have to be modified later when FLASH size
154 * has been determined
157 #if defined(CONFIG_SYS_OR0_REMAP)
158 memctl
->memc_or0
= CONFIG_SYS_OR0_REMAP
;
160 #if defined(CONFIG_SYS_OR1_REMAP)
161 memctl
->memc_or1
= CONFIG_SYS_OR1_REMAP
;
164 /* now restrict to preliminary range */
165 /* the PS came from the HRCW, don't change it */
166 memctl
->memc_br0
= SET_VAL_MASK(memctl
->memc_br0
, CONFIG_SYS_BR0_PRELIM
, BRx_PS_MSK
);
167 memctl
->memc_or0
= CONFIG_SYS_OR0_PRELIM
;
169 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
170 memctl
->memc_or1
= CONFIG_SYS_OR1_PRELIM
;
171 memctl
->memc_br1
= CONFIG_SYS_BR1_PRELIM
;
174 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
175 memctl
->memc_or2
= CONFIG_SYS_OR2_PRELIM
;
176 memctl
->memc_br2
= CONFIG_SYS_BR2_PRELIM
;
179 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
180 memctl
->memc_or3
= CONFIG_SYS_OR3_PRELIM
;
181 memctl
->memc_br3
= CONFIG_SYS_BR3_PRELIM
;
184 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
185 memctl
->memc_or4
= CONFIG_SYS_OR4_PRELIM
;
186 memctl
->memc_br4
= CONFIG_SYS_BR4_PRELIM
;
189 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
190 memctl
->memc_or5
= CONFIG_SYS_OR5_PRELIM
;
191 memctl
->memc_br5
= CONFIG_SYS_BR5_PRELIM
;
194 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
195 memctl
->memc_or6
= CONFIG_SYS_OR6_PRELIM
;
196 memctl
->memc_br6
= CONFIG_SYS_BR6_PRELIM
;
199 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
200 memctl
->memc_or7
= CONFIG_SYS_OR7_PRELIM
;
201 memctl
->memc_br7
= CONFIG_SYS_BR7_PRELIM
;
204 #if defined(CONFIG_SYS_BR8_PRELIM) && defined(CONFIG_SYS_OR8_PRELIM)
205 memctl
->memc_or8
= CONFIG_SYS_OR8_PRELIM
;
206 memctl
->memc_br8
= CONFIG_SYS_BR8_PRELIM
;
209 #if defined(CONFIG_SYS_BR9_PRELIM) && defined(CONFIG_SYS_OR9_PRELIM)
210 memctl
->memc_or9
= CONFIG_SYS_OR9_PRELIM
;
211 memctl
->memc_br9
= CONFIG_SYS_BR9_PRELIM
;
214 #if defined(CONFIG_SYS_BR10_PRELIM) && defined(CONFIG_SYS_OR10_PRELIM)
215 memctl
->memc_or10
= CONFIG_SYS_OR10_PRELIM
;
216 memctl
->memc_br10
= CONFIG_SYS_BR10_PRELIM
;
219 #if defined(CONFIG_SYS_BR11_PRELIM) && defined(CONFIG_SYS_OR11_PRELIM)
220 memctl
->memc_or11
= CONFIG_SYS_OR11_PRELIM
;
221 memctl
->memc_br11
= CONFIG_SYS_BR11_PRELIM
;
228 * initialize higher level parts of CPU like time base and timers
230 int cpu_init_r (void)
232 volatile immap_t
*immr
= (immap_t
*) gd
->bd
->bi_immr_base
;
234 immr
->im_cpm
.cp_rccr
= CONFIG_SYS_RCCR
;
240 * print out the reason for the reset
242 int prt_8260_rsr (void)
250 RSR_CSRS
, "Check Stop"}, {
251 RSR_SWRS
, "Software Watchdog"}, {
252 RSR_BMRS
, "Bus Monitor"}, {
253 RSR_ESRS
, "External Soft"}, {
254 RSR_EHRS
, "External Hard"}
256 static int n
= ARRAY_SIZE(bits
);
257 ulong rsr
= gd
->arch
.reset_status
;
261 puts (CPU_ID_STR
" Reset Status:");
264 for (i
= 0; i
< n
; i
++)
265 if (rsr
& bits
[i
].mask
) {
266 printf ("%s%s", sep
, bits
[i
].desc
);