arch/powerpc/cpu/mpc8260/cpu_init.c

   1 /*
   2  * (C) Copyright 2000-2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <mpc8260.h>
  10 #include <asm/cpm_8260.h>
  11 #include <ioports.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
  16 extern unsigned long board_get_cpu_clk_f (void);
  17 #endif
  18
  19 static void config_8260_ioports (volatile immap_t * immr)
  20 {
  21         int portnum;
  22
  23         for (portnum = 0; portnum < 4; portnum++) {
  24                 uint pmsk = 0,
  25                      ppar = 0,
  26                      psor = 0,
  27                      pdir = 0,
  28                      podr = 0,
  29                      pdat = 0;
  30                 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
  31                 iop_conf_t *eiopc = iopc + 32;
  32                 uint msk = 1;
  33
  34                 /*
  35                  * NOTE:
  36                  * index 0 refers to pin 31,
  37                  * index 31 refers to pin 0
  38                  */
  39                 while (iopc < eiopc) {
  40                         if (iopc->conf) {
  41                                 pmsk |= msk;
  42                                 if (iopc->ppar)
  43                                         ppar |= msk;
  44                                 if (iopc->psor)
  45                                         psor |= msk;
  46                                 if (iopc->pdir)
  47                                         pdir |= msk;
  48                                 if (iopc->podr)
  49                                         podr |= msk;
  50                                 if (iopc->pdat)
  51                                         pdat |= msk;
  52                         }
  53
  54                         msk <<= 1;
  55                         iopc++;
  56                 }
  57
  58                 if (pmsk != 0) {
  59                         volatile ioport_t *iop = ioport_addr (immr, portnum);
  60                         uint tpmsk = ~pmsk;
  61
  62                         /*
  63                          * the (somewhat confused) paragraph at the
  64                          * bottom of page 35-5 warns that there might
  65                          * be "unknown behaviour" when programming
  66                          * PSORx and PDIRx, if PPARx = 1, so I
  67                          * decided this meant I had to disable the
  68                          * dedicated function first, and enable it
  69                          * last.
  70                          */
  71                         iop->ppar &= tpmsk;
  72                         iop->psor = (iop->psor & tpmsk) | psor;
  73                         iop->podr = (iop->podr & tpmsk) | podr;
  74                         iop->pdat = (iop->pdat & tpmsk) | pdat;
  75                         iop->pdir = (iop->pdir & tpmsk) | pdir;
  76                         iop->ppar |= ppar;
  77                 }
  78         }
  79 }
  80
  81 #define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask))
  82 /*
  83  * Breath some life into the CPU...
  84  *
  85  * Set up the memory map,
  86  * initialize a bunch of registers,
  87  * initialize the UPM's
  88  */
  89 void cpu_init_f (volatile immap_t * immr)
  90 {
  91 #if !defined(CONFIG_COGENT)             /* done in start.S for the cogent */
  92         uint sccr;
  93 #endif
  94 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
  95         unsigned long cpu_clk;
  96 #endif
  97         volatile memctl8260_t *memctl = &immr->im_memctl;
  98         extern void m8260_cpm_reset (void);
  99
 100         /* Pointer is writable since we allocated a register for it */
 101         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 102
 103         /* Clear initial global data */
 104         memset ((void *) gd, 0, sizeof (gd_t));
 105
 106         /* RSR - Reset Status Register - clear all status (5-4) */
 107         gd->arch.reset_status = immr->im_clkrst.car_rsr;
 108         immr->im_clkrst.car_rsr = RSR_ALLBITS;
 109
 110         /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
 111         immr->im_clkrst.car_rmr = CONFIG_SYS_RMR;
 112
 113         /* BCR - Bus Configuration Register (4-25) */
 114 #if defined(CONFIG_SYS_BCR_60x) && (CONFIG_SYS_BCR_SINGLE)
 115         if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
 116                 immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_60x, 0x80000010);
 117         } else {
 118                 immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_SINGLE, 0x80000010);
 119         }
 120 #else
 121         immr->im_siu_conf.sc_bcr = CONFIG_SYS_BCR;
 122 #endif
 123
 124         /* SIUMCR - contains debug pin configuration (4-31) */
 125 #if defined(CONFIG_SYS_SIUMCR_LOW) && (CONFIG_SYS_SIUMCR_HIGH)
 126         cpu_clk = board_get_cpu_clk_f ();
 127         if (cpu_clk >= 100000000) {
 128                 immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_HIGH, 0x9f3cc000);
 129         } else {
 130                 immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_LOW, 0x9f3cc000);
 131         }
 132 #else
 133         immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
 134 #endif
 135
 136         config_8260_ioports (immr);
 137
 138         /* initialize time counter status and control register (4-40) */
 139         immr->im_sit.sit_tmcntsc = CONFIG_SYS_TMCNTSC;
 140
 141         /* initialize the PIT (4-42) */
 142         immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
 143
 144 #if !defined(CONFIG_COGENT)             /* done in start.S for the cogent */
 145         /* System clock control register (9-8) */
 146         sccr = immr->im_clkrst.car_sccr &
 147                 (SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK);
 148         immr->im_clkrst.car_sccr = sccr |
 149                 (CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) );
 150 #endif /* !CONFIG_COGENT */
 151
 152         /*
 153          * Memory Controller:
 154          */
 155
 156         /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 157          * addresses - these have to be modified later when FLASH size
 158          * has been determined
 159          */
 160
 161 #if defined(CONFIG_SYS_OR0_REMAP)
 162         memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
 163 #endif
 164 #if defined(CONFIG_SYS_OR1_REMAP)
 165         memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
 166 #endif
 167
 168         /* now restrict to preliminary range */
 169         /* the PS came from the HRCW, don't change it */
 170         memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CONFIG_SYS_BR0_PRELIM, BRx_PS_MSK);
 171         memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
 172
 173 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
 174         memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
 175         memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 176 #endif
 177
 178 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
 179         memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
 180         memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 181 #endif
 182
 183 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
 184         memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
 185         memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 186 #endif
 187
 188 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
 189         memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
 190         memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
 191 #endif
 192
 193 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
 194         memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
 195         memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
 196 #endif
 197
 198 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
 199         memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
 200         memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
 201 #endif
 202
 203 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
 204         memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
 205         memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
 206 #endif
 207
 208 #if defined(CONFIG_SYS_BR8_PRELIM) && defined(CONFIG_SYS_OR8_PRELIM)
 209         memctl->memc_or8 = CONFIG_SYS_OR8_PRELIM;
 210         memctl->memc_br8 = CONFIG_SYS_BR8_PRELIM;
 211 #endif
 212
 213 #if defined(CONFIG_SYS_BR9_PRELIM) && defined(CONFIG_SYS_OR9_PRELIM)
 214         memctl->memc_or9 = CONFIG_SYS_OR9_PRELIM;
 215         memctl->memc_br9 = CONFIG_SYS_BR9_PRELIM;
 216 #endif
 217
 218 #if defined(CONFIG_SYS_BR10_PRELIM) && defined(CONFIG_SYS_OR10_PRELIM)
 219         memctl->memc_or10 = CONFIG_SYS_OR10_PRELIM;
 220         memctl->memc_br10 = CONFIG_SYS_BR10_PRELIM;
 221 #endif
 222
 223 #if defined(CONFIG_SYS_BR11_PRELIM) && defined(CONFIG_SYS_OR11_PRELIM)
 224         memctl->memc_or11 = CONFIG_SYS_OR11_PRELIM;
 225         memctl->memc_br11 = CONFIG_SYS_BR11_PRELIM;
 226 #endif
 227
 228         m8260_cpm_reset ();
 229 }
 230
 231 /*
 232  * initialize higher level parts of CPU like time base and timers
 233  */
 234 int cpu_init_r (void)
 235 {
 236         volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base;
 237
 238         immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;
 239
 240         return (0);
 241 }
 242
 243 /*
 244  * print out the reason for the reset
 245  */
 246 int prt_8260_rsr (void)
 247 {
 248         static struct {
 249                 ulong mask;
 250                 char *desc;
 251         } bits[] = {
 252                 {
 253                 RSR_JTRS, "JTAG"}, {
 254                 RSR_CSRS, "Check Stop"}, {
 255                 RSR_SWRS, "Software Watchdog"}, {
 256                 RSR_BMRS, "Bus Monitor"}, {
 257                 RSR_ESRS, "External Soft"}, {
 258                 RSR_EHRS, "External Hard"}
 259         };
 260         static int n = sizeof bits / sizeof bits[0];
 261         ulong rsr = gd->arch.reset_status;
 262         int i;
 263         char *sep;
 264
 265         puts (CPU_ID_STR " Reset Status:");
 266
 267         sep = " ";
 268         for (i = 0; i < n; i++)
 269                 if (rsr & bits[i].mask) {
 270                         printf ("%s%s", sep, bits[i].desc);
 271                         sep = ", ";
 272                 }
 273
 274         puts ("\n\n");
 275         return (0);
 276 }