arch/powerpc/cpu/mpc8260/i2c.c

   1 /*
   2  * (C) Copyright 2000
   3  * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
   4  *
   5  * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   6  * Marius Groeger <mgroeger@sysgo.de>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <console.h>
  13
  14 #if defined(CONFIG_HARD_I2C)
  15
  16 #include <asm/cpm_8260.h>
  17 #include <i2c.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #if defined(CONFIG_I2C_MULTI_BUS)
  22 static unsigned int i2c_bus_num __attribute__ ((section(".data"))) = 0;
  23 #endif /* CONFIG_I2C_MULTI_BUS */
  24
  25 /* uSec to wait between polls of the i2c */
  26 #define DELAY_US        100
  27 /* uSec to wait for the CPM to start processing the buffer */
  28 #define START_DELAY_US  1000
  29
  30 /*
  31  * tx/rx per-byte timeout: we delay DELAY_US uSec between polls so the
  32  * timeout will be (tx_length + rx_length) * DELAY_US * TOUT_LOOP
  33  */
  34 #define TOUT_LOOP 5
  35
  36 /*
  37  * Set default values
  38  */
  39 #ifndef CONFIG_SYS_I2C_SPEED
  40 #define CONFIG_SYS_I2C_SPEED    50000
  41 #endif
  42
  43
  44 typedef void (*i2c_ecb_t) (int, int, void *);   /* error callback function */
  45
  46 /* This structure keeps track of the bd and buffer space usage. */
  47 typedef struct i2c_state {
  48         int rx_idx;             /* index   to next free Rx BD */
  49         int tx_idx;             /* index   to next free Tx BD */
  50         void *rxbd;             /* pointer to next free Rx BD */
  51         void *txbd;             /* pointer to next free Tx BD */
  52         int tx_space;           /* number  of Tx bytes left   */
  53         unsigned char *tx_buf;  /* pointer to free Tx area    */
  54         i2c_ecb_t err_cb;       /* error callback function    */
  55         void *cb_data;          /* private data to be passed  */
  56 } i2c_state_t;
  57
  58 /* flags for i2c_send() and i2c_receive() */
  59 #define I2CF_ENABLE_SECONDARY   0x01    /* secondary_address is valid   */
  60 #define I2CF_START_COND         0x02    /* tx: generate start condition */
  61 #define I2CF_STOP_COND          0x04    /* tx: generate stop  condition */
  62
  63 /* return codes */
  64 #define I2CERR_NO_BUFFERS       1       /* no more BDs or buffer space  */
  65 #define I2CERR_MSG_TOO_LONG     2       /* tried to send/receive to much data */
  66 #define I2CERR_TIMEOUT          3       /* timeout in i2c_doio()        */
  67 #define I2CERR_QUEUE_EMPTY      4       /* i2c_doio called without send/rcv */
  68 #define I2CERR_IO_ERROR         5       /* had an error during comms    */
  69
  70 /* error callback flags */
  71 #define I2CECB_RX_ERR           0x10    /* this is a receive error      */
  72 #define     I2CECB_RX_OV        0x02    /* receive overrun error        */
  73 #define     I2CECB_RX_MASK      0x0f    /* mask for error bits          */
  74 #define I2CECB_TX_ERR           0x20    /* this is a transmit error     */
  75 #define     I2CECB_TX_CL        0x01    /* transmit collision error     */
  76 #define     I2CECB_TX_UN        0x02    /* transmit underflow error     */
  77 #define     I2CECB_TX_NAK       0x04    /* transmit no ack error        */
  78 #define     I2CECB_TX_MASK      0x0f    /* mask for error bits          */
  79 #define I2CECB_TIMEOUT          0x40    /* this is a timeout error      */
  80
  81 #define ERROR_I2C_NONE          0
  82 #define ERROR_I2C_LENGTH        1
  83
  84 #define I2C_WRITE_BIT           0x00
  85 #define I2C_READ_BIT            0x01
  86
  87 #define I2C_RXTX_LEN    128     /* maximum tx/rx buffer length */
  88
  89
  90 #define NUM_RX_BDS 4
  91 #define NUM_TX_BDS 4
  92 #define MAX_TX_SPACE 256
  93
  94 typedef struct I2C_BD {
  95         unsigned short status;
  96         unsigned short length;
  97         unsigned char *addr;
  98 } I2C_BD;
  99
 100 #define BD_I2C_TX_START 0x0400  /* special status for i2c: Start condition */
 101
 102 #define BD_I2C_TX_CL    0x0001  /* collision error */
 103 #define BD_I2C_TX_UN    0x0002  /* underflow error */
 104 #define BD_I2C_TX_NAK   0x0004  /* no acknowledge error */
 105 #define BD_I2C_TX_ERR   (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
 106
 107 #define BD_I2C_RX_ERR   BD_SC_OV
 108
 109 /*
 110  * Returns the best value of I2BRG to meet desired clock speed of I2C with
 111  * input parameters (clock speed, filter, and predivider value).
 112  * It returns computer speed value and the difference between it and desired
 113  * speed.
 114  */
 115 static inline int
 116 i2c_roundrate(int hz, int speed, int filter, int modval,
 117               int *brgval, int *totspeed)
 118 {
 119         int moddiv = 1 << (5 - (modval & 3)), brgdiv, div;
 120
 121         debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
 122                 hz, speed, filter, modval);
 123
 124         div = moddiv * speed;
 125         brgdiv = (hz + div - 1) / div;
 126
 127         debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv);
 128
 129         *brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter);
 130
 131         if ((*brgval < 0) || (*brgval > 255)) {
 132                 debug("\t\trejected brgval=%d\n", *brgval);
 133                 return -1;
 134         }
 135
 136         brgdiv = 2 * (*brgval + 3 + (2 * filter));
 137         div = moddiv * brgdiv;
 138         *totspeed = hz / div;
 139
 140         debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed);
 141
 142         return 0;
 143 }
 144
 145 /*
 146  * Sets the I2C clock predivider and divider to meet required clock speed.
 147  */
 148 static int i2c_setrate(int hz, int speed)
 149 {
 150         immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 151         volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
 152         int     brgval,
 153                 modval, /* 0-3 */
 154                 bestspeed_diff = speed,
 155                 bestspeed_brgval = 0,
 156                 bestspeed_modval = 0,
 157                 bestspeed_filter = 0,
 158                 totspeed,
 159                 filter = 0;     /* Use this fixed value */
 160
 161         for (modval = 0; modval < 4; modval++) {
 162                 if (i2c_roundrate(hz, speed, filter, modval, &brgval, &totspeed)
 163                     == 0) {
 164                         int diff = speed - totspeed;
 165
 166                         if ((diff >= 0) && (diff < bestspeed_diff)) {
 167                                 bestspeed_diff = diff;
 168                                 bestspeed_modval = modval;
 169                                 bestspeed_brgval = brgval;
 170                                 bestspeed_filter = filter;
 171                         }
 172                 }
 173         }
 174
 175         debug("[I2C] Best is:\n");
 176         debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
 177                 hz, speed, bestspeed_filter, bestspeed_modval, bestspeed_brgval,
 178                 bestspeed_diff);
 179
 180         i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) |
 181                 (bestspeed_filter << 3);
 182         i2c->i2c_i2brg = bestspeed_brgval & 0xff;
 183
 184         debug("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod,
 185                 i2c->i2c_i2brg);
 186
 187         return 1;
 188 }
 189
 190 void i2c_init(int speed, int slaveadd)
 191 {
 192         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 193         volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
 194         volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
 195         volatile iic_t *iip;
 196         ulong rbase, tbase;
 197         volatile I2C_BD *rxbd, *txbd;
 198         uint dpaddr;
 199
 200 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 201         /*
 202          * call board specific i2c bus reset routine before accessing the
 203          * environment, which might be in a chip on that bus. For details
 204          * about this problem see doc/I2C_Edge_Conditions.
 205          */
 206         i2c_init_board();
 207 #endif
 208
 209         dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)];
 210         if (dpaddr == 0) {
 211                 /* need to allocate dual port ram */
 212                 dpaddr = m8260_cpm_dpalloc(64 +
 213                                         (NUM_RX_BDS * sizeof(I2C_BD)) +
 214                                         (NUM_TX_BDS * sizeof(I2C_BD)) +
 215                                         MAX_TX_SPACE, 64);
 216                 immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)] =
 217                         dpaddr;
 218         }
 219
 220         /*
 221          * initialise data in dual port ram:
 222          *
 223          *        dpaddr -> parameter ram (64 bytes)
 224          *         rbase -> rx BD         (NUM_RX_BDS * sizeof(I2C_BD) bytes)
 225          *         tbase -> tx BD         (NUM_TX_BDS * sizeof(I2C_BD) bytes)
 226          *                  tx buffer     (MAX_TX_SPACE bytes)
 227          */
 228
 229         iip = (iic_t *)&immap->im_dprambase[dpaddr];
 230         memset((void *)iip, 0, sizeof(iic_t));
 231
 232         rbase = dpaddr + 64;
 233         tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
 234
 235         /* Disable interrupts */
 236         i2c->i2c_i2mod = 0x00;
 237         i2c->i2c_i2cmr = 0x00;
 238         i2c->i2c_i2cer = 0xff;
 239         i2c->i2c_i2add = slaveadd;
 240
 241         /*
 242          * Set the I2C BRG Clock division factor from desired i2c rate
 243          * and current CPU rate (we assume sccr dfbgr field is 0;
 244          * divide BRGCLK by 1)
 245          */
 246         debug("[I2C] Setting rate...\n");
 247         i2c_setrate(gd->arch.brg_clk, CONFIG_SYS_I2C_SPEED);
 248
 249         /* Set I2C controller in master mode */
 250         i2c->i2c_i2com = 0x01;
 251
 252         /* Initialize Tx/Rx parameters */
 253         iip->iic_rbase = rbase;
 254         iip->iic_tbase = tbase;
 255         rxbd = (I2C_BD *)((unsigned char *) &immap->
 256                         im_dprambase[iip->iic_rbase]);
 257         txbd = (I2C_BD *)((unsigned char *) &immap->
 258                         im_dprambase[iip->iic_tbase]);
 259
 260         debug("[I2C] rbase = %04x\n", iip->iic_rbase);
 261         debug("[I2C] tbase = %04x\n", iip->iic_tbase);
 262         debug("[I2C] rxbd = %08x\n", (int) rxbd);
 263         debug("[I2C] txbd = %08x\n", (int) txbd);
 264
 265         /* Set big endian byte order */
 266         iip->iic_tfcr = 0x10;
 267         iip->iic_rfcr = 0x10;
 268
 269         /* Set maximum receive size. */
 270         iip->iic_mrblr = I2C_RXTX_LEN;
 271
 272         cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE,
 273                                 CPM_CR_I2C_SBLOCK,
 274                                 0x00, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 275         do {
 276                 __asm__ __volatile__("eieio");
 277         } while (cp->cp_cpcr & CPM_CR_FLG);
 278
 279         /* Clear events and interrupts */
 280         i2c->i2c_i2cer = 0xff;
 281         i2c->i2c_i2cmr = 0x00;
 282 }
 283
 284 static
 285 void i2c_newio(i2c_state_t *state)
 286 {
 287         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 288         volatile iic_t *iip;
 289         uint dpaddr;
 290
 291         debug("[I2C] i2c_newio\n");
 292
 293         dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)];
 294         iip = (iic_t *)&immap->im_dprambase[dpaddr];
 295         state->rx_idx = 0;
 296         state->tx_idx = 0;
 297         state->rxbd = (void *)&immap->im_dprambase[iip->iic_rbase];
 298         state->txbd = (void *)&immap->im_dprambase[iip->iic_tbase];
 299         state->tx_space = MAX_TX_SPACE;
 300         state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
 301         state->err_cb = NULL;
 302         state->cb_data = NULL;
 303
 304         debug("[I2C] rxbd = %08x\n", (int)state->rxbd);
 305         debug("[I2C] txbd = %08x\n", (int)state->txbd);
 306         debug("[I2C] tx_buf = %08x\n", (int)state->tx_buf);
 307
 308         /* clear the buffer memory */
 309         memset((char *) state->tx_buf, 0, MAX_TX_SPACE);
 310 }
 311
 312 static
 313 int i2c_send(i2c_state_t *state,
 314              unsigned char address,
 315              unsigned char secondary_address,
 316              unsigned int flags, unsigned short size, unsigned char *dataout)
 317 {
 318         volatile I2C_BD *txbd;
 319         int i, j;
 320
 321         debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
 322                 address, secondary_address, flags, size);
 323
 324         /* trying to send message larger than BD */
 325         if (size > I2C_RXTX_LEN)
 326                 return I2CERR_MSG_TOO_LONG;
 327
 328         /* no more free bds */
 329         if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
 330                 return I2CERR_NO_BUFFERS;
 331
 332         txbd = (I2C_BD *)state->txbd;
 333         txbd->addr = state->tx_buf;
 334
 335         debug("[I2C] txbd = %08x\n", (int) txbd);
 336
 337         if (flags & I2CF_START_COND) {
 338                 debug("[I2C] Formatting addresses...\n");
 339                 if (flags & I2CF_ENABLE_SECONDARY) {
 340                         /* Length of message plus dest addresses */
 341                         txbd->length = size + 2;
 342                         txbd->addr[0] = address << 1;
 343                         txbd->addr[1] = secondary_address;
 344                         i = 2;
 345                 } else {
 346                         /* Length of message plus dest address */
 347                         txbd->length = size + 1;
 348                         /* Write destination address to BD */
 349                         txbd->addr[0] = address << 1;
 350                         i = 1;
 351                 }
 352         } else {
 353                 txbd->length = size;    /* Length of message */
 354                 i = 0;
 355         }
 356
 357         /* set up txbd */
 358         txbd->status = BD_SC_READY;
 359         if (flags & I2CF_START_COND)
 360                 txbd->status |= BD_I2C_TX_START;
 361         if (flags & I2CF_STOP_COND)
 362                 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 363
 364         /* Copy data to send into buffer */
 365         debug("[I2C] copy data...\n");
 366         for (j = 0; j < size; i++, j++)
 367                 txbd->addr[i] = dataout[j];
 368
 369         debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 370                 txbd->length, txbd->status, txbd->addr[0], txbd->addr[1]);
 371
 372         /* advance state */
 373         state->tx_buf += txbd->length;
 374         state->tx_space -= txbd->length;
 375         state->tx_idx++;
 376         state->txbd = (void *) (txbd + 1);
 377
 378         return 0;
 379 }
 380
 381 static
 382 int i2c_receive(i2c_state_t *state,
 383                 unsigned char address,
 384                 unsigned char secondary_address,
 385                 unsigned int flags,
 386                 unsigned short size_to_expect, unsigned char *datain)
 387 {
 388         volatile I2C_BD *rxbd, *txbd;
 389
 390         debug("[I2C] i2c_receive %02d %02d %02d\n", address,
 391                 secondary_address, flags);
 392
 393         /* Expected to receive too much */
 394         if (size_to_expect > I2C_RXTX_LEN)
 395                 return I2CERR_MSG_TOO_LONG;
 396
 397         /* no more free bds */
 398         if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
 399             || state->tx_space < 2)
 400                 return I2CERR_NO_BUFFERS;
 401
 402         rxbd = (I2C_BD *) state->rxbd;
 403         txbd = (I2C_BD *) state->txbd;
 404
 405         debug("[I2C] rxbd = %08x\n", (int) rxbd);
 406         debug("[I2C] txbd = %08x\n", (int) txbd);
 407
 408         txbd->addr = state->tx_buf;
 409
 410         /* set up TXBD for destination address */
 411         if (flags & I2CF_ENABLE_SECONDARY) {
 412                 txbd->length = 2;
 413                 txbd->addr[0] = address << 1;   /* Write data */
 414                 txbd->addr[1] = secondary_address;      /* Internal address */
 415                 txbd->status = BD_SC_READY;
 416         } else {
 417                 txbd->length = 1 + size_to_expect;
 418                 txbd->addr[0] = (address << 1) | 0x01;
 419                 txbd->status = BD_SC_READY;
 420                 memset(&txbd->addr[1], 0, txbd->length);
 421         }
 422
 423         /* set up rxbd for reception */
 424         rxbd->status = BD_SC_EMPTY;
 425         rxbd->length = size_to_expect;
 426         rxbd->addr = datain;
 427
 428         txbd->status |= BD_I2C_TX_START;
 429         if (flags & I2CF_STOP_COND) {
 430                 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 431                 rxbd->status |= BD_SC_WRAP;
 432         }
 433
 434         debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 435                 txbd->length, txbd->status, txbd->addr[0], txbd->addr[1]);
 436         debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 437                 rxbd->length, rxbd->status, rxbd->addr[0], rxbd->addr[1]);
 438
 439         /* advance state */
 440         state->tx_buf += txbd->length;
 441         state->tx_space -= txbd->length;
 442         state->tx_idx++;
 443         state->txbd = (void *) (txbd + 1);
 444         state->rx_idx++;
 445         state->rxbd = (void *) (rxbd + 1);
 446
 447         return 0;
 448 }
 449
 450
 451 static
 452 int i2c_doio(i2c_state_t *state)
 453 {
 454         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 455         volatile iic_t *iip;
 456         volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
 457         volatile I2C_BD *txbd, *rxbd;
 458         int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
 459         uint dpaddr;
 460
 461         debug("[I2C] i2c_doio\n");
 462
 463         if (state->tx_idx <= 0 && state->rx_idx <= 0) {
 464                 debug("[I2C] No I/O is queued\n");
 465                 return I2CERR_QUEUE_EMPTY;
 466         }
 467
 468         dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)];
 469         iip = (iic_t *)&immap->im_dprambase[dpaddr];
 470         iip->iic_rbptr = iip->iic_rbase;
 471         iip->iic_tbptr = iip->iic_tbase;
 472
 473         /* Enable I2C */
 474         debug("[I2C] Enabling I2C...\n");
 475         i2c->i2c_i2mod |= 0x01;
 476
 477         /* Begin transmission */
 478         i2c->i2c_i2com |= 0x80;
 479
 480         /* Loop until transmit & receive completed */
 481
 482         n = state->tx_idx;
 483
 484         if (n > 0) {
 485
 486                 txbd = ((I2C_BD *) state->txbd) - n;
 487                 for (i = 0; i < n; i++) {
 488                         txtimeo += TOUT_LOOP * txbd->length;
 489                         txbd++;
 490                 }
 491
 492                 txbd--;         /* wait until last in list is done */
 493
 494                 debug("[I2C] Transmitting...(txbd=0x%08lx)\n",
 495                         (ulong) txbd);
 496
 497                 udelay(START_DELAY_US); /* give it time to start */
 498                 while ((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) {
 499                         udelay(DELAY_US);
 500                         if (ctrlc())
 501                                 return -1;
 502                         __asm__ __volatile__("eieio");
 503                 }
 504         }
 505
 506         n = state->rx_idx;
 507
 508         if (txcnt < txtimeo && n > 0) {
 509
 510                 rxbd = ((I2C_BD *) state->rxbd) - n;
 511                 for (i = 0; i < n; i++) {
 512                         rxtimeo += TOUT_LOOP * rxbd->length;
 513                         rxbd++;
 514                 }
 515
 516                 rxbd--;         /* wait until last in list is done */
 517
 518                 debug("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong) rxbd);
 519
 520                 udelay(START_DELAY_US); /* give it time to start */
 521                 while ((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) {
 522                         udelay(DELAY_US);
 523                         if (ctrlc())
 524                                 return -1;
 525                         __asm__ __volatile__("eieio");
 526                 }
 527         }
 528
 529         /* Turn off I2C */
 530         i2c->i2c_i2mod &= ~0x01;
 531
 532         n = state->tx_idx;
 533
 534         if (n > 0) {
 535                 for (i = 0; i < n; i++) {
 536                         txbd = ((I2C_BD *) state->txbd) - (n - i);
 537                         b = txbd->status & BD_I2C_TX_ERR;
 538                         if (b != 0) {
 539                                 if (state->err_cb != NULL)
 540                                         (*state->err_cb) (I2CECB_TX_ERR | b,
 541                                                           i, state->cb_data);
 542                                 if (rc == 0)
 543                                         rc = I2CERR_IO_ERROR;
 544                         }
 545                 }
 546         }
 547
 548         n = state->rx_idx;
 549
 550         if (n > 0) {
 551                 for (i = 0; i < n; i++) {
 552                         rxbd = ((I2C_BD *) state->rxbd) - (n - i);
 553                         b = rxbd->status & BD_I2C_RX_ERR;
 554                         if (b != 0) {
 555                                 if (state->err_cb != NULL)
 556                                         (*state->err_cb) (I2CECB_RX_ERR | b,
 557                                                           i, state->cb_data);
 558                                 if (rc == 0)
 559                                         rc = I2CERR_IO_ERROR;
 560                         }
 561                 }
 562         }
 563
 564         if ((txtimeo > 0 && txcnt >= txtimeo) ||
 565             (rxtimeo > 0 && rxcnt >= rxtimeo)) {
 566                 if (state->err_cb != NULL)
 567                         (*state->err_cb) (I2CECB_TIMEOUT, -1, state->cb_data);
 568                 if (rc == 0)
 569                         rc = I2CERR_TIMEOUT;
 570         }
 571
 572         return rc;
 573 }
 574
 575 static void i2c_probe_callback(int flags, int xnum, void *data)
 576 {
 577         /*
 578          * the only acceptable errors are a transmit NAK or a receive
 579          * overrun - tx NAK means the device does not exist, rx OV
 580          * means the device must have responded to the slave address
 581          * even though the transfer failed
 582          */
 583         if (flags == (I2CECB_TX_ERR | I2CECB_TX_NAK))
 584                 *(int *) data |= 1;
 585         if (flags == (I2CECB_RX_ERR | I2CECB_RX_OV))
 586                 *(int *) data |= 2;
 587 }
 588
 589 int i2c_probe(uchar chip)
 590 {
 591         i2c_state_t state;
 592         int rc, err_flag;
 593         uchar buf[1];
 594
 595         i2c_newio(&state);
 596
 597         state.err_cb = i2c_probe_callback;
 598         state.cb_data = (void *) &err_flag;
 599         err_flag = 0;
 600
 601         rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1,
 602                          buf);
 603
 604         if (rc != 0)
 605                 return rc;      /* probe failed */
 606
 607         rc = i2c_doio(&state);
 608
 609         if (rc == 0)
 610                 return 0;       /* device exists - read succeeded */
 611
 612         if (rc == I2CERR_TIMEOUT)
 613                 return -1;      /* device does not exist - timeout */
 614
 615         if (rc != I2CERR_IO_ERROR || err_flag == 0)
 616                 return rc;      /* probe failed */
 617
 618         if (err_flag & 1)
 619                 return -1;      /* device does not exist - had transmit NAK */
 620
 621         return 0;               /* device exists - had receive overrun */
 622 }
 623
 624
 625 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 626 {
 627         i2c_state_t state;
 628         uchar xaddr[4];
 629         int rc;
 630
 631         xaddr[0] = (addr >> 24) & 0xFF;
 632         xaddr[1] = (addr >> 16) & 0xFF;
 633         xaddr[2] = (addr >> 8) & 0xFF;
 634         xaddr[3] = addr & 0xFF;
 635
 636 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 637         /*
 638          * EEPROM chips that implement "address overflow" are ones
 639          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
 640          * and the extra bits end up in the "chip address" bit slots.
 641          * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
 642          * chips.
 643          *
 644          * Note that we consider the length of the address field to still
 645          * be one byte because the extra address bits are hidden in the
 646          * chip address.
 647          */
 648         chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 649 #endif
 650
 651         i2c_newio(&state);
 652
 653         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
 654                       &xaddr[4 - alen]);
 655         if (rc != 0) {
 656                 printf("i2c_read: i2c_send failed (%d)\n", rc);
 657                 return 1;
 658         }
 659
 660         rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
 661         if (rc != 0) {
 662                 printf("i2c_read: i2c_receive failed (%d)\n", rc);
 663                 return 1;
 664         }
 665
 666         rc = i2c_doio(&state);
 667         if (rc != 0) {
 668                 printf("i2c_read: i2c_doio failed (%d)\n", rc);
 669                 return 1;
 670         }
 671         return 0;
 672 }
 673
 674 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 675 {
 676         i2c_state_t state;
 677         uchar xaddr[4];
 678         int rc;
 679
 680         xaddr[0] = (addr >> 24) & 0xFF;
 681         xaddr[1] = (addr >> 16) & 0xFF;
 682         xaddr[2] = (addr >> 8) & 0xFF;
 683         xaddr[3] = addr & 0xFF;
 684
 685 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 686         /*
 687          * EEPROM chips that implement "address overflow" are ones
 688          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
 689          * and the extra bits end up in the "chip address" bit slots.
 690          * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
 691          * chips.
 692          *
 693          * Note that we consider the length of the address field to still
 694          * be one byte because the extra address bits are hidden in the
 695          * chip address.
 696          */
 697         chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 698 #endif
 699
 700         i2c_newio(&state);
 701
 702         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
 703                       &xaddr[4 - alen]);
 704         if (rc != 0) {
 705                 printf("i2c_write: first i2c_send failed (%d)\n", rc);
 706                 return 1;
 707         }
 708
 709         rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
 710         if (rc != 0) {
 711                 printf("i2c_write: second i2c_send failed (%d)\n", rc);
 712                 return 1;
 713         }
 714
 715         rc = i2c_doio(&state);
 716         if (rc != 0) {
 717                 printf("i2c_write: i2c_doio failed (%d)\n", rc);
 718                 return 1;
 719         }
 720         return 0;
 721 }
 722
 723 #if defined(CONFIG_I2C_MULTI_BUS)
 724 /*
 725  * Functions for multiple I2C bus handling
 726  */
 727 unsigned int i2c_get_bus_num(void)
 728 {
 729         return i2c_bus_num;
 730 }
 731
 732 int i2c_set_bus_num(unsigned int bus)
 733 {
 734         if (bus >= CONFIG_SYS_MAX_I2C_BUS)
 735                 return -1;
 736         i2c_bus_num = bus;
 737         return 0;
 738 }
 739
 740 #endif /* CONFIG_I2C_MULTI_BUS */
 741 #endif /* CONFIG_HARD_I2C */