arch/powerpc/cpu/mpc8260/i2c.c

   1 /*
   2  * (C) Copyright 2000
   3  * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
   4  *
   5  * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   6  * Marius Groeger <mgroeger@sysgo.de>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28
  29 #if defined(CONFIG_HARD_I2C)
  30
  31 #include <asm/cpm_8260.h>
  32 #include <i2c.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #if defined(CONFIG_I2C_MULTI_BUS)
  37 static unsigned int i2c_bus_num __attribute__ ((section(".data"))) = 0;
  38 #endif /* CONFIG_I2C_MULTI_BUS */
  39
  40 /* uSec to wait between polls of the i2c */
  41 #define DELAY_US        100
  42 /* uSec to wait for the CPM to start processing the buffer */
  43 #define START_DELAY_US  1000
  44
  45 /*
  46  * tx/rx per-byte timeout: we delay DELAY_US uSec between polls so the
  47  * timeout will be (tx_length + rx_length) * DELAY_US * TOUT_LOOP
  48  */
  49 #define TOUT_LOOP 5
  50
  51 /*
  52  * Set default values
  53  */
  54 #ifndef CONFIG_SYS_I2C_SPEED
  55 #define CONFIG_SYS_I2C_SPEED    50000
  56 #endif
  57
  58
  59 typedef void (*i2c_ecb_t) (int, int, void *);   /* error callback function */
  60
  61 /* This structure keeps track of the bd and buffer space usage. */
  62 typedef struct i2c_state {
  63         int rx_idx;             /* index   to next free Rx BD */
  64         int tx_idx;             /* index   to next free Tx BD */
  65         void *rxbd;             /* pointer to next free Rx BD */
  66         void *txbd;             /* pointer to next free Tx BD */
  67         int tx_space;           /* number  of Tx bytes left   */
  68         unsigned char *tx_buf;  /* pointer to free Tx area    */
  69         i2c_ecb_t err_cb;       /* error callback function    */
  70         void *cb_data;          /* private data to be passed  */
  71 } i2c_state_t;
  72
  73 /* flags for i2c_send() and i2c_receive() */
  74 #define I2CF_ENABLE_SECONDARY   0x01    /* secondary_address is valid   */
  75 #define I2CF_START_COND         0x02    /* tx: generate start condition */
  76 #define I2CF_STOP_COND          0x04    /* tx: generate stop  condition */
  77
  78 /* return codes */
  79 #define I2CERR_NO_BUFFERS       1       /* no more BDs or buffer space  */
  80 #define I2CERR_MSG_TOO_LONG     2       /* tried to send/receive to much data */
  81 #define I2CERR_TIMEOUT          3       /* timeout in i2c_doio()        */
  82 #define I2CERR_QUEUE_EMPTY      4       /* i2c_doio called without send/rcv */
  83 #define I2CERR_IO_ERROR         5       /* had an error during comms    */
  84
  85 /* error callback flags */
  86 #define I2CECB_RX_ERR           0x10    /* this is a receive error      */
  87 #define     I2CECB_RX_OV        0x02    /* receive overrun error        */
  88 #define     I2CECB_RX_MASK      0x0f    /* mask for error bits          */
  89 #define I2CECB_TX_ERR           0x20    /* this is a transmit error     */
  90 #define     I2CECB_TX_CL        0x01    /* transmit collision error     */
  91 #define     I2CECB_TX_UN        0x02    /* transmit underflow error     */
  92 #define     I2CECB_TX_NAK       0x04    /* transmit no ack error        */
  93 #define     I2CECB_TX_MASK      0x0f    /* mask for error bits          */
  94 #define I2CECB_TIMEOUT          0x40    /* this is a timeout error      */
  95
  96 #define ERROR_I2C_NONE          0
  97 #define ERROR_I2C_LENGTH        1
  98
  99 #define I2C_WRITE_BIT           0x00
 100 #define I2C_READ_BIT            0x01
 101
 102 #define I2C_RXTX_LEN    128     /* maximum tx/rx buffer length */
 103
 104
 105 #define NUM_RX_BDS 4
 106 #define NUM_TX_BDS 4
 107 #define MAX_TX_SPACE 256
 108
 109 typedef struct I2C_BD {
 110         unsigned short status;
 111         unsigned short length;
 112         unsigned char *addr;
 113 } I2C_BD;
 114
 115 #define BD_I2C_TX_START 0x0400  /* special status for i2c: Start condition */
 116
 117 #define BD_I2C_TX_CL    0x0001  /* collision error */
 118 #define BD_I2C_TX_UN    0x0002  /* underflow error */
 119 #define BD_I2C_TX_NAK   0x0004  /* no acknowledge error */
 120 #define BD_I2C_TX_ERR   (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
 121
 122 #define BD_I2C_RX_ERR   BD_SC_OV
 123
 124 /*
 125  * Returns the best value of I2BRG to meet desired clock speed of I2C with
 126  * input parameters (clock speed, filter, and predivider value).
 127  * It returns computer speed value and the difference between it and desired
 128  * speed.
 129  */
 130 static inline int
 131 i2c_roundrate(int hz, int speed, int filter, int modval,
 132               int *brgval, int *totspeed)
 133 {
 134         int moddiv = 1 << (5 - (modval & 3)), brgdiv, div;
 135
 136         debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
 137                 hz, speed, filter, modval);
 138
 139         div = moddiv * speed;
 140         brgdiv = (hz + div - 1) / div;
 141
 142         debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv);
 143
 144         *brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter);
 145
 146         if ((*brgval < 0) || (*brgval > 255)) {
 147                 debug("\t\trejected brgval=%d\n", *brgval);
 148                 return -1;
 149         }
 150
 151         brgdiv = 2 * (*brgval + 3 + (2 * filter));
 152         div = moddiv * brgdiv;
 153         *totspeed = hz / div;
 154
 155         debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed);
 156
 157         return 0;
 158 }
 159
 160 /*
 161  * Sets the I2C clock predivider and divider to meet required clock speed.
 162  */
 163 static int i2c_setrate(int hz, int speed)
 164 {
 165         immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 166         volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
 167         int     brgval,
 168                 modval, /* 0-3 */
 169                 bestspeed_diff = speed,
 170                 bestspeed_brgval = 0,
 171                 bestspeed_modval = 0,
 172                 bestspeed_filter = 0,
 173                 totspeed,
 174                 filter = 0;     /* Use this fixed value */
 175
 176         for (modval = 0; modval < 4; modval++) {
 177                 if (i2c_roundrate(hz, speed, filter, modval, &brgval, &totspeed)
 178                     == 0) {
 179                         int diff = speed - totspeed;
 180
 181                         if ((diff >= 0) && (diff < bestspeed_diff)) {
 182                                 bestspeed_diff = diff;
 183                                 bestspeed_modval = modval;
 184                                 bestspeed_brgval = brgval;
 185                                 bestspeed_filter = filter;
 186                         }
 187                 }
 188         }
 189
 190         debug("[I2C] Best is:\n");
 191         debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
 192                 hz, speed, bestspeed_filter, bestspeed_modval, bestspeed_brgval,
 193                 bestspeed_diff);
 194
 195         i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) |
 196                 (bestspeed_filter << 3);
 197         i2c->i2c_i2brg = bestspeed_brgval & 0xff;
 198
 199         debug("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod,
 200                 i2c->i2c_i2brg);
 201
 202         return 1;
 203 }
 204
 205 void i2c_init(int speed, int slaveadd)
 206 {
 207         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 208         volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
 209         volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
 210         volatile iic_t *iip;
 211         ulong rbase, tbase;
 212         volatile I2C_BD *rxbd, *txbd;
 213         uint dpaddr;
 214
 215 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 216         /*
 217          * call board specific i2c bus reset routine before accessing the
 218          * environment, which might be in a chip on that bus. For details
 219          * about this problem see doc/I2C_Edge_Conditions.
 220          */
 221         i2c_init_board();
 222 #endif
 223
 224         dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)];
 225         if (dpaddr == 0) {
 226                 /* need to allocate dual port ram */
 227                 dpaddr = m8260_cpm_dpalloc(64 +
 228                                         (NUM_RX_BDS * sizeof(I2C_BD)) +
 229                                         (NUM_TX_BDS * sizeof(I2C_BD)) +
 230                                         MAX_TX_SPACE, 64);
 231                 immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)] =
 232                         dpaddr;
 233         }
 234
 235         /*
 236          * initialise data in dual port ram:
 237          *
 238          *        dpaddr -> parameter ram (64 bytes)
 239          *         rbase -> rx BD         (NUM_RX_BDS * sizeof(I2C_BD) bytes)
 240          *         tbase -> tx BD         (NUM_TX_BDS * sizeof(I2C_BD) bytes)
 241          *                  tx buffer     (MAX_TX_SPACE bytes)
 242          */
 243
 244         iip = (iic_t *)&immap->im_dprambase[dpaddr];
 245         memset((void *)iip, 0, sizeof(iic_t));
 246
 247         rbase = dpaddr + 64;
 248         tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
 249
 250         /* Disable interrupts */
 251         i2c->i2c_i2mod = 0x00;
 252         i2c->i2c_i2cmr = 0x00;
 253         i2c->i2c_i2cer = 0xff;
 254         i2c->i2c_i2add = slaveadd;
 255
 256         /*
 257          * Set the I2C BRG Clock division factor from desired i2c rate
 258          * and current CPU rate (we assume sccr dfbgr field is 0;
 259          * divide BRGCLK by 1)
 260          */
 261         debug("[I2C] Setting rate...\n");
 262         i2c_setrate(gd->arch.brg_clk, CONFIG_SYS_I2C_SPEED);
 263
 264         /* Set I2C controller in master mode */
 265         i2c->i2c_i2com = 0x01;
 266
 267         /* Initialize Tx/Rx parameters */
 268         iip->iic_rbase = rbase;
 269         iip->iic_tbase = tbase;
 270         rxbd = (I2C_BD *)((unsigned char *) &immap->
 271                         im_dprambase[iip->iic_rbase]);
 272         txbd = (I2C_BD *)((unsigned char *) &immap->
 273                         im_dprambase[iip->iic_tbase]);
 274
 275         debug("[I2C] rbase = %04x\n", iip->iic_rbase);
 276         debug("[I2C] tbase = %04x\n", iip->iic_tbase);
 277         debug("[I2C] rxbd = %08x\n", (int) rxbd);
 278         debug("[I2C] txbd = %08x\n", (int) txbd);
 279
 280         /* Set big endian byte order */
 281         iip->iic_tfcr = 0x10;
 282         iip->iic_rfcr = 0x10;
 283
 284         /* Set maximum receive size. */
 285         iip->iic_mrblr = I2C_RXTX_LEN;
 286
 287         cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE,
 288                                 CPM_CR_I2C_SBLOCK,
 289                                 0x00, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 290         do {
 291                 __asm__ __volatile__("eieio");
 292         } while (cp->cp_cpcr & CPM_CR_FLG);
 293
 294         /* Clear events and interrupts */
 295         i2c->i2c_i2cer = 0xff;
 296         i2c->i2c_i2cmr = 0x00;
 297 }
 298
 299 static
 300 void i2c_newio(i2c_state_t *state)
 301 {
 302         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 303         volatile iic_t *iip;
 304         uint dpaddr;
 305
 306         debug("[I2C] i2c_newio\n");
 307
 308         dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)];
 309         iip = (iic_t *)&immap->im_dprambase[dpaddr];
 310         state->rx_idx = 0;
 311         state->tx_idx = 0;
 312         state->rxbd = (void *)&immap->im_dprambase[iip->iic_rbase];
 313         state->txbd = (void *)&immap->im_dprambase[iip->iic_tbase];
 314         state->tx_space = MAX_TX_SPACE;
 315         state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
 316         state->err_cb = NULL;
 317         state->cb_data = NULL;
 318
 319         debug("[I2C] rxbd = %08x\n", (int)state->rxbd);
 320         debug("[I2C] txbd = %08x\n", (int)state->txbd);
 321         debug("[I2C] tx_buf = %08x\n", (int)state->tx_buf);
 322
 323         /* clear the buffer memory */
 324         memset((char *) state->tx_buf, 0, MAX_TX_SPACE);
 325 }
 326
 327 static
 328 int i2c_send(i2c_state_t *state,
 329              unsigned char address,
 330              unsigned char secondary_address,
 331              unsigned int flags, unsigned short size, unsigned char *dataout)
 332 {
 333         volatile I2C_BD *txbd;
 334         int i, j;
 335
 336         debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
 337                 address, secondary_address, flags, size);
 338
 339         /* trying to send message larger than BD */
 340         if (size > I2C_RXTX_LEN)
 341                 return I2CERR_MSG_TOO_LONG;
 342
 343         /* no more free bds */
 344         if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
 345                 return I2CERR_NO_BUFFERS;
 346
 347         txbd = (I2C_BD *)state->txbd;
 348         txbd->addr = state->tx_buf;
 349
 350         debug("[I2C] txbd = %08x\n", (int) txbd);
 351
 352         if (flags & I2CF_START_COND) {
 353                 debug("[I2C] Formatting addresses...\n");
 354                 if (flags & I2CF_ENABLE_SECONDARY) {
 355                         /* Length of message plus dest addresses */
 356                         txbd->length = size + 2;
 357                         txbd->addr[0] = address << 1;
 358                         txbd->addr[1] = secondary_address;
 359                         i = 2;
 360                 } else {
 361                         /* Length of message plus dest address */
 362                         txbd->length = size + 1;
 363                         /* Write destination address to BD */
 364                         txbd->addr[0] = address << 1;
 365                         i = 1;
 366                 }
 367         } else {
 368                 txbd->length = size;    /* Length of message */
 369                 i = 0;
 370         }
 371
 372         /* set up txbd */
 373         txbd->status = BD_SC_READY;
 374         if (flags & I2CF_START_COND)
 375                 txbd->status |= BD_I2C_TX_START;
 376         if (flags & I2CF_STOP_COND)
 377                 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 378
 379         /* Copy data to send into buffer */
 380         debug("[I2C] copy data...\n");
 381         for (j = 0; j < size; i++, j++)
 382                 txbd->addr[i] = dataout[j];
 383
 384         debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 385                 txbd->length, txbd->status, txbd->addr[0], txbd->addr[1]);
 386
 387         /* advance state */
 388         state->tx_buf += txbd->length;
 389         state->tx_space -= txbd->length;
 390         state->tx_idx++;
 391         state->txbd = (void *) (txbd + 1);
 392
 393         return 0;
 394 }
 395
 396 static
 397 int i2c_receive(i2c_state_t *state,
 398                 unsigned char address,
 399                 unsigned char secondary_address,
 400                 unsigned int flags,
 401                 unsigned short size_to_expect, unsigned char *datain)
 402 {
 403         volatile I2C_BD *rxbd, *txbd;
 404
 405         debug("[I2C] i2c_receive %02d %02d %02d\n", address,
 406                 secondary_address, flags);
 407
 408         /* Expected to receive too much */
 409         if (size_to_expect > I2C_RXTX_LEN)
 410                 return I2CERR_MSG_TOO_LONG;
 411
 412         /* no more free bds */
 413         if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
 414             || state->tx_space < 2)
 415                 return I2CERR_NO_BUFFERS;
 416
 417         rxbd = (I2C_BD *) state->rxbd;
 418         txbd = (I2C_BD *) state->txbd;
 419
 420         debug("[I2C] rxbd = %08x\n", (int) rxbd);
 421         debug("[I2C] txbd = %08x\n", (int) txbd);
 422
 423         txbd->addr = state->tx_buf;
 424
 425         /* set up TXBD for destination address */
 426         if (flags & I2CF_ENABLE_SECONDARY) {
 427                 txbd->length = 2;
 428                 txbd->addr[0] = address << 1;   /* Write data */
 429                 txbd->addr[1] = secondary_address;      /* Internal address */
 430                 txbd->status = BD_SC_READY;
 431         } else {
 432                 txbd->length = 1 + size_to_expect;
 433                 txbd->addr[0] = (address << 1) | 0x01;
 434                 txbd->status = BD_SC_READY;
 435                 memset(&txbd->addr[1], 0, txbd->length);
 436         }
 437
 438         /* set up rxbd for reception */
 439         rxbd->status = BD_SC_EMPTY;
 440         rxbd->length = size_to_expect;
 441         rxbd->addr = datain;
 442
 443         txbd->status |= BD_I2C_TX_START;
 444         if (flags & I2CF_STOP_COND) {
 445                 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 446                 rxbd->status |= BD_SC_WRAP;
 447         }
 448
 449         debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 450                 txbd->length, txbd->status, txbd->addr[0], txbd->addr[1]);
 451         debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 452                 rxbd->length, rxbd->status, rxbd->addr[0], rxbd->addr[1]);
 453
 454         /* advance state */
 455         state->tx_buf += txbd->length;
 456         state->tx_space -= txbd->length;
 457         state->tx_idx++;
 458         state->txbd = (void *) (txbd + 1);
 459         state->rx_idx++;
 460         state->rxbd = (void *) (rxbd + 1);
 461
 462         return 0;
 463 }
 464
 465
 466 static
 467 int i2c_doio(i2c_state_t *state)
 468 {
 469         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 470         volatile iic_t *iip;
 471         volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
 472         volatile I2C_BD *txbd, *rxbd;
 473         int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
 474         uint dpaddr;
 475
 476         debug("[I2C] i2c_doio\n");
 477
 478         if (state->tx_idx <= 0 && state->rx_idx <= 0) {
 479                 debug("[I2C] No I/O is queued\n");
 480                 return I2CERR_QUEUE_EMPTY;
 481         }
 482
 483         dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)];
 484         iip = (iic_t *)&immap->im_dprambase[dpaddr];
 485         iip->iic_rbptr = iip->iic_rbase;
 486         iip->iic_tbptr = iip->iic_tbase;
 487
 488         /* Enable I2C */
 489         debug("[I2C] Enabling I2C...\n");
 490         i2c->i2c_i2mod |= 0x01;
 491
 492         /* Begin transmission */
 493         i2c->i2c_i2com |= 0x80;
 494
 495         /* Loop until transmit & receive completed */
 496
 497         n = state->tx_idx;
 498
 499         if (n > 0) {
 500
 501                 txbd = ((I2C_BD *) state->txbd) - n;
 502                 for (i = 0; i < n; i++) {
 503                         txtimeo += TOUT_LOOP * txbd->length;
 504                         txbd++;
 505                 }
 506
 507                 txbd--;         /* wait until last in list is done */
 508
 509                 debug("[I2C] Transmitting...(txbd=0x%08lx)\n",
 510                         (ulong) txbd);
 511
 512                 udelay(START_DELAY_US); /* give it time to start */
 513                 while ((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) {
 514                         udelay(DELAY_US);
 515                         if (ctrlc())
 516                                 return -1;
 517                         __asm__ __volatile__("eieio");
 518                 }
 519         }
 520
 521         n = state->rx_idx;
 522
 523         if (txcnt < txtimeo && n > 0) {
 524
 525                 rxbd = ((I2C_BD *) state->rxbd) - n;
 526                 for (i = 0; i < n; i++) {
 527                         rxtimeo += TOUT_LOOP * rxbd->length;
 528                         rxbd++;
 529                 }
 530
 531                 rxbd--;         /* wait until last in list is done */
 532
 533                 debug("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong) rxbd);
 534
 535                 udelay(START_DELAY_US); /* give it time to start */
 536                 while ((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) {
 537                         udelay(DELAY_US);
 538                         if (ctrlc())
 539                                 return -1;
 540                         __asm__ __volatile__("eieio");
 541                 }
 542         }
 543
 544         /* Turn off I2C */
 545         i2c->i2c_i2mod &= ~0x01;
 546
 547         n = state->tx_idx;
 548
 549         if (n > 0) {
 550                 for (i = 0; i < n; i++) {
 551                         txbd = ((I2C_BD *) state->txbd) - (n - i);
 552                         b = txbd->status & BD_I2C_TX_ERR;
 553                         if (b != 0) {
 554                                 if (state->err_cb != NULL)
 555                                         (*state->err_cb) (I2CECB_TX_ERR | b,
 556                                                           i, state->cb_data);
 557                                 if (rc == 0)
 558                                         rc = I2CERR_IO_ERROR;
 559                         }
 560                 }
 561         }
 562
 563         n = state->rx_idx;
 564
 565         if (n > 0) {
 566                 for (i = 0; i < n; i++) {
 567                         rxbd = ((I2C_BD *) state->rxbd) - (n - i);
 568                         b = rxbd->status & BD_I2C_RX_ERR;
 569                         if (b != 0) {
 570                                 if (state->err_cb != NULL)
 571                                         (*state->err_cb) (I2CECB_RX_ERR | b,
 572                                                           i, state->cb_data);
 573                                 if (rc == 0)
 574                                         rc = I2CERR_IO_ERROR;
 575                         }
 576                 }
 577         }
 578
 579         if ((txtimeo > 0 && txcnt >= txtimeo) ||
 580             (rxtimeo > 0 && rxcnt >= rxtimeo)) {
 581                 if (state->err_cb != NULL)
 582                         (*state->err_cb) (I2CECB_TIMEOUT, -1, state->cb_data);
 583                 if (rc == 0)
 584                         rc = I2CERR_TIMEOUT;
 585         }
 586
 587         return rc;
 588 }
 589
 590 static void i2c_probe_callback(int flags, int xnum, void *data)
 591 {
 592         /*
 593          * the only acceptable errors are a transmit NAK or a receive
 594          * overrun - tx NAK means the device does not exist, rx OV
 595          * means the device must have responded to the slave address
 596          * even though the transfer failed
 597          */
 598         if (flags == (I2CECB_TX_ERR | I2CECB_TX_NAK))
 599                 *(int *) data |= 1;
 600         if (flags == (I2CECB_RX_ERR | I2CECB_RX_OV))
 601                 *(int *) data |= 2;
 602 }
 603
 604 int i2c_probe(uchar chip)
 605 {
 606         i2c_state_t state;
 607         int rc, err_flag;
 608         uchar buf[1];
 609
 610         i2c_newio(&state);
 611
 612         state.err_cb = i2c_probe_callback;
 613         state.cb_data = (void *) &err_flag;
 614         err_flag = 0;
 615
 616         rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1,
 617                          buf);
 618
 619         if (rc != 0)
 620                 return rc;      /* probe failed */
 621
 622         rc = i2c_doio(&state);
 623
 624         if (rc == 0)
 625                 return 0;       /* device exists - read succeeded */
 626
 627         if (rc == I2CERR_TIMEOUT)
 628                 return -1;      /* device does not exist - timeout */
 629
 630         if (rc != I2CERR_IO_ERROR || err_flag == 0)
 631                 return rc;      /* probe failed */
 632
 633         if (err_flag & 1)
 634                 return -1;      /* device does not exist - had transmit NAK */
 635
 636         return 0;               /* device exists - had receive overrun */
 637 }
 638
 639
 640 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 641 {
 642         i2c_state_t state;
 643         uchar xaddr[4];
 644         int rc;
 645
 646         xaddr[0] = (addr >> 24) & 0xFF;
 647         xaddr[1] = (addr >> 16) & 0xFF;
 648         xaddr[2] = (addr >> 8) & 0xFF;
 649         xaddr[3] = addr & 0xFF;
 650
 651 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 652         /*
 653          * EEPROM chips that implement "address overflow" are ones
 654          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
 655          * and the extra bits end up in the "chip address" bit slots.
 656          * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
 657          * chips.
 658          *
 659          * Note that we consider the length of the address field to still
 660          * be one byte because the extra address bits are hidden in the
 661          * chip address.
 662          */
 663         chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 664 #endif
 665
 666         i2c_newio(&state);
 667
 668         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
 669                       &xaddr[4 - alen]);
 670         if (rc != 0) {
 671                 printf("i2c_read: i2c_send failed (%d)\n", rc);
 672                 return 1;
 673         }
 674
 675         rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
 676         if (rc != 0) {
 677                 printf("i2c_read: i2c_receive failed (%d)\n", rc);
 678                 return 1;
 679         }
 680
 681         rc = i2c_doio(&state);
 682         if (rc != 0) {
 683                 printf("i2c_read: i2c_doio failed (%d)\n", rc);
 684                 return 1;
 685         }
 686         return 0;
 687 }
 688
 689 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 690 {
 691         i2c_state_t state;
 692         uchar xaddr[4];
 693         int rc;
 694
 695         xaddr[0] = (addr >> 24) & 0xFF;
 696         xaddr[1] = (addr >> 16) & 0xFF;
 697         xaddr[2] = (addr >> 8) & 0xFF;
 698         xaddr[3] = addr & 0xFF;
 699
 700 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 701         /*
 702          * EEPROM chips that implement "address overflow" are ones
 703          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
 704          * and the extra bits end up in the "chip address" bit slots.
 705          * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
 706          * chips.
 707          *
 708          * Note that we consider the length of the address field to still
 709          * be one byte because the extra address bits are hidden in the
 710          * chip address.
 711          */
 712         chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 713 #endif
 714
 715         i2c_newio(&state);
 716
 717         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
 718                       &xaddr[4 - alen]);
 719         if (rc != 0) {
 720                 printf("i2c_write: first i2c_send failed (%d)\n", rc);
 721                 return 1;
 722         }
 723
 724         rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
 725         if (rc != 0) {
 726                 printf("i2c_write: second i2c_send failed (%d)\n", rc);
 727                 return 1;
 728         }
 729
 730         rc = i2c_doio(&state);
 731         if (rc != 0) {
 732                 printf("i2c_write: i2c_doio failed (%d)\n", rc);
 733                 return 1;
 734         }
 735         return 0;
 736 }
 737
 738 #if defined(CONFIG_I2C_MULTI_BUS)
 739 /*
 740  * Functions for multiple I2C bus handling
 741  */
 742 unsigned int i2c_get_bus_num(void)
 743 {
 744         return i2c_bus_num;
 745 }
 746
 747 int i2c_set_bus_num(unsigned int bus)
 748 {
 749 #if defined(CONFIG_I2C_MUX)
 750         if (bus < CONFIG_SYS_MAX_I2C_BUS) {
 751                 i2c_bus_num = bus;
 752         } else {
 753                 int ret;
 754
 755                 ret = i2x_mux_select_mux(bus);
 756                 if (ret == 0)
 757                         i2c_bus_num = bus;
 758                 else
 759                         return ret;
 760         }
 761 #else
 762         if (bus >= CONFIG_SYS_MAX_I2C_BUS)
 763                 return -1;
 764         i2c_bus_num = bus;
 765 #endif
 766         return 0;
 767 }
 768
 769 #endif /* CONFIG_I2C_MULTI_BUS */
 770 #endif /* CONFIG_HARD_I2C */