3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
5 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
8 * SPDX-License-Identifier: GPL-2.0+
13 #if defined(CONFIG_HARD_I2C)
15 #include <asm/cpm_8260.h>
18 DECLARE_GLOBAL_DATA_PTR
;
20 #if defined(CONFIG_I2C_MULTI_BUS)
21 static unsigned int i2c_bus_num
__attribute__ ((section(".data"))) = 0;
22 #endif /* CONFIG_I2C_MULTI_BUS */
24 /* uSec to wait between polls of the i2c */
26 /* uSec to wait for the CPM to start processing the buffer */
27 #define START_DELAY_US 1000
30 * tx/rx per-byte timeout: we delay DELAY_US uSec between polls so the
31 * timeout will be (tx_length + rx_length) * DELAY_US * TOUT_LOOP
38 #ifndef CONFIG_SYS_I2C_SPEED
39 #define CONFIG_SYS_I2C_SPEED 50000
43 typedef void (*i2c_ecb_t
) (int, int, void *); /* error callback function */
45 /* This structure keeps track of the bd and buffer space usage. */
46 typedef struct i2c_state
{
47 int rx_idx
; /* index to next free Rx BD */
48 int tx_idx
; /* index to next free Tx BD */
49 void *rxbd
; /* pointer to next free Rx BD */
50 void *txbd
; /* pointer to next free Tx BD */
51 int tx_space
; /* number of Tx bytes left */
52 unsigned char *tx_buf
; /* pointer to free Tx area */
53 i2c_ecb_t err_cb
; /* error callback function */
54 void *cb_data
; /* private data to be passed */
57 /* flags for i2c_send() and i2c_receive() */
58 #define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
59 #define I2CF_START_COND 0x02 /* tx: generate start condition */
60 #define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
63 #define I2CERR_NO_BUFFERS 1 /* no more BDs or buffer space */
64 #define I2CERR_MSG_TOO_LONG 2 /* tried to send/receive to much data */
65 #define I2CERR_TIMEOUT 3 /* timeout in i2c_doio() */
66 #define I2CERR_QUEUE_EMPTY 4 /* i2c_doio called without send/rcv */
67 #define I2CERR_IO_ERROR 5 /* had an error during comms */
69 /* error callback flags */
70 #define I2CECB_RX_ERR 0x10 /* this is a receive error */
71 #define I2CECB_RX_OV 0x02 /* receive overrun error */
72 #define I2CECB_RX_MASK 0x0f /* mask for error bits */
73 #define I2CECB_TX_ERR 0x20 /* this is a transmit error */
74 #define I2CECB_TX_CL 0x01 /* transmit collision error */
75 #define I2CECB_TX_UN 0x02 /* transmit underflow error */
76 #define I2CECB_TX_NAK 0x04 /* transmit no ack error */
77 #define I2CECB_TX_MASK 0x0f /* mask for error bits */
78 #define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
80 #define ERROR_I2C_NONE 0
81 #define ERROR_I2C_LENGTH 1
83 #define I2C_WRITE_BIT 0x00
84 #define I2C_READ_BIT 0x01
86 #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
91 #define MAX_TX_SPACE 256
93 typedef struct I2C_BD
{
94 unsigned short status
;
95 unsigned short length
;
99 #define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
101 #define BD_I2C_TX_CL 0x0001 /* collision error */
102 #define BD_I2C_TX_UN 0x0002 /* underflow error */
103 #define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
104 #define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
106 #define BD_I2C_RX_ERR BD_SC_OV
109 * Returns the best value of I2BRG to meet desired clock speed of I2C with
110 * input parameters (clock speed, filter, and predivider value).
111 * It returns computer speed value and the difference between it and desired
115 i2c_roundrate(int hz
, int speed
, int filter
, int modval
,
116 int *brgval
, int *totspeed
)
118 int moddiv
= 1 << (5 - (modval
& 3)), brgdiv
, div
;
120 debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
121 hz
, speed
, filter
, modval
);
123 div
= moddiv
* speed
;
124 brgdiv
= (hz
+ div
- 1) / div
;
126 debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv
, brgdiv
);
128 *brgval
= ((brgdiv
+ 1) / 2) - 3 - (2 * filter
);
130 if ((*brgval
< 0) || (*brgval
> 255)) {
131 debug("\t\trejected brgval=%d\n", *brgval
);
135 brgdiv
= 2 * (*brgval
+ 3 + (2 * filter
));
136 div
= moddiv
* brgdiv
;
137 *totspeed
= hz
/ div
;
139 debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval
, *totspeed
);
145 * Sets the I2C clock predivider and divider to meet required clock speed.
147 static int i2c_setrate(int hz
, int speed
)
149 immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
150 volatile i2c8260_t
*i2c
= (i2c8260_t
*)&immap
->im_i2c
;
153 bestspeed_diff
= speed
,
154 bestspeed_brgval
= 0,
155 bestspeed_modval
= 0,
156 bestspeed_filter
= 0,
158 filter
= 0; /* Use this fixed value */
160 for (modval
= 0; modval
< 4; modval
++) {
161 if (i2c_roundrate(hz
, speed
, filter
, modval
, &brgval
, &totspeed
)
163 int diff
= speed
- totspeed
;
165 if ((diff
>= 0) && (diff
< bestspeed_diff
)) {
166 bestspeed_diff
= diff
;
167 bestspeed_modval
= modval
;
168 bestspeed_brgval
= brgval
;
169 bestspeed_filter
= filter
;
174 debug("[I2C] Best is:\n");
175 debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
176 hz
, speed
, bestspeed_filter
, bestspeed_modval
, bestspeed_brgval
,
179 i2c
->i2c_i2mod
|= ((bestspeed_modval
& 3) << 1) |
180 (bestspeed_filter
<< 3);
181 i2c
->i2c_i2brg
= bestspeed_brgval
& 0xff;
183 debug("[I2C] i2mod=%08x i2brg=%08x\n", i2c
->i2c_i2mod
,
189 void i2c_init(int speed
, int slaveadd
)
191 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
192 volatile cpm8260_t
*cp
= (cpm8260_t
*)&immap
->im_cpm
;
193 volatile i2c8260_t
*i2c
= (i2c8260_t
*)&immap
->im_i2c
;
196 volatile I2C_BD
*rxbd
, *txbd
;
199 #ifdef CONFIG_SYS_I2C_INIT_BOARD
201 * call board specific i2c bus reset routine before accessing the
202 * environment, which might be in a chip on that bus. For details
203 * about this problem see doc/I2C_Edge_Conditions.
208 dpaddr
= immap
->im_dprambase16
[PROFF_I2C_BASE
/ sizeof(u16
)];
210 /* need to allocate dual port ram */
211 dpaddr
= m8260_cpm_dpalloc(64 +
212 (NUM_RX_BDS
* sizeof(I2C_BD
)) +
213 (NUM_TX_BDS
* sizeof(I2C_BD
)) +
215 immap
->im_dprambase16
[PROFF_I2C_BASE
/ sizeof(u16
)] =
220 * initialise data in dual port ram:
222 * dpaddr -> parameter ram (64 bytes)
223 * rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
224 * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
225 * tx buffer (MAX_TX_SPACE bytes)
228 iip
= (iic_t
*)&immap
->im_dprambase
[dpaddr
];
229 memset((void *)iip
, 0, sizeof(iic_t
));
232 tbase
= rbase
+ NUM_RX_BDS
* sizeof(I2C_BD
);
234 /* Disable interrupts */
235 i2c
->i2c_i2mod
= 0x00;
236 i2c
->i2c_i2cmr
= 0x00;
237 i2c
->i2c_i2cer
= 0xff;
238 i2c
->i2c_i2add
= slaveadd
;
241 * Set the I2C BRG Clock division factor from desired i2c rate
242 * and current CPU rate (we assume sccr dfbgr field is 0;
243 * divide BRGCLK by 1)
245 debug("[I2C] Setting rate...\n");
246 i2c_setrate(gd
->arch
.brg_clk
, CONFIG_SYS_I2C_SPEED
);
248 /* Set I2C controller in master mode */
249 i2c
->i2c_i2com
= 0x01;
251 /* Initialize Tx/Rx parameters */
252 iip
->iic_rbase
= rbase
;
253 iip
->iic_tbase
= tbase
;
254 rxbd
= (I2C_BD
*)((unsigned char *) &immap
->
255 im_dprambase
[iip
->iic_rbase
]);
256 txbd
= (I2C_BD
*)((unsigned char *) &immap
->
257 im_dprambase
[iip
->iic_tbase
]);
259 debug("[I2C] rbase = %04x\n", iip
->iic_rbase
);
260 debug("[I2C] tbase = %04x\n", iip
->iic_tbase
);
261 debug("[I2C] rxbd = %08x\n", (int) rxbd
);
262 debug("[I2C] txbd = %08x\n", (int) txbd
);
264 /* Set big endian byte order */
265 iip
->iic_tfcr
= 0x10;
266 iip
->iic_rfcr
= 0x10;
268 /* Set maximum receive size. */
269 iip
->iic_mrblr
= I2C_RXTX_LEN
;
271 cp
->cp_cpcr
= mk_cr_cmd(CPM_CR_I2C_PAGE
,
273 0x00, CPM_CR_INIT_TRX
) | CPM_CR_FLG
;
275 __asm__
__volatile__("eieio");
276 } while (cp
->cp_cpcr
& CPM_CR_FLG
);
278 /* Clear events and interrupts */
279 i2c
->i2c_i2cer
= 0xff;
280 i2c
->i2c_i2cmr
= 0x00;
284 void i2c_newio(i2c_state_t
*state
)
286 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
290 debug("[I2C] i2c_newio\n");
292 dpaddr
= immap
->im_dprambase16
[PROFF_I2C_BASE
/ sizeof(u16
)];
293 iip
= (iic_t
*)&immap
->im_dprambase
[dpaddr
];
296 state
->rxbd
= (void *)&immap
->im_dprambase
[iip
->iic_rbase
];
297 state
->txbd
= (void *)&immap
->im_dprambase
[iip
->iic_tbase
];
298 state
->tx_space
= MAX_TX_SPACE
;
299 state
->tx_buf
= (uchar
*)state
->txbd
+ NUM_TX_BDS
* sizeof(I2C_BD
);
300 state
->err_cb
= NULL
;
301 state
->cb_data
= NULL
;
303 debug("[I2C] rxbd = %08x\n", (int)state
->rxbd
);
304 debug("[I2C] txbd = %08x\n", (int)state
->txbd
);
305 debug("[I2C] tx_buf = %08x\n", (int)state
->tx_buf
);
307 /* clear the buffer memory */
308 memset((char *) state
->tx_buf
, 0, MAX_TX_SPACE
);
312 int i2c_send(i2c_state_t
*state
,
313 unsigned char address
,
314 unsigned char secondary_address
,
315 unsigned int flags
, unsigned short size
, unsigned char *dataout
)
317 volatile I2C_BD
*txbd
;
320 debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
321 address
, secondary_address
, flags
, size
);
323 /* trying to send message larger than BD */
324 if (size
> I2C_RXTX_LEN
)
325 return I2CERR_MSG_TOO_LONG
;
327 /* no more free bds */
328 if (state
->tx_idx
>= NUM_TX_BDS
|| state
->tx_space
< (2 + size
))
329 return I2CERR_NO_BUFFERS
;
331 txbd
= (I2C_BD
*)state
->txbd
;
332 txbd
->addr
= state
->tx_buf
;
334 debug("[I2C] txbd = %08x\n", (int) txbd
);
336 if (flags
& I2CF_START_COND
) {
337 debug("[I2C] Formatting addresses...\n");
338 if (flags
& I2CF_ENABLE_SECONDARY
) {
339 /* Length of message plus dest addresses */
340 txbd
->length
= size
+ 2;
341 txbd
->addr
[0] = address
<< 1;
342 txbd
->addr
[1] = secondary_address
;
345 /* Length of message plus dest address */
346 txbd
->length
= size
+ 1;
347 /* Write destination address to BD */
348 txbd
->addr
[0] = address
<< 1;
352 txbd
->length
= size
; /* Length of message */
357 txbd
->status
= BD_SC_READY
;
358 if (flags
& I2CF_START_COND
)
359 txbd
->status
|= BD_I2C_TX_START
;
360 if (flags
& I2CF_STOP_COND
)
361 txbd
->status
|= BD_SC_LAST
| BD_SC_WRAP
;
363 /* Copy data to send into buffer */
364 debug("[I2C] copy data...\n");
365 for (j
= 0; j
< size
; i
++, j
++)
366 txbd
->addr
[i
] = dataout
[j
];
368 debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
369 txbd
->length
, txbd
->status
, txbd
->addr
[0], txbd
->addr
[1]);
372 state
->tx_buf
+= txbd
->length
;
373 state
->tx_space
-= txbd
->length
;
375 state
->txbd
= (void *) (txbd
+ 1);
381 int i2c_receive(i2c_state_t
*state
,
382 unsigned char address
,
383 unsigned char secondary_address
,
385 unsigned short size_to_expect
, unsigned char *datain
)
387 volatile I2C_BD
*rxbd
, *txbd
;
389 debug("[I2C] i2c_receive %02d %02d %02d\n", address
,
390 secondary_address
, flags
);
392 /* Expected to receive too much */
393 if (size_to_expect
> I2C_RXTX_LEN
)
394 return I2CERR_MSG_TOO_LONG
;
396 /* no more free bds */
397 if (state
->tx_idx
>= NUM_TX_BDS
|| state
->rx_idx
>= NUM_RX_BDS
398 || state
->tx_space
< 2)
399 return I2CERR_NO_BUFFERS
;
401 rxbd
= (I2C_BD
*) state
->rxbd
;
402 txbd
= (I2C_BD
*) state
->txbd
;
404 debug("[I2C] rxbd = %08x\n", (int) rxbd
);
405 debug("[I2C] txbd = %08x\n", (int) txbd
);
407 txbd
->addr
= state
->tx_buf
;
409 /* set up TXBD for destination address */
410 if (flags
& I2CF_ENABLE_SECONDARY
) {
412 txbd
->addr
[0] = address
<< 1; /* Write data */
413 txbd
->addr
[1] = secondary_address
; /* Internal address */
414 txbd
->status
= BD_SC_READY
;
416 txbd
->length
= 1 + size_to_expect
;
417 txbd
->addr
[0] = (address
<< 1) | 0x01;
418 txbd
->status
= BD_SC_READY
;
419 memset(&txbd
->addr
[1], 0, txbd
->length
);
422 /* set up rxbd for reception */
423 rxbd
->status
= BD_SC_EMPTY
;
424 rxbd
->length
= size_to_expect
;
427 txbd
->status
|= BD_I2C_TX_START
;
428 if (flags
& I2CF_STOP_COND
) {
429 txbd
->status
|= BD_SC_LAST
| BD_SC_WRAP
;
430 rxbd
->status
|= BD_SC_WRAP
;
433 debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
434 txbd
->length
, txbd
->status
, txbd
->addr
[0], txbd
->addr
[1]);
435 debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
436 rxbd
->length
, rxbd
->status
, rxbd
->addr
[0], rxbd
->addr
[1]);
439 state
->tx_buf
+= txbd
->length
;
440 state
->tx_space
-= txbd
->length
;
442 state
->txbd
= (void *) (txbd
+ 1);
444 state
->rxbd
= (void *) (rxbd
+ 1);
451 int i2c_doio(i2c_state_t
*state
)
453 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
455 volatile i2c8260_t
*i2c
= (i2c8260_t
*)&immap
->im_i2c
;
456 volatile I2C_BD
*txbd
, *rxbd
;
457 int n
, i
, b
, rxcnt
= 0, rxtimeo
= 0, txcnt
= 0, txtimeo
= 0, rc
= 0;
460 debug("[I2C] i2c_doio\n");
462 if (state
->tx_idx
<= 0 && state
->rx_idx
<= 0) {
463 debug("[I2C] No I/O is queued\n");
464 return I2CERR_QUEUE_EMPTY
;
467 dpaddr
= immap
->im_dprambase16
[PROFF_I2C_BASE
/ sizeof(u16
)];
468 iip
= (iic_t
*)&immap
->im_dprambase
[dpaddr
];
469 iip
->iic_rbptr
= iip
->iic_rbase
;
470 iip
->iic_tbptr
= iip
->iic_tbase
;
473 debug("[I2C] Enabling I2C...\n");
474 i2c
->i2c_i2mod
|= 0x01;
476 /* Begin transmission */
477 i2c
->i2c_i2com
|= 0x80;
479 /* Loop until transmit & receive completed */
485 txbd
= ((I2C_BD
*) state
->txbd
) - n
;
486 for (i
= 0; i
< n
; i
++) {
487 txtimeo
+= TOUT_LOOP
* txbd
->length
;
491 txbd
--; /* wait until last in list is done */
493 debug("[I2C] Transmitting...(txbd=0x%08lx)\n",
496 udelay(START_DELAY_US
); /* give it time to start */
497 while ((txbd
->status
& BD_SC_READY
) && (++txcnt
< txtimeo
)) {
501 __asm__
__volatile__("eieio");
507 if (txcnt
< txtimeo
&& n
> 0) {
509 rxbd
= ((I2C_BD
*) state
->rxbd
) - n
;
510 for (i
= 0; i
< n
; i
++) {
511 rxtimeo
+= TOUT_LOOP
* rxbd
->length
;
515 rxbd
--; /* wait until last in list is done */
517 debug("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong
) rxbd
);
519 udelay(START_DELAY_US
); /* give it time to start */
520 while ((rxbd
->status
& BD_SC_EMPTY
) && (++rxcnt
< rxtimeo
)) {
524 __asm__
__volatile__("eieio");
529 i2c
->i2c_i2mod
&= ~0x01;
534 for (i
= 0; i
< n
; i
++) {
535 txbd
= ((I2C_BD
*) state
->txbd
) - (n
- i
);
536 b
= txbd
->status
& BD_I2C_TX_ERR
;
538 if (state
->err_cb
!= NULL
)
539 (*state
->err_cb
) (I2CECB_TX_ERR
| b
,
542 rc
= I2CERR_IO_ERROR
;
550 for (i
= 0; i
< n
; i
++) {
551 rxbd
= ((I2C_BD
*) state
->rxbd
) - (n
- i
);
552 b
= rxbd
->status
& BD_I2C_RX_ERR
;
554 if (state
->err_cb
!= NULL
)
555 (*state
->err_cb
) (I2CECB_RX_ERR
| b
,
558 rc
= I2CERR_IO_ERROR
;
563 if ((txtimeo
> 0 && txcnt
>= txtimeo
) ||
564 (rxtimeo
> 0 && rxcnt
>= rxtimeo
)) {
565 if (state
->err_cb
!= NULL
)
566 (*state
->err_cb
) (I2CECB_TIMEOUT
, -1, state
->cb_data
);
574 static void i2c_probe_callback(int flags
, int xnum
, void *data
)
577 * the only acceptable errors are a transmit NAK or a receive
578 * overrun - tx NAK means the device does not exist, rx OV
579 * means the device must have responded to the slave address
580 * even though the transfer failed
582 if (flags
== (I2CECB_TX_ERR
| I2CECB_TX_NAK
))
584 if (flags
== (I2CECB_RX_ERR
| I2CECB_RX_OV
))
588 int i2c_probe(uchar chip
)
596 state
.err_cb
= i2c_probe_callback
;
597 state
.cb_data
= (void *) &err_flag
;
600 rc
= i2c_receive(&state
, chip
, 0, I2CF_START_COND
| I2CF_STOP_COND
, 1,
604 return rc
; /* probe failed */
606 rc
= i2c_doio(&state
);
609 return 0; /* device exists - read succeeded */
611 if (rc
== I2CERR_TIMEOUT
)
612 return -1; /* device does not exist - timeout */
614 if (rc
!= I2CERR_IO_ERROR
|| err_flag
== 0)
615 return rc
; /* probe failed */
618 return -1; /* device does not exist - had transmit NAK */
620 return 0; /* device exists - had receive overrun */
624 int i2c_read(uchar chip
, uint addr
, int alen
, uchar
*buffer
, int len
)
630 xaddr
[0] = (addr
>> 24) & 0xFF;
631 xaddr
[1] = (addr
>> 16) & 0xFF;
632 xaddr
[2] = (addr
>> 8) & 0xFF;
633 xaddr
[3] = addr
& 0xFF;
635 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
637 * EEPROM chips that implement "address overflow" are ones
638 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
639 * and the extra bits end up in the "chip address" bit slots.
640 * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
643 * Note that we consider the length of the address field to still
644 * be one byte because the extra address bits are hidden in the
647 chip
|= ((addr
>> (alen
* 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
);
652 rc
= i2c_send(&state
, chip
, 0, I2CF_START_COND
, alen
,
655 printf("i2c_read: i2c_send failed (%d)\n", rc
);
659 rc
= i2c_receive(&state
, chip
, 0, I2CF_STOP_COND
, len
, buffer
);
661 printf("i2c_read: i2c_receive failed (%d)\n", rc
);
665 rc
= i2c_doio(&state
);
667 printf("i2c_read: i2c_doio failed (%d)\n", rc
);
673 int i2c_write(uchar chip
, uint addr
, int alen
, uchar
*buffer
, int len
)
679 xaddr
[0] = (addr
>> 24) & 0xFF;
680 xaddr
[1] = (addr
>> 16) & 0xFF;
681 xaddr
[2] = (addr
>> 8) & 0xFF;
682 xaddr
[3] = addr
& 0xFF;
684 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
686 * EEPROM chips that implement "address overflow" are ones
687 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
688 * and the extra bits end up in the "chip address" bit slots.
689 * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
692 * Note that we consider the length of the address field to still
693 * be one byte because the extra address bits are hidden in the
696 chip
|= ((addr
>> (alen
* 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
);
701 rc
= i2c_send(&state
, chip
, 0, I2CF_START_COND
, alen
,
704 printf("i2c_write: first i2c_send failed (%d)\n", rc
);
708 rc
= i2c_send(&state
, 0, 0, I2CF_STOP_COND
, len
, buffer
);
710 printf("i2c_write: second i2c_send failed (%d)\n", rc
);
714 rc
= i2c_doio(&state
);
716 printf("i2c_write: i2c_doio failed (%d)\n", rc
);
722 #if defined(CONFIG_I2C_MULTI_BUS)
724 * Functions for multiple I2C bus handling
726 unsigned int i2c_get_bus_num(void)
731 int i2c_set_bus_num(unsigned int bus
)
733 #if defined(CONFIG_I2C_MUX)
734 if (bus
< CONFIG_SYS_MAX_I2C_BUS
) {
739 ret
= i2x_mux_select_mux(bus
);
746 if (bus
>= CONFIG_SYS_MAX_I2C_BUS
)
753 #endif /* CONFIG_I2C_MULTI_BUS */
754 #endif /* CONFIG_HARD_I2C */