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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/powerpc/cpu/mpc83xx/cpu.c
e41988d5fadabde58418bb9514acb5ac59ed2207
2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * CPU specific code for the MPC83xx family.
10 * Derived from the MPC8260 and MPC85xx.
17 #include <asm/processor.h>
21 #include <fsl_esdhc.h>
22 #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
23 #include <asm/immap_qe.h>
27 DECLARE_GLOBAL_DATA_PTR
;
31 volatile immap_t
*immr
;
32 ulong clock
= gd
->cpu_clk
;
38 const struct cpu_type
{
41 } cpu_type_list
[] = {
51 CPU_TYPE_ENTRY(8347_TBGA_
),
52 CPU_TYPE_ENTRY(8347_PBGA_
),
54 CPU_TYPE_ENTRY(8358_TBGA_
),
55 CPU_TYPE_ENTRY(8358_PBGA_
),
62 immr
= (immap_t
*)CONFIG_SYS_IMMR
;
66 switch (pvr
& 0xffff0000) {
84 printf("Unknown core, ");
87 spridr
= immr
->sysconf
.spridr
;
89 for (i
= 0; i
< ARRAY_SIZE(cpu_type_list
); i
++)
90 if (cpu_type_list
[i
].partid
== PARTID_NO_E(spridr
)) {
92 puts(cpu_type_list
[i
].name
);
93 if (IS_E_PROCESSOR(spridr
))
95 if ((SPR_FAMILY(spridr
) == SPR_834X_FAMILY
||
96 SPR_FAMILY(spridr
) == SPR_836X_FAMILY
) &&
97 REVID_MAJOR(spridr
) >= 2)
99 printf(", Rev: %d.%d", REVID_MAJOR(spridr
),
100 REVID_MINOR(spridr
));
104 if (i
== ARRAY_SIZE(cpu_type_list
))
105 printf("(SPRIDR %08x unknown), ", spridr
);
107 printf(" at %s MHz, ", strmhz(buf
, clock
));
109 printf("CSB: %s MHz\n", strmhz(buf
, gd
->arch
.csb_clk
));
115 do_reset (cmd_tbl_t
* cmdtp
, int flag
, int argc
, char * const argv
[])
118 #ifndef MPC83xx_RESET
122 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
124 puts("Resetting the board.\n");
128 /* Interrupts and MMU off */
129 __asm__
__volatile__ ("mfmsr %0":"=r" (msr
):);
131 msr
&= ~( MSR_EE
| MSR_IR
| MSR_DR
);
132 __asm__
__volatile__ ("mtmsr %0"::"r" (msr
));
134 /* enable Reset Control Reg */
135 immap
->reset
.rpr
= 0x52535445;
136 __asm__
__volatile__ ("sync");
137 __asm__
__volatile__ ("isync");
139 /* confirm Reset Control Reg is enabled */
140 while(!((immap
->reset
.rcer
) & RCER_CRE
));
144 /* perform reset, only one bit */
145 immap
->reset
.rcr
= RCR_SWHR
;
147 #else /* ! MPC83xx_RESET */
149 immap
->reset
.rmr
= RMR_CSRE
; /* Checkstop Reset enable */
151 /* Interrupts and MMU off */
152 __asm__
__volatile__ ("mfmsr %0":"=r" (msr
):);
154 msr
&= ~(MSR_ME
| MSR_EE
| MSR_IR
| MSR_DR
);
155 __asm__
__volatile__ ("mtmsr %0"::"r" (msr
));
158 * Trying to execute the next instruction at a non-existing address
159 * should cause a machine check, resulting in reset
161 addr
= CONFIG_SYS_RESET_ADDRESS
;
163 ((void (*)(void)) addr
) ();
164 #endif /* MPC83xx_RESET */
171 * Get timebase clock frequency (like cpu_clk in Hz)
174 unsigned long get_tbclk(void)
178 tbclk
= (gd
->bus_clk
+ 3L) / 4L;
184 #if defined(CONFIG_WATCHDOG)
185 void watchdog_reset (void)
187 int re_enable
= disable_interrupts();
189 /* Reset the 83xx watchdog */
190 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
191 immr
->wdt
.swsrr
= 0x556c;
192 immr
->wdt
.swsrr
= 0xaa39;
195 enable_interrupts ();
200 * Initializes on-chip ethernet controllers.
201 * to override, implement board_eth_init()
203 int cpu_eth_init(bd_t
*bis
)
205 #if defined(CONFIG_UEC_ETH)
206 uec_standard_init(bis
);
209 #if defined(CONFIG_TSEC_ENET)
210 tsec_standard_init(bis
);
216 * Initializes on-chip MMC controllers.
217 * to override, implement board_mmc_init()
219 int cpu_mmc_init(bd_t
*bis
)
221 #ifdef CONFIG_FSL_ESDHC
222 return fsl_esdhc_mmc_init(bis
);