2 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 DECLARE_GLOBAL_DATA_PTR
;
29 * Breathe some life into the CPU...
31 * Set up the memory map,
32 * initialize a bunch of registers,
33 * initialize the UPM's
35 void cpu_init_f (volatile immap_t
* im
)
39 /* Pointer is writable since we allocated a register for it */
40 gd
= (gd_t
*) (CONFIG_SYS_INIT_RAM_ADDR
+ CONFIG_SYS_GBL_DATA_OFFSET
);
42 /* Clear initial global data */
43 for (i
= 0; i
< sizeof(gd_t
); i
++)
46 /* system performance tweaking */
48 #ifdef CONFIG_SYS_ACR_PIPE_DEP
49 /* Arbiter pipeline depth */
50 im
->arbiter
.acr
= (im
->arbiter
.acr
& ~ACR_PIPE_DEP
) |
51 (CONFIG_SYS_ACR_PIPE_DEP
<< ACR_PIPE_DEP_SHIFT
);
54 #ifdef CONFIG_SYS_ACR_RPTCNT
55 /* Arbiter repeat count */
56 im
->arbiter
.acr
= (im
->arbiter
.acr
& ~(ACR_RPTCNT
)) |
57 (CONFIG_SYS_ACR_RPTCNT
<< ACR_RPTCNT_SHIFT
);
60 #ifdef CONFIG_SYS_SPCR_OPT
61 /* Optimize transactions between CSB and other devices */
62 im
->sysconf
.spcr
= (im
->sysconf
.spcr
& ~SPCR_OPT
) |
63 (CONFIG_SYS_SPCR_OPT
<< SPCR_OPT_SHIFT
);
66 /* Enable Time Base & Decrimenter (so we will have udelay()) */
67 im
->sysconf
.spcr
|= SPCR_TBEN
;
69 /* DDR control driver register */
70 #ifdef CONFIG_SYS_DDRCDR
71 im
->sysconf
.ddrcdr
= CONFIG_SYS_DDRCDR
;
73 /* Output buffer impedance register */
74 #ifdef CONFIG_SYS_OBIR
75 im
->sysconf
.obir
= CONFIG_SYS_OBIR
;
82 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
83 * addresses - these have to be modified later when FLASH size
87 #if defined(CONFIG_SYS_NAND_BR_PRELIM) \
88 && defined(CONFIG_SYS_NAND_OR_PRELIM) \
89 && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
90 && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
91 set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM
);
92 set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM
);
93 im
->sysconf
.lblaw
[0].bar
= CONFIG_SYS_NAND_LBLAWBAR_PRELIM
;
94 im
->sysconf
.lblaw
[0].ar
= CONFIG_SYS_NAND_LBLAWAR_PRELIM
;
96 #error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
101 * Get timebase clock frequency (like cpu_clk in Hz)
103 unsigned long get_tbclk(void)
105 return (gd
->bus_clk
+ 3L) / 4L;
108 void puts(const char *str
)