12 bool "Support sbc8548"
15 config TARGET_SOCRATES
16 bool "Support socrates"
19 config TARGET_B4420QDS
20 bool "Support B4420QDS"
25 config TARGET_B4860QDS
26 bool "Support B4860QDS"
28 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 config TARGET_BSC9131RDB
33 bool "Support BSC9131RDB"
37 config TARGET_BSC9132QDS
38 bool "Support BSC9132QDS"
40 select BOARD_LATE_INIT if CHAIN_OF_TRUST
43 config TARGET_C29XPCIE
44 bool "Support C29XPCIE"
46 select BOARD_LATE_INIT if CHAIN_OF_TRUST
52 bool "Support P3041DS"
55 select BOARD_LATE_INIT if CHAIN_OF_TRUST
58 bool "Support P4080DS"
61 select BOARD_LATE_INIT if CHAIN_OF_TRUST
64 bool "Support P5020DS"
67 select BOARD_LATE_INIT if CHAIN_OF_TRUST
70 bool "Support P5040DS"
73 select BOARD_LATE_INIT if CHAIN_OF_TRUST
75 config TARGET_MPC8536DS
76 bool "Support MPC8536DS"
78 # Use DDR3 controller with DDR2 DIMMs on this board
79 select SYS_FSL_DDRC_GEN3
81 config TARGET_MPC8540ADS
82 bool "Support MPC8540ADS"
85 config TARGET_MPC8541CDS
86 bool "Support MPC8541CDS"
89 config TARGET_MPC8544DS
90 bool "Support MPC8544DS"
93 config TARGET_MPC8548CDS
94 bool "Support MPC8548CDS"
97 config TARGET_MPC8555CDS
98 bool "Support MPC8555CDS"
101 config TARGET_MPC8560ADS
102 bool "Support MPC8560ADS"
105 config TARGET_MPC8568MDS
106 bool "Support MPC8568MDS"
109 config TARGET_MPC8569MDS
110 bool "Support MPC8569MDS"
113 config TARGET_MPC8572DS
114 bool "Support MPC8572DS"
116 # Use DDR3 controller with DDR2 DIMMs on this board
117 select SYS_FSL_DDRC_GEN3
119 config TARGET_P1010RDB_PA
120 bool "Support P1010RDB_PA"
122 select BOARD_LATE_INIT if CHAIN_OF_TRUST
126 config TARGET_P1010RDB_PB
127 bool "Support P1010RDB_PB"
129 select BOARD_LATE_INIT if CHAIN_OF_TRUST
133 config TARGET_P1022DS
134 bool "Support P1022DS"
139 config TARGET_P1023RDB
140 bool "Support P1023RDB"
143 config TARGET_P1020MBG
144 bool "Support P1020MBG-PC"
149 config TARGET_P1020RDB_PC
150 bool "Support P1020RDB-PC"
155 config TARGET_P1020RDB_PD
156 bool "Support P1020RDB-PD"
161 config TARGET_P1020UTM
162 bool "Support P1020UTM"
167 config TARGET_P1021RDB
168 bool "Support P1021RDB"
173 config TARGET_P1024RDB
174 bool "Support P1024RDB"
179 config TARGET_P1025RDB
180 bool "Support P1025RDB"
185 config TARGET_P2020RDB
186 bool "Support P2020RDB-PC"
192 bool "Support p1_twr"
195 config TARGET_P2041RDB
196 bool "Support P2041RDB"
198 select BOARD_LATE_INIT if CHAIN_OF_TRUST
201 config TARGET_QEMU_PPCE500
202 bool "Support qemu-ppce500"
203 select ARCH_QEMU_E500
206 config TARGET_T1024QDS
207 bool "Support T1024QDS"
209 select BOARD_LATE_INIT if CHAIN_OF_TRUST
213 config TARGET_T1023RDB
214 bool "Support T1023RDB"
216 select BOARD_LATE_INIT if CHAIN_OF_TRUST
220 config TARGET_T1024RDB
221 bool "Support T1024RDB"
223 select BOARD_LATE_INIT if CHAIN_OF_TRUST
227 config TARGET_T1040QDS
228 bool "Support T1040QDS"
230 select BOARD_LATE_INIT if CHAIN_OF_TRUST
233 config TARGET_T1040RDB
234 bool "Support T1040RDB"
236 select BOARD_LATE_INIT if CHAIN_OF_TRUST
240 config TARGET_T1040D4RDB
241 bool "Support T1040D4RDB"
243 select BOARD_LATE_INIT if CHAIN_OF_TRUST
247 config TARGET_T1042RDB
248 bool "Support T1042RDB"
250 select BOARD_LATE_INIT if CHAIN_OF_TRUST
254 config TARGET_T1042D4RDB
255 bool "Support T1042D4RDB"
257 select BOARD_LATE_INIT if CHAIN_OF_TRUST
261 config TARGET_T1042RDB_PI
262 bool "Support T1042RDB_PI"
264 select BOARD_LATE_INIT if CHAIN_OF_TRUST
268 config TARGET_T2080QDS
269 bool "Support T2080QDS"
271 select BOARD_LATE_INIT if CHAIN_OF_TRUST
275 config TARGET_T2080RDB
276 bool "Support T2080RDB"
278 select BOARD_LATE_INIT if CHAIN_OF_TRUST
282 config TARGET_T2081QDS
283 bool "Support T2081QDS"
288 config TARGET_T4160QDS
289 bool "Support T4160QDS"
291 select BOARD_LATE_INIT if CHAIN_OF_TRUST
295 config TARGET_T4160RDB
296 bool "Support T4160RDB"
301 config TARGET_T4240QDS
302 bool "Support T4240QDS"
304 select BOARD_LATE_INIT if CHAIN_OF_TRUST
308 config TARGET_T4240RDB
309 bool "Support T4240RDB"
314 config TARGET_CONTROLCENTERD
315 bool "Support controlcenterd"
318 config TARGET_KMP204X
319 bool "Support kmp204x"
323 config TARGET_XPEDITE520X
324 bool "Support xpedite520x"
327 config TARGET_XPEDITE537X
328 bool "Support xpedite537x"
330 # Use DDR3 controller with DDR2 DIMMs on this board
331 select SYS_FSL_DDRC_GEN3
333 config TARGET_XPEDITE550X
334 bool "Support xpedite550x"
337 config TARGET_UCP1020
338 bool "Support uCP1020"
341 config TARGET_CYRUS_P5020
342 bool "Support Varisys Cyrus P5020"
346 config TARGET_CYRUS_P5040
347 bool "Support Varisys Cyrus P5040"
358 select SYS_FSL_DDR_VER_47
359 select SYS_FSL_ERRATUM_A004477
360 select SYS_FSL_ERRATUM_A005871
361 select SYS_FSL_ERRATUM_A006379
362 select SYS_FSL_ERRATUM_A006384
363 select SYS_FSL_ERRATUM_A006475
364 select SYS_FSL_ERRATUM_A006593
365 select SYS_FSL_ERRATUM_A007075
366 select SYS_FSL_ERRATUM_A007186
367 select SYS_FSL_ERRATUM_A007212
368 select SYS_FSL_ERRATUM_A009942
369 select SYS_FSL_HAS_DDR3
370 select SYS_FSL_HAS_SEC
371 select SYS_FSL_QORIQ_CHASSIS2
372 select SYS_FSL_SEC_BE
373 select SYS_FSL_SEC_COMPAT_4
381 select SYS_FSL_DDR_VER_47
382 select SYS_FSL_ERRATUM_A004477
383 select SYS_FSL_ERRATUM_A005871
384 select SYS_FSL_ERRATUM_A006379
385 select SYS_FSL_ERRATUM_A006384
386 select SYS_FSL_ERRATUM_A006475
387 select SYS_FSL_ERRATUM_A006593
388 select SYS_FSL_ERRATUM_A007075
389 select SYS_FSL_ERRATUM_A007186
390 select SYS_FSL_ERRATUM_A007212
391 select SYS_FSL_ERRATUM_A009942
392 select SYS_FSL_HAS_DDR3
393 select SYS_FSL_HAS_SEC
394 select SYS_FSL_QORIQ_CHASSIS2
395 select SYS_FSL_SEC_BE
396 select SYS_FSL_SEC_COMPAT_4
402 select SYS_FSL_DDR_VER_44
403 select SYS_FSL_ERRATUM_A004477
404 select SYS_FSL_ERRATUM_A005125
405 select SYS_FSL_ERRATUM_ESDHC111
406 select SYS_FSL_HAS_DDR3
407 select SYS_FSL_HAS_SEC
408 select SYS_FSL_SEC_BE
409 select SYS_FSL_SEC_COMPAT_4
414 select SYS_FSL_DDR_VER_46
415 select SYS_FSL_ERRATUM_A004477
416 select SYS_FSL_ERRATUM_A005125
417 select SYS_FSL_ERRATUM_A005434
418 select SYS_FSL_ERRATUM_ESDHC111
419 select SYS_FSL_ERRATUM_I2C_A004447
420 select SYS_FSL_ERRATUM_IFC_A002769
421 select SYS_FSL_HAS_DDR3
422 select SYS_FSL_HAS_SEC
423 select SYS_FSL_SEC_BE
424 select SYS_FSL_SEC_COMPAT_4
425 select SYS_PPC_E500_USE_DEBUG_TLB
430 select SYS_FSL_DDR_VER_46
431 select SYS_FSL_ERRATUM_A005125
432 select SYS_FSL_ERRATUM_ESDHC111
433 select SYS_FSL_HAS_DDR3
434 select SYS_FSL_HAS_SEC
435 select SYS_FSL_SEC_BE
436 select SYS_FSL_SEC_COMPAT_6
437 select SYS_PPC_E500_USE_DEBUG_TLB
442 select SYS_FSL_ERRATUM_A004508
443 select SYS_FSL_ERRATUM_A005125
444 select SYS_FSL_HAS_DDR2
445 select SYS_FSL_HAS_DDR3
446 select SYS_FSL_HAS_SEC
447 select SYS_FSL_SEC_BE
448 select SYS_FSL_SEC_COMPAT_2
449 select SYS_PPC_E500_USE_DEBUG_TLB
454 select SYS_FSL_HAS_DDR1
459 select SYS_FSL_HAS_DDR1
460 select SYS_FSL_HAS_SEC
461 select SYS_FSL_SEC_BE
462 select SYS_FSL_SEC_COMPAT_2
467 select SYS_FSL_ERRATUM_A005125
468 select SYS_FSL_HAS_DDR2
469 select SYS_FSL_HAS_SEC
470 select SYS_FSL_SEC_BE
471 select SYS_FSL_SEC_COMPAT_2
472 select SYS_PPC_E500_USE_DEBUG_TLB
477 select SYS_FSL_ERRATUM_A005125
478 select SYS_FSL_ERRATUM_NMG_DDR120
479 select SYS_FSL_ERRATUM_NMG_LBC103
480 select SYS_FSL_ERRATUM_NMG_ETSEC129
481 select SYS_FSL_ERRATUM_I2C_A004447
482 select SYS_FSL_HAS_DDR2
483 select SYS_FSL_HAS_DDR1
484 select SYS_FSL_HAS_SEC
485 select SYS_FSL_SEC_BE
486 select SYS_FSL_SEC_COMPAT_2
487 select SYS_PPC_E500_USE_DEBUG_TLB
492 select SYS_FSL_HAS_DDR1
493 select SYS_FSL_HAS_SEC
494 select SYS_FSL_SEC_BE
495 select SYS_FSL_SEC_COMPAT_2
500 select SYS_FSL_HAS_DDR1
505 select SYS_FSL_HAS_DDR2
506 select SYS_FSL_HAS_SEC
507 select SYS_FSL_SEC_BE
508 select SYS_FSL_SEC_COMPAT_2
513 select SYS_FSL_ERRATUM_A004508
514 select SYS_FSL_ERRATUM_A005125
515 select SYS_FSL_HAS_DDR3
516 select SYS_FSL_HAS_SEC
517 select SYS_FSL_SEC_BE
518 select SYS_FSL_SEC_COMPAT_2
523 select SYS_FSL_ERRATUM_A004508
524 select SYS_FSL_ERRATUM_A005125
525 select SYS_FSL_ERRATUM_DDR_115
526 select SYS_FSL_ERRATUM_DDR111_DDR134
527 select SYS_FSL_HAS_DDR2
528 select SYS_FSL_HAS_DDR3
529 select SYS_FSL_HAS_SEC
530 select SYS_FSL_SEC_BE
531 select SYS_FSL_SEC_COMPAT_2
532 select SYS_PPC_E500_USE_DEBUG_TLB
537 select SYS_FSL_ERRATUM_A004477
538 select SYS_FSL_ERRATUM_A004508
539 select SYS_FSL_ERRATUM_A005125
540 select SYS_FSL_ERRATUM_A006261
541 select SYS_FSL_ERRATUM_A007075
542 select SYS_FSL_ERRATUM_ESDHC111
543 select SYS_FSL_ERRATUM_I2C_A004447
544 select SYS_FSL_ERRATUM_IFC_A002769
545 select SYS_FSL_ERRATUM_P1010_A003549
546 select SYS_FSL_ERRATUM_SEC_A003571
547 select SYS_FSL_ERRATUM_IFC_A003399
548 select SYS_FSL_HAS_DDR3
549 select SYS_FSL_HAS_SEC
550 select SYS_FSL_SEC_BE
551 select SYS_FSL_SEC_COMPAT_4
552 select SYS_PPC_E500_USE_DEBUG_TLB
557 select SYS_FSL_ERRATUM_A004508
558 select SYS_FSL_ERRATUM_A005125
559 select SYS_FSL_ERRATUM_ELBC_A001
560 select SYS_FSL_ERRATUM_ESDHC111
561 select SYS_FSL_HAS_DDR3
562 select SYS_FSL_HAS_SEC
563 select SYS_FSL_SEC_BE
564 select SYS_FSL_SEC_COMPAT_2
565 select SYS_PPC_E500_USE_DEBUG_TLB
570 select SYS_FSL_ERRATUM_A004508
571 select SYS_FSL_ERRATUM_A005125
572 select SYS_FSL_ERRATUM_ELBC_A001
573 select SYS_FSL_ERRATUM_ESDHC111
574 select SYS_FSL_HAS_DDR3
575 select SYS_FSL_HAS_SEC
576 select SYS_FSL_SEC_BE
577 select SYS_FSL_SEC_COMPAT_2
578 select SYS_PPC_E500_USE_DEBUG_TLB
583 select SYS_FSL_ERRATUM_A004508
584 select SYS_FSL_ERRATUM_A005125
585 select SYS_FSL_ERRATUM_ELBC_A001
586 select SYS_FSL_ERRATUM_ESDHC111
587 select SYS_FSL_HAS_DDR3
588 select SYS_FSL_HAS_SEC
589 select SYS_FSL_SEC_BE
590 select SYS_FSL_SEC_COMPAT_2
591 select SYS_PPC_E500_USE_DEBUG_TLB
596 select SYS_FSL_ERRATUM_A004477
597 select SYS_FSL_ERRATUM_A004508
598 select SYS_FSL_ERRATUM_A005125
599 select SYS_FSL_ERRATUM_ELBC_A001
600 select SYS_FSL_ERRATUM_ESDHC111
601 select SYS_FSL_ERRATUM_SATA_A001
602 select SYS_FSL_HAS_DDR3
603 select SYS_FSL_HAS_SEC
604 select SYS_FSL_SEC_BE
605 select SYS_FSL_SEC_COMPAT_2
606 select SYS_PPC_E500_USE_DEBUG_TLB
611 select SYS_FSL_ERRATUM_A004508
612 select SYS_FSL_ERRATUM_A005125
613 select SYS_FSL_ERRATUM_I2C_A004447
614 select SYS_FSL_HAS_DDR3
615 select SYS_FSL_HAS_SEC
616 select SYS_FSL_SEC_BE
617 select SYS_FSL_SEC_COMPAT_4
622 select SYS_FSL_ERRATUM_A004508
623 select SYS_FSL_ERRATUM_A005125
624 select SYS_FSL_ERRATUM_ELBC_A001
625 select SYS_FSL_ERRATUM_ESDHC111
626 select SYS_FSL_HAS_DDR3
627 select SYS_FSL_HAS_SEC
628 select SYS_FSL_SEC_BE
629 select SYS_FSL_SEC_COMPAT_2
630 select SYS_PPC_E500_USE_DEBUG_TLB
635 select SYS_FSL_ERRATUM_A004508
636 select SYS_FSL_ERRATUM_A005125
637 select SYS_FSL_ERRATUM_ELBC_A001
638 select SYS_FSL_ERRATUM_ESDHC111
639 select SYS_FSL_HAS_DDR3
640 select SYS_FSL_HAS_SEC
641 select SYS_FSL_SEC_BE
642 select SYS_FSL_SEC_COMPAT_2
643 select SYS_PPC_E500_USE_DEBUG_TLB
648 select SYS_FSL_ERRATUM_A004477
649 select SYS_FSL_ERRATUM_A004508
650 select SYS_FSL_ERRATUM_A005125
651 select SYS_FSL_ERRATUM_ESDHC111
652 select SYS_FSL_ERRATUM_ESDHC_A001
653 select SYS_FSL_HAS_DDR3
654 select SYS_FSL_HAS_SEC
655 select SYS_FSL_SEC_BE
656 select SYS_FSL_SEC_COMPAT_2
657 select SYS_PPC_E500_USE_DEBUG_TLB
663 select SYS_FSL_ERRATUM_A004510
664 select SYS_FSL_ERRATUM_A004849
665 select SYS_FSL_ERRATUM_A006261
666 select SYS_FSL_ERRATUM_CPU_A003999
667 select SYS_FSL_ERRATUM_DDR_A003
668 select SYS_FSL_ERRATUM_DDR_A003474
669 select SYS_FSL_ERRATUM_ESDHC111
670 select SYS_FSL_ERRATUM_I2C_A004447
671 select SYS_FSL_ERRATUM_NMG_CPU_A011
672 select SYS_FSL_ERRATUM_SRIO_A004034
673 select SYS_FSL_ERRATUM_USB14
674 select SYS_FSL_HAS_DDR3
675 select SYS_FSL_HAS_SEC
676 select SYS_FSL_QORIQ_CHASSIS1
677 select SYS_FSL_SEC_BE
678 select SYS_FSL_SEC_COMPAT_4
684 select SYS_FSL_DDR_VER_44
685 select SYS_FSL_ERRATUM_A004510
686 select SYS_FSL_ERRATUM_A004849
687 select SYS_FSL_ERRATUM_A005812
688 select SYS_FSL_ERRATUM_A006261
689 select SYS_FSL_ERRATUM_CPU_A003999
690 select SYS_FSL_ERRATUM_DDR_A003
691 select SYS_FSL_ERRATUM_DDR_A003474
692 select SYS_FSL_ERRATUM_ESDHC111
693 select SYS_FSL_ERRATUM_I2C_A004447
694 select SYS_FSL_ERRATUM_NMG_CPU_A011
695 select SYS_FSL_ERRATUM_SRIO_A004034
696 select SYS_FSL_ERRATUM_USB14
697 select SYS_FSL_HAS_DDR3
698 select SYS_FSL_HAS_SEC
699 select SYS_FSL_QORIQ_CHASSIS1
700 select SYS_FSL_SEC_BE
701 select SYS_FSL_SEC_COMPAT_4
707 select SYS_FSL_DDR_VER_44
708 select SYS_FSL_ERRATUM_A004510
709 select SYS_FSL_ERRATUM_A004580
710 select SYS_FSL_ERRATUM_A004849
711 select SYS_FSL_ERRATUM_A005812
712 select SYS_FSL_ERRATUM_A007075
713 select SYS_FSL_ERRATUM_CPC_A002
714 select SYS_FSL_ERRATUM_CPC_A003
715 select SYS_FSL_ERRATUM_CPU_A003999
716 select SYS_FSL_ERRATUM_DDR_A003
717 select SYS_FSL_ERRATUM_DDR_A003474
718 select SYS_FSL_ERRATUM_ELBC_A001
719 select SYS_FSL_ERRATUM_ESDHC111
720 select SYS_FSL_ERRATUM_ESDHC13
721 select SYS_FSL_ERRATUM_ESDHC135
722 select SYS_FSL_ERRATUM_I2C_A004447
723 select SYS_FSL_ERRATUM_NMG_CPU_A011
724 select SYS_FSL_ERRATUM_SRIO_A004034
725 select SYS_P4080_ERRATUM_CPU22
726 select SYS_P4080_ERRATUM_PCIE_A003
727 select SYS_P4080_ERRATUM_SERDES8
728 select SYS_P4080_ERRATUM_SERDES9
729 select SYS_P4080_ERRATUM_SERDES_A001
730 select SYS_P4080_ERRATUM_SERDES_A005
731 select SYS_FSL_HAS_DDR3
732 select SYS_FSL_HAS_SEC
733 select SYS_FSL_QORIQ_CHASSIS1
734 select SYS_FSL_SEC_BE
735 select SYS_FSL_SEC_COMPAT_4
741 select SYS_FSL_DDR_VER_44
742 select SYS_FSL_ERRATUM_A004510
743 select SYS_FSL_ERRATUM_A006261
744 select SYS_FSL_ERRATUM_DDR_A003
745 select SYS_FSL_ERRATUM_DDR_A003474
746 select SYS_FSL_ERRATUM_ESDHC111
747 select SYS_FSL_ERRATUM_I2C_A004447
748 select SYS_FSL_ERRATUM_SRIO_A004034
749 select SYS_FSL_ERRATUM_USB14
750 select SYS_FSL_HAS_DDR3
751 select SYS_FSL_HAS_SEC
752 select SYS_FSL_QORIQ_CHASSIS1
753 select SYS_FSL_SEC_BE
754 select SYS_FSL_SEC_COMPAT_4
761 select SYS_FSL_DDR_VER_44
762 select SYS_FSL_ERRATUM_A004510
763 select SYS_FSL_ERRATUM_A004699
764 select SYS_FSL_ERRATUM_A005812
765 select SYS_FSL_ERRATUM_A006261
766 select SYS_FSL_ERRATUM_DDR_A003
767 select SYS_FSL_ERRATUM_DDR_A003474
768 select SYS_FSL_ERRATUM_ESDHC111
769 select SYS_FSL_ERRATUM_USB14
770 select SYS_FSL_HAS_DDR3
771 select SYS_FSL_HAS_SEC
772 select SYS_FSL_QORIQ_CHASSIS1
773 select SYS_FSL_SEC_BE
774 select SYS_FSL_SEC_COMPAT_4
777 config ARCH_QEMU_E500
784 select SYS_FSL_DDR_VER_50
785 select SYS_FSL_ERRATUM_A008378
786 select SYS_FSL_ERRATUM_A009663
787 select SYS_FSL_ERRATUM_A009942
788 select SYS_FSL_ERRATUM_ESDHC111
789 select SYS_FSL_HAS_DDR3
790 select SYS_FSL_HAS_DDR4
791 select SYS_FSL_HAS_SEC
792 select SYS_FSL_QORIQ_CHASSIS2
793 select SYS_FSL_SEC_BE
794 select SYS_FSL_SEC_COMPAT_5
800 select SYS_FSL_DDR_VER_50
801 select SYS_FSL_ERRATUM_A008378
802 select SYS_FSL_ERRATUM_A009663
803 select SYS_FSL_ERRATUM_A009942
804 select SYS_FSL_ERRATUM_ESDHC111
805 select SYS_FSL_HAS_DDR3
806 select SYS_FSL_HAS_DDR4
807 select SYS_FSL_HAS_SEC
808 select SYS_FSL_QORIQ_CHASSIS2
809 select SYS_FSL_SEC_BE
810 select SYS_FSL_SEC_COMPAT_5
816 select SYS_FSL_DDR_VER_50
817 select SYS_FSL_ERRATUM_A008044
818 select SYS_FSL_ERRATUM_A008378
819 select SYS_FSL_ERRATUM_A009663
820 select SYS_FSL_ERRATUM_A009942
821 select SYS_FSL_ERRATUM_ESDHC111
822 select SYS_FSL_HAS_DDR3
823 select SYS_FSL_HAS_DDR4
824 select SYS_FSL_HAS_SEC
825 select SYS_FSL_QORIQ_CHASSIS2
826 select SYS_FSL_SEC_BE
827 select SYS_FSL_SEC_COMPAT_5
833 select SYS_FSL_DDR_VER_50
834 select SYS_FSL_ERRATUM_A008044
835 select SYS_FSL_ERRATUM_A008378
836 select SYS_FSL_ERRATUM_A009663
837 select SYS_FSL_ERRATUM_A009942
838 select SYS_FSL_ERRATUM_ESDHC111
839 select SYS_FSL_HAS_DDR3
840 select SYS_FSL_HAS_DDR4
841 select SYS_FSL_HAS_SEC
842 select SYS_FSL_QORIQ_CHASSIS2
843 select SYS_FSL_SEC_BE
844 select SYS_FSL_SEC_COMPAT_5
851 select SYS_FSL_DDR_VER_47
852 select SYS_FSL_ERRATUM_A006379
853 select SYS_FSL_ERRATUM_A006593
854 select SYS_FSL_ERRATUM_A007186
855 select SYS_FSL_ERRATUM_A007212
856 select SYS_FSL_ERRATUM_A009942
857 select SYS_FSL_ERRATUM_ESDHC111
858 select SYS_FSL_HAS_DDR3
859 select SYS_FSL_HAS_SEC
860 select SYS_FSL_QORIQ_CHASSIS2
861 select SYS_FSL_SEC_BE
862 select SYS_FSL_SEC_COMPAT_4
870 select SYS_FSL_DDR_VER_47
871 select SYS_FSL_ERRATUM_A006379
872 select SYS_FSL_ERRATUM_A006593
873 select SYS_FSL_ERRATUM_A007186
874 select SYS_FSL_ERRATUM_A007212
875 select SYS_FSL_ERRATUM_A009942
876 select SYS_FSL_ERRATUM_ESDHC111
877 select SYS_FSL_HAS_DDR3
878 select SYS_FSL_HAS_SEC
879 select SYS_FSL_QORIQ_CHASSIS2
880 select SYS_FSL_SEC_BE
881 select SYS_FSL_SEC_COMPAT_4
889 select SYS_FSL_DDR_VER_47
890 select SYS_FSL_ERRATUM_A004468
891 select SYS_FSL_ERRATUM_A005871
892 select SYS_FSL_ERRATUM_A006379
893 select SYS_FSL_ERRATUM_A006593
894 select SYS_FSL_ERRATUM_A007186
895 select SYS_FSL_ERRATUM_A007798
896 select SYS_FSL_ERRATUM_A009942
897 select SYS_FSL_HAS_DDR3
898 select SYS_FSL_HAS_SEC
899 select SYS_FSL_QORIQ_CHASSIS2
900 select SYS_FSL_SEC_BE
901 select SYS_FSL_SEC_COMPAT_4
909 select SYS_FSL_DDR_VER_47
910 select SYS_FSL_ERRATUM_A004468
911 select SYS_FSL_ERRATUM_A005871
912 select SYS_FSL_ERRATUM_A006261
913 select SYS_FSL_ERRATUM_A006379
914 select SYS_FSL_ERRATUM_A006593
915 select SYS_FSL_ERRATUM_A007186
916 select SYS_FSL_ERRATUM_A007798
917 select SYS_FSL_ERRATUM_A009942
918 select SYS_FSL_HAS_DDR3
919 select SYS_FSL_HAS_SEC
920 select SYS_FSL_QORIQ_CHASSIS2
921 select SYS_FSL_SEC_BE
922 select SYS_FSL_SEC_COMPAT_4
933 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
938 Enble PowerPC E500MC core
943 Enable PowerPC E6500 core
948 Use Freescale common code for Local Access Window
953 Enable Freescale Secure Boot feature. Normally selected
954 by defconfig. If unsure, do not change.
957 int "Maximum number of CPUs permitted for MPC85xx"
958 default 12 if ARCH_T4240
959 default 8 if ARCH_P4080 || \
961 default 4 if ARCH_B4860 || \
969 default 2 if ARCH_B4420 || \
984 Set this number to the maximum number of possible CPUs in the SoC.
985 SoCs may have multiple clusters with each cluster may have multiple
986 ports. If some ports are reserved but higher ports are used for
987 cores, count the reserved ports. This will allocate enough memory
988 in spin table to properly handle all cores.
990 config SYS_CCSRBAR_DEFAULT
991 hex "Default CCSRBAR address"
992 default 0xff700000 if ARCH_BSC9131 || \
1013 default 0xff600000 if ARCH_P1023
1014 default 0xfe000000 if ARCH_B4420 || \
1029 default 0xe0000000 if ARCH_QEMU_E500
1031 Default value of CCSRBAR comes from power-on-reset. It
1032 is fixed on each SoC. Some SoCs can have different value
1033 if changed by pre-boot regime. The value here must match
1034 the current value in SoC. If not sure, do not change.
1036 config SYS_FSL_ERRATUM_A004468
1039 config SYS_FSL_ERRATUM_A004477
1042 config SYS_FSL_ERRATUM_A004508
1045 config SYS_FSL_ERRATUM_A004580
1048 config SYS_FSL_ERRATUM_A004699
1051 config SYS_FSL_ERRATUM_A004849
1054 config SYS_FSL_ERRATUM_A004510
1057 config SYS_FSL_ERRATUM_A004510_SVR_REV
1059 depends on SYS_FSL_ERRATUM_A004510
1060 default 0x20 if ARCH_P4080
1063 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1065 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1068 config SYS_FSL_ERRATUM_A005125
1071 config SYS_FSL_ERRATUM_A005434
1074 config SYS_FSL_ERRATUM_A005812
1077 config SYS_FSL_ERRATUM_A005871
1080 config SYS_FSL_ERRATUM_A006261
1083 config SYS_FSL_ERRATUM_A006379
1086 config SYS_FSL_ERRATUM_A006384
1089 config SYS_FSL_ERRATUM_A006475
1092 config SYS_FSL_ERRATUM_A006593
1095 config SYS_FSL_ERRATUM_A007075
1098 config SYS_FSL_ERRATUM_A007186
1101 config SYS_FSL_ERRATUM_A007212
1104 config SYS_FSL_ERRATUM_A007798
1107 config SYS_FSL_ERRATUM_A008044
1110 config SYS_FSL_ERRATUM_CPC_A002
1113 config SYS_FSL_ERRATUM_CPC_A003
1116 config SYS_FSL_ERRATUM_CPU_A003999
1119 config SYS_FSL_ERRATUM_ELBC_A001
1122 config SYS_FSL_ERRATUM_I2C_A004447
1125 config SYS_FSL_A004447_SVR_REV
1127 depends on SYS_FSL_ERRATUM_I2C_A004447
1128 default 0x00 if ARCH_MPC8548
1129 default 0x10 if ARCH_P1010
1130 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1131 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1133 config SYS_FSL_ERRATUM_IFC_A002769
1136 config SYS_FSL_ERRATUM_IFC_A003399
1139 config SYS_FSL_ERRATUM_NMG_CPU_A011
1142 config SYS_FSL_ERRATUM_NMG_ETSEC129
1145 config SYS_FSL_ERRATUM_NMG_LBC103
1148 config SYS_FSL_ERRATUM_P1010_A003549
1151 config SYS_FSL_ERRATUM_SATA_A001
1154 config SYS_FSL_ERRATUM_SEC_A003571
1157 config SYS_FSL_ERRATUM_SRIO_A004034
1160 config SYS_FSL_ERRATUM_USB14
1163 config SYS_P4080_ERRATUM_CPU22
1166 config SYS_P4080_ERRATUM_PCIE_A003
1169 config SYS_P4080_ERRATUM_SERDES8
1172 config SYS_P4080_ERRATUM_SERDES9
1175 config SYS_P4080_ERRATUM_SERDES_A001
1178 config SYS_P4080_ERRATUM_SERDES_A005
1181 config SYS_FSL_QORIQ_CHASSIS1
1184 config SYS_FSL_QORIQ_CHASSIS2
1187 config SYS_FSL_NUM_LAWS
1188 int "Number of local access windows"
1190 default 32 if ARCH_B4420 || \
1201 default 16 if ARCH_T1023 || \
1205 default 12 if ARCH_BSC9131 || \
1219 default 10 if ARCH_MPC8544 || \
1223 default 8 if ARCH_MPC8540 || \
1228 Number of local access windows. This is fixed per SoC.
1229 If not sure, do not change.
1231 config SYS_FSL_THREADS_PER_CORE
1236 config SYS_NUM_TLBCAMS
1237 int "Number of TLB CAM entries"
1238 default 64 if E500MC
1241 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1242 16 for other E500 SoCs.
1247 config SYS_PPC_E500_USE_DEBUG_TLB
1250 config SYS_PPC_E500_DEBUG_TLB
1251 int "Temporary TLB entry for external debugger"
1252 depends on SYS_PPC_E500_USE_DEBUG_TLB
1253 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1254 default 1 if ARCH_MPC8536
1255 default 2 if ARCH_MPC8572 || \
1263 default 3 if ARCH_P1010 || \
1267 Select a temporary TLB entry to be used during boot to work
1268 around limitations in e500v1 and e500v2 external debugger
1269 support. This reduces the portions of the boot code where
1270 breakpoints and single stepping do not work. The value of this
1271 symbol should be set to the TLB1 entry to be used for this
1272 purpose. If unsure, do not change.
1274 source "board/freescale/b4860qds/Kconfig"
1275 source "board/freescale/bsc9131rdb/Kconfig"
1276 source "board/freescale/bsc9132qds/Kconfig"
1277 source "board/freescale/c29xpcie/Kconfig"
1278 source "board/freescale/corenet_ds/Kconfig"
1279 source "board/freescale/mpc8536ds/Kconfig"
1280 source "board/freescale/mpc8540ads/Kconfig"
1281 source "board/freescale/mpc8541cds/Kconfig"
1282 source "board/freescale/mpc8544ds/Kconfig"
1283 source "board/freescale/mpc8548cds/Kconfig"
1284 source "board/freescale/mpc8555cds/Kconfig"
1285 source "board/freescale/mpc8560ads/Kconfig"
1286 source "board/freescale/mpc8568mds/Kconfig"
1287 source "board/freescale/mpc8569mds/Kconfig"
1288 source "board/freescale/mpc8572ds/Kconfig"
1289 source "board/freescale/p1010rdb/Kconfig"
1290 source "board/freescale/p1022ds/Kconfig"
1291 source "board/freescale/p1023rdb/Kconfig"
1292 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1293 source "board/freescale/p1_twr/Kconfig"
1294 source "board/freescale/p2041rdb/Kconfig"
1295 source "board/freescale/qemu-ppce500/Kconfig"
1296 source "board/freescale/t102xqds/Kconfig"
1297 source "board/freescale/t102xrdb/Kconfig"
1298 source "board/freescale/t1040qds/Kconfig"
1299 source "board/freescale/t104xrdb/Kconfig"
1300 source "board/freescale/t208xqds/Kconfig"
1301 source "board/freescale/t208xrdb/Kconfig"
1302 source "board/freescale/t4qds/Kconfig"
1303 source "board/freescale/t4rdb/Kconfig"
1304 source "board/gdsys/p1022/Kconfig"
1305 source "board/keymile/kmp204x/Kconfig"
1306 source "board/sbc8548/Kconfig"
1307 source "board/socrates/Kconfig"
1308 source "board/varisys/cyrus/Kconfig"
1309 source "board/xes/xpedite520x/Kconfig"
1310 source "board/xes/xpedite537x/Kconfig"
1311 source "board/xes/xpedite550x/Kconfig"
1312 source "board/Arcturus/ucp1020/Kconfig"