4 config PPC_SPINTABLE_COMPATIBLE
8 To comply with ePAPR 1.1, the spin table has been moved to
9 cache-enabled memory. Old OS may not work with this change. A patch
10 is waiting to be accepted for Linux kernel. Other OS needs similar
11 fix to spin table. For OSes with old spin table code, we can enable
12 this temporary fix by setting environmental variable
13 "spin_table_compat". For new OSes, set "spin_table_compat=no". After
14 Linux is fixed, we can remove this macro and related code. For now,
15 it is enabled by default.
21 bool "Enable the 'errata' command"
25 This enables the 'errata' command which displays a list of errata
26 work-arounds which are enabled for the current board.
28 config FSL_PREPBL_ESDHC_BOOT_SECTOR
29 bool "Generate QorIQ pre-PBL eSDHC boot sector"
33 With this option final image would have prepended QorIQ pre-PBL eSDHC
34 boot sector suitable for SD card images. This boot sector instruct
35 BootROM to configure L2 SRAM and eSDHC then load image from SD card
36 into L2 SRAM and finally jump to image entry point.
38 This is alternative to Freescale boot_format tool, but works only for
39 SD card images and only for L2 SRAM booting. U-Boot images generated
40 with this option should not passed to boot_format tool.
42 For other configuration like booting from eSPI or configuring SDRAM
43 please use Freescale boot_format tool without this option. See file
44 doc/README.mpc85xx-sd-spi-boot
46 config FSL_PREPBL_ESDHC_BOOT_SECTOR_START
47 int "QorIQ pre-PBL eSDHC boot sector start offset"
48 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
52 QorIQ pre-PBL eSDHC boot sector may be located on one of the first
53 24 SD card sectors. Select SD card sector on which final U-Boot
54 image (with this boot sector) would be installed.
56 By default first SD card sector (0) is used. But this may be changed
57 to allow installing U-Boot image on some partition (with fixed start
60 Please note that any sector on SD card prior this boot sector must
61 not contain ASCII "BOOT" bytes at sector offset 0x40.
63 config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA
64 int "Relative data sector for QorIQ pre-PBL eSDHC boot sector"
65 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
69 Select data sector from the beginning of QorIQ pre-PBL eSDHC boot
70 sector on which would be stored raw U-Boot image.
72 By default is it second sector (1) which is the first available free
73 sector (on the first sector is stored boot sector). It can be any
74 sector number which offset in bytes can be expressed by 32-bit number.
76 In case this final U-Boot image (with this boot sector) is put on
77 the FAT32 partition into reserved boot area, this data sector needs
78 to be at least 2 (third sector) because FAT32 use second sector for
82 prompt "Target select"
85 config TARGET_SOCRATES
86 bool "Support socrates"
91 bool "Support P3041DS"
94 select BOARD_LATE_INIT if CHAIN_OF_TRUST
100 bool "Support P4080DS"
103 select BOARD_LATE_INIT if CHAIN_OF_TRUST
108 config TARGET_P5040DS
109 bool "Support P5040DS"
112 select BOARD_LATE_INIT if CHAIN_OF_TRUST
114 select SYS_FSL_RAID_ENGINE
118 config TARGET_MPC8548CDS
119 bool "Support MPC8548CDS"
122 select SYS_CACHE_SHIFT_5
124 config TARGET_P1010RDB_PA
125 bool "Support P1010RDB_PA"
127 select BOARD_LATE_INIT if CHAIN_OF_TRUST
130 select SYS_L2_SIZE_256KB
135 config TARGET_P1010RDB_PB
136 bool "Support P1010RDB_PB"
138 select BOARD_LATE_INIT if CHAIN_OF_TRUST
141 select SYS_L2_SIZE_256KB
146 config TARGET_P1020RDB_PC
147 bool "Support P1020RDB-PC"
151 select SYS_L2_SIZE_256KB
156 config TARGET_P1020RDB_PD
157 bool "Support P1020RDB-PD"
161 select SYS_L2_SIZE_256KB
166 config TARGET_P2020RDB
167 bool "Support P2020RDB-PC"
171 select SYS_L2_SIZE_512KB
176 config TARGET_P2041RDB
177 bool "Support P2041RDB"
179 select BOARD_LATE_INIT if CHAIN_OF_TRUST
182 select SYS_L3_SIZE_1024KB
186 config TARGET_QEMU_PPCE500
187 bool "Support qemu-ppce500"
188 select ARCH_QEMU_E500
191 imply OF_HAS_PRIOR_STAGE
193 config TARGET_T1024RDB
194 bool "Support T1024RDB"
196 select BOARD_LATE_INIT if CHAIN_OF_TRUST
199 select FSL_DDR_INTERACTIVE
200 select SYS_L3_SIZE_256KB
204 config TARGET_T1042D4RDB
205 bool "Support T1042D4RDB"
207 select BOARD_LATE_INIT if CHAIN_OF_TRUST
210 select SYS_L3_SIZE_256KB
213 config TARGET_T2080QDS
214 bool "Support T2080QDS"
216 select BOARD_LATE_INIT if CHAIN_OF_TRUST
219 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
220 select FSL_DDR_INTERACTIVE
221 select SYS_L3_SIZE_512KB
224 config TARGET_T2080RDB
225 bool "Support T2080RDB"
227 select BOARD_LATE_INIT if CHAIN_OF_TRUST
230 select SYS_L3_SIZE_512KB
234 config TARGET_T4240RDB
235 bool "Support T4240RDB"
239 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
240 select SYS_L3_SIZE_512KB
244 config TARGET_KMP204X
245 bool "Support kmp204x"
248 config TARGET_KMCENT2
249 bool "Support kmcent2"
254 select SYS_L3_SIZE_256KB
264 select HETROGENOUS_CLUSTERS
265 select SYS_FSL_DDR_VER_47
266 select SYS_FSL_ERRATUM_A004477
267 select SYS_FSL_ERRATUM_A005871
268 select SYS_FSL_ERRATUM_A006379
269 select SYS_FSL_ERRATUM_A006384
270 select SYS_FSL_ERRATUM_A006475
271 select SYS_FSL_ERRATUM_A006593
272 select SYS_FSL_ERRATUM_A007075
273 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
274 select SYS_FSL_ERRATUM_A007212
275 select SYS_FSL_ERRATUM_A009942
276 select SYS_FSL_HAS_DDR3
277 select SYS_FSL_HAS_SEC
278 select SYS_FSL_QORIQ_CHASSIS2
279 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
280 select SYS_FSL_SEC_BE
281 select SYS_FSL_SEC_COMPAT_4
282 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
283 select SYS_FSL_USB1_PHY_ENABLE
296 select HETROGENOUS_CLUSTERS
297 select SYS_FSL_DDR_VER_47
298 select SYS_FSL_ERRATUM_A004477
299 select SYS_FSL_ERRATUM_A005871
300 select SYS_FSL_ERRATUM_A006379
301 select SYS_FSL_ERRATUM_A006384
302 select SYS_FSL_ERRATUM_A006475
303 select SYS_FSL_ERRATUM_A006593
304 select SYS_FSL_ERRATUM_A007075
305 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
306 select SYS_FSL_ERRATUM_A007212
307 select SYS_FSL_ERRATUM_A007907
308 select SYS_FSL_ERRATUM_A009942
309 select SYS_FSL_HAS_DDR3
310 select SYS_FSL_HAS_SEC
311 select SYS_FSL_QORIQ_CHASSIS2
312 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
313 select SYS_FSL_SEC_BE
314 select SYS_FSL_SEC_COMPAT_4
315 select SYS_FSL_SRIO_LIODN
316 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
317 select SYS_FSL_USB1_PHY_ENABLE
327 select SYS_FSL_DDR_VER_44
328 select SYS_FSL_ERRATUM_A004477
329 select SYS_FSL_ERRATUM_A005125
330 select SYS_FSL_ERRATUM_ESDHC111
331 select SYS_FSL_HAS_DDR3
332 select SYS_FSL_HAS_SEC
333 select SYS_FSL_SEC_BE
334 select SYS_FSL_SEC_COMPAT_4
343 select SYS_FSL_DDR_VER_46
344 select SYS_FSL_ERRATUM_A004477
345 select SYS_FSL_ERRATUM_A005125
346 select SYS_FSL_ERRATUM_A005434
347 select SYS_FSL_ERRATUM_ESDHC111
348 select SYS_FSL_ERRATUM_I2C_A004447
349 select SYS_FSL_ERRATUM_IFC_A002769
350 select FSL_PCIE_RESET
351 select SYS_FSL_HAS_DDR3
352 select SYS_FSL_HAS_SEC
353 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
354 select SYS_FSL_SEC_BE
355 select SYS_FSL_SEC_COMPAT_4
356 select SYS_PPC_E500_USE_DEBUG_TLB
367 select SYS_FSL_DDR_VER_46
368 select SYS_FSL_ERRATUM_A005125
369 select SYS_FSL_ERRATUM_ESDHC111
370 select FSL_PCIE_RESET
371 select SYS_FSL_HAS_DDR3
372 select SYS_FSL_HAS_SEC
373 select SYS_FSL_SEC_BE
374 select SYS_FSL_SEC_COMPAT_6
375 select SYS_PPC_E500_USE_DEBUG_TLB
384 select SYS_FSL_ERRATUM_A004508
385 select SYS_FSL_ERRATUM_A005125
386 select FSL_PCIE_RESET
387 select SYS_FSL_HAS_DDR2
388 select SYS_FSL_HAS_DDR3
389 select SYS_FSL_HAS_SEC
390 select SYS_FSL_SEC_BE
391 select SYS_FSL_SEC_COMPAT_2
392 select SYS_PPC_E500_USE_DEBUG_TLB
401 select SYS_FSL_HAS_DDR1
407 select SYS_CACHE_SHIFT_5
408 select SYS_FSL_ERRATUM_A005125
409 select FSL_PCIE_RESET
410 select SYS_FSL_HAS_DDR2
411 select SYS_FSL_HAS_SEC
412 select SYS_FSL_SEC_BE
413 select SYS_FSL_SEC_COMPAT_2
414 select SYS_PPC_E500_USE_DEBUG_TLB
421 select SYS_FSL_ERRATUM_A005125
422 select SYS_FSL_ERRATUM_NMG_DDR120
423 select SYS_FSL_ERRATUM_NMG_LBC103
424 select SYS_FSL_ERRATUM_NMG_ETSEC129
425 select SYS_FSL_ERRATUM_I2C_A004447
426 select FSL_PCIE_RESET
427 select SYS_FSL_HAS_DDR2
428 select SYS_FSL_HAS_DDR1
429 select SYS_FSL_HAS_SEC
431 select SYS_FSL_SEC_BE
432 select SYS_FSL_SEC_COMPAT_2
433 select SYS_PPC_E500_USE_DEBUG_TLB
439 select SYS_FSL_HAS_DDR1
443 select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL
446 select SYS_CACHE_SHIFT_5
447 select SYS_HAS_SERDES
448 select SYS_FSL_ERRATUM_A004477
449 select SYS_FSL_ERRATUM_A004508
450 select SYS_FSL_ERRATUM_A005125
451 select SYS_FSL_ERRATUM_A005275
452 select SYS_FSL_ERRATUM_A006261
453 select SYS_FSL_ERRATUM_A007075
454 select SYS_FSL_ERRATUM_ESDHC111
455 select SYS_FSL_ERRATUM_I2C_A004447
456 select SYS_FSL_ERRATUM_IFC_A002769
457 select SYS_FSL_ERRATUM_P1010_A003549
458 select SYS_FSL_ERRATUM_SEC_A003571
459 select SYS_FSL_ERRATUM_IFC_A003399
460 select FSL_PCIE_RESET
461 select SYS_FSL_HAS_DDR3
462 select SYS_FSL_HAS_SEC
463 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
464 select SYS_FSL_SEC_BE
465 select SYS_FSL_SEC_COMPAT_4
466 select SYS_FSL_USB1_PHY_ENABLE
467 select SYS_PPC_E500_USE_DEBUG_TLB
481 select SYS_FSL_ERRATUM_A004508
482 select SYS_FSL_ERRATUM_A005125
483 select SYS_FSL_ERRATUM_ELBC_A001
484 select SYS_FSL_ERRATUM_ESDHC111
485 select FSL_PCIE_DISABLE_ASPM
486 select SYS_FSL_HAS_DDR3
487 select SYS_FSL_HAS_SEC
488 select SYS_FSL_SEC_BE
489 select SYS_FSL_SEC_COMPAT_2
490 select SYS_PPC_E500_USE_DEBUG_TLB
497 select SYS_CACHE_SHIFT_5
498 select SYS_FSL_ERRATUM_A004508
499 select SYS_FSL_ERRATUM_A005125
500 select SYS_FSL_ERRATUM_ELBC_A001
501 select SYS_FSL_ERRATUM_ESDHC111
502 select FSL_PCIE_DISABLE_ASPM
503 select FSL_PCIE_RESET
504 select SYS_FSL_HAS_DDR3
505 select SYS_FSL_HAS_SEC
506 select SYS_FSL_SEC_BE
507 select SYS_FSL_SEC_COMPAT_2
508 select SYS_PPC_E500_USE_DEBUG_TLB
519 select SYS_FSL_ERRATUM_A004508
520 select SYS_FSL_ERRATUM_A005125
521 select SYS_FSL_ERRATUM_ELBC_A001
522 select SYS_FSL_ERRATUM_ESDHC111
523 select FSL_PCIE_DISABLE_ASPM
524 select FSL_PCIE_RESET
525 select SYS_FSL_HAS_DDR3
526 select SYS_FSL_HAS_SEC
527 select SYS_FSL_SEC_BE
528 select SYS_FSL_SEC_COMPAT_2
529 select SYS_PPC_E500_USE_DEBUG_TLB
540 select SYS_FSL_ERRATUM_A004508
541 select SYS_FSL_ERRATUM_A005125
542 select SYS_FSL_ERRATUM_I2C_A004447
543 select FSL_PCIE_RESET
544 select SYS_FSL_HAS_DDR3
545 select SYS_FSL_HAS_SEC
546 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
547 select SYS_FSL_SEC_BE
548 select SYS_FSL_SEC_COMPAT_4
554 select SYS_FSL_ERRATUM_A004508
555 select SYS_FSL_ERRATUM_A005125
556 select SYS_FSL_ERRATUM_ELBC_A001
557 select SYS_FSL_ERRATUM_ESDHC111
558 select FSL_PCIE_DISABLE_ASPM
559 select FSL_PCIE_RESET
560 select SYS_FSL_HAS_DDR3
561 select SYS_FSL_HAS_SEC
563 select SYS_FSL_SEC_BE
564 select SYS_FSL_SEC_COMPAT_2
565 select SYS_PPC_E500_USE_DEBUG_TLB
577 select SYS_FSL_ERRATUM_A004508
578 select SYS_FSL_ERRATUM_A005125
579 select SYS_FSL_ERRATUM_ELBC_A001
580 select SYS_FSL_ERRATUM_ESDHC111
581 select FSL_PCIE_DISABLE_ASPM
582 select FSL_PCIE_RESET
583 select SYS_FSL_HAS_DDR3
584 select SYS_FSL_HAS_SEC
585 select SYS_FSL_SEC_BE
586 select SYS_FSL_SEC_COMPAT_2
587 select SYS_PPC_E500_USE_DEBUG_TLB
596 select SYS_CACHE_SHIFT_5
597 select SYS_FSL_ERRATUM_A004477
598 select SYS_FSL_ERRATUM_A004508
599 select SYS_FSL_ERRATUM_A005125
600 select SYS_FSL_ERRATUM_ESDHC111
601 select SYS_FSL_ERRATUM_ESDHC_A001
602 select FSL_PCIE_RESET
603 select SYS_FSL_HAS_DDR3
604 select SYS_FSL_HAS_SEC
605 select SYS_FSL_SEC_BE
606 select SYS_FSL_SEC_COMPAT_2
607 select SYS_PPC_E500_USE_DEBUG_TLB
616 select BACKSIDE_L2_CACHE
619 select SYS_CACHE_SHIFT_6
623 select SYS_FSL_ERRATUM_A004510
624 select SYS_FSL_ERRATUM_A004849
625 select SYS_FSL_ERRATUM_A005275
626 select SYS_FSL_ERRATUM_A006261
627 select SYS_FSL_ERRATUM_CPU_A003999
628 select SYS_FSL_ERRATUM_DDR_A003
629 select SYS_FSL_ERRATUM_DDR_A003474
630 select SYS_FSL_ERRATUM_ESDHC111
631 select SYS_FSL_ERRATUM_I2C_A004447
632 select SYS_FSL_ERRATUM_NMG_CPU_A011
633 select SYS_FSL_ERRATUM_SRIO_A004034
634 select SYS_FSL_ERRATUM_USB14
635 select SYS_FSL_HAS_DDR3
636 select SYS_FSL_HAS_SEC
637 select SYS_FSL_QORIQ_CHASSIS1
638 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
639 select SYS_FSL_SEC_BE
640 select SYS_FSL_SEC_COMPAT_4
641 select SYS_FSL_USB1_PHY_ENABLE
642 select SYS_FSL_USB2_PHY_ENABLE
648 select BACKSIDE_L2_CACHE
652 select SYS_CACHE_SHIFT_6
653 select SYS_FSL_DDR_VER_44
654 select SYS_FSL_ERRATUM_A004510
655 select SYS_FSL_ERRATUM_A004849
656 select SYS_FSL_ERRATUM_A005275
657 select SYS_FSL_ERRATUM_A005812
658 select SYS_FSL_ERRATUM_A006261
659 select SYS_FSL_ERRATUM_CPU_A003999
660 select SYS_FSL_ERRATUM_DDR_A003
661 select SYS_FSL_ERRATUM_DDR_A003474
662 select SYS_FSL_ERRATUM_ESDHC111
663 select SYS_FSL_ERRATUM_I2C_A004447
664 select SYS_FSL_ERRATUM_NMG_CPU_A011
665 select SYS_FSL_ERRATUM_SRIO_A004034
666 select SYS_FSL_ERRATUM_USB14
667 select SYS_FSL_HAS_DDR3
668 select SYS_FSL_HAS_SEC
669 select SYS_FSL_QORIQ_CHASSIS1
670 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
671 select SYS_FSL_SEC_BE
672 select SYS_FSL_SEC_COMPAT_4
673 select SYS_FSL_USB1_PHY_ENABLE
674 select SYS_FSL_USB2_PHY_ENABLE
683 select BACKSIDE_L2_CACHE
687 select SYS_CACHE_SHIFT_6
688 select SYS_FSL_DDR_VER_44
689 select SYS_FSL_ERRATUM_A004510
690 select SYS_FSL_ERRATUM_A004580
691 select SYS_FSL_ERRATUM_A004849
692 select SYS_FSL_ERRATUM_A005812
693 select SYS_FSL_ERRATUM_A007075
694 select SYS_FSL_ERRATUM_CPC_A002
695 select SYS_FSL_ERRATUM_CPC_A003
696 select SYS_FSL_ERRATUM_CPU_A003999
697 select SYS_FSL_ERRATUM_DDR_A003
698 select SYS_FSL_ERRATUM_DDR_A003474
699 select SYS_FSL_ERRATUM_ELBC_A001
700 select SYS_FSL_ERRATUM_ESDHC111
701 select SYS_FSL_ERRATUM_ESDHC13
702 select SYS_FSL_ERRATUM_ESDHC135
703 select SYS_FSL_ERRATUM_I2C_A004447
704 select SYS_FSL_ERRATUM_NMG_CPU_A011
705 select SYS_FSL_ERRATUM_SRIO_A004034
706 select SYS_FSL_PCIE_COMPAT_P4080_PCIE
707 select SYS_P4080_ERRATUM_CPU22
708 select SYS_P4080_ERRATUM_PCIE_A003
709 select SYS_P4080_ERRATUM_SERDES8
710 select SYS_P4080_ERRATUM_SERDES9
711 select SYS_P4080_ERRATUM_SERDES_A001
712 select SYS_P4080_ERRATUM_SERDES_A005
713 select SYS_FSL_HAS_DDR3
714 select SYS_FSL_HAS_SEC
715 select SYS_FSL_QORIQ_CHASSIS1
717 select SYS_FSL_SEC_BE
718 select SYS_FSL_SEC_COMPAT_4
726 select BACKSIDE_L2_CACHE
730 select SYS_CACHE_SHIFT_6
731 select SYS_FSL_DDR_VER_44
732 select SYS_FSL_ERRATUM_A004510
733 select SYS_FSL_ERRATUM_A004699
734 select SYS_FSL_ERRATUM_A005275
735 select SYS_FSL_ERRATUM_A005812
736 select SYS_FSL_ERRATUM_A006261
737 select SYS_FSL_ERRATUM_DDR_A003
738 select SYS_FSL_ERRATUM_DDR_A003474
739 select SYS_FSL_ERRATUM_ESDHC111
740 select SYS_FSL_ERRATUM_USB14
741 select SYS_FSL_HAS_DDR3
742 select SYS_FSL_HAS_SEC
743 select SYS_FSL_QORIQ_CHASSIS1
744 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
745 select SYS_FSL_SEC_BE
746 select SYS_FSL_SEC_COMPAT_4
747 select SYS_FSL_USB1_PHY_ENABLE
748 select SYS_FSL_USB2_PHY_ENABLE
755 config ARCH_QEMU_E500
757 select SYS_CACHE_SHIFT_5
761 select BACKSIDE_L2_CACHE
766 select SYS_CACHE_SHIFT_6
768 select SYS_FSL_DDR_VER_50
769 select SYS_FSL_ERRATUM_A008378
770 select SYS_FSL_ERRATUM_A008109
771 select SYS_FSL_ERRATUM_A009663
772 select SYS_FSL_ERRATUM_A009942
773 select SYS_FSL_ERRATUM_ESDHC111
774 select SYS_FSL_HAS_DDR3
775 select SYS_FSL_HAS_DDR4
776 select SYS_FSL_HAS_SEC
777 select SYS_FSL_QORIQ_CHASSIS2
778 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
779 select SYS_FSL_SEC_BE
780 select SYS_FSL_SEC_COMPAT_5
781 select SYS_FSL_SINGLE_SOURCE_CLK
782 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
783 select SYS_FSL_USB_DUAL_PHY_ENABLE
792 select BACKSIDE_L2_CACHE
797 select SYS_CACHE_SHIFT_6
800 select SYS_FSL_DDR_VER_50
801 select SYS_FSL_ERRATUM_A008044
802 select SYS_FSL_ERRATUM_A008378
803 select SYS_FSL_ERRATUM_A008109
804 select SYS_FSL_ERRATUM_A009663
805 select SYS_FSL_ERRATUM_A009942
806 select SYS_FSL_ERRATUM_ESDHC111
807 select SYS_FSL_HAS_DDR3
808 select SYS_FSL_HAS_DDR4
809 select SYS_FSL_HAS_SEC
810 select SYS_FSL_QORIQ_CHASSIS2
811 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
812 select SYS_FSL_SEC_BE
813 select SYS_FSL_SEC_COMPAT_5
814 select SYS_FSL_SINGLE_SOURCE_CLK
815 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
816 select SYS_FSL_USB_DUAL_PHY_ENABLE
824 select BACKSIDE_L2_CACHE
829 select SYS_CACHE_SHIFT_6
832 select SYS_FSL_DDR_VER_50
833 select SYS_FSL_ERRATUM_A008044
834 select SYS_FSL_ERRATUM_A008378
835 select SYS_FSL_ERRATUM_A008109
836 select SYS_FSL_ERRATUM_A009663
837 select SYS_FSL_ERRATUM_A009942
838 select SYS_FSL_ERRATUM_ESDHC111
839 select SYS_FSL_HAS_DDR3
840 select SYS_FSL_HAS_DDR4
841 select SYS_FSL_HAS_SEC
842 select SYS_FSL_QORIQ_CHASSIS2
843 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
844 select SYS_FSL_SEC_BE
845 select SYS_FSL_SEC_COMPAT_5
846 select SYS_FSL_SINGLE_SOURCE_CLK
847 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
848 select SYS_FSL_USB_DUAL_PHY_ENABLE
860 select SYS_CACHE_SHIFT_6
861 select SYS_DPAA_DCE if !NOBQFMAN
862 select SYS_DPAA_FMAN if !NOBQFMAN
863 select SYS_DPAA_PME if !NOBQFMAN
864 select SYS_DPAA_RMAN if !NOBQFMAN
865 select SYS_FSL_DDR_VER_47
866 select SYS_FSL_ERRATUM_A006379
867 select SYS_FSL_ERRATUM_A006593
868 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
869 select SYS_FSL_ERRATUM_A007212
870 select SYS_FSL_ERRATUM_A007815
871 select SYS_FSL_ERRATUM_A007907
872 select SYS_FSL_ERRATUM_A008109
873 select SYS_FSL_ERRATUM_A009942
874 select SYS_FSL_ERRATUM_ESDHC111
875 select FSL_PCIE_RESET
876 select SYS_FSL_HAS_DDR3
877 select SYS_FSL_HAS_SEC
878 select SYS_FSL_QORIQ_CHASSIS2
879 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
880 select SYS_FSL_SEC_BE
881 select SYS_FSL_SEC_COMPAT_4
882 select SYS_FSL_SRIO_LIODN
883 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
884 select SYS_FSL_USB_DUAL_PHY_ENABLE
885 select SYS_PMAN if !NOBQFMAN
900 select SYS_CACHE_SHIFT_6
901 select SYS_DPAA_DCE if !NOBQFMAN
902 select SYS_DPAA_FMAN if !NOBQFMAN
903 select SYS_DPAA_PME if !NOBQFMAN
904 select SYS_DPAA_RMAN if !NOBQFMAN
905 select SYS_FSL_DDR_VER_47
906 select SYS_FSL_ERRATUM_A004468
907 select SYS_FSL_ERRATUM_A005871
908 select SYS_FSL_ERRATUM_A006261
909 select SYS_FSL_ERRATUM_A006379
910 select SYS_FSL_ERRATUM_A006593
911 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
912 select SYS_FSL_ERRATUM_A007798
913 select SYS_FSL_ERRATUM_A007815
914 select SYS_FSL_ERRATUM_A007907
915 select SYS_FSL_ERRATUM_A008109
916 select SYS_FSL_ERRATUM_A009942
917 select SYS_FSL_HAS_DDR3
918 select SYS_FSL_HAS_SEC
919 select SYS_FSL_QORIQ_CHASSIS2
920 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
921 select SYS_FSL_SEC_BE
922 select SYS_FSL_SEC_COMPAT_4
923 select SYS_FSL_SRIO_LIODN
924 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
925 select SYS_FSL_USB_DUAL_PHY_ENABLE
926 select SYS_PMAN if !NOBQFMAN
934 config MPC85XX_HAVE_RESET_VECTOR
935 bool "Indicate reset vector at CFG_RESET_VECTOR_ADDRESS - 0xffc"
939 bool "toggle branch predition"
949 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
956 Enble PowerPC E500MC core
965 Enable PowerPC E6500 core
973 Use Freescale common code for Local Access Window
975 config HETROGENOUS_CLUSTERS
979 int "Maximum number of CPUs permitted for MPC85xx"
980 default 12 if ARCH_T4240
981 default 8 if ARCH_P4080
982 default 4 if ARCH_B4860 || \
989 default 2 if ARCH_B4420 || \
1000 Set this number to the maximum number of possible CPUs in the SoC.
1001 SoCs may have multiple clusters with each cluster may have multiple
1002 ports. If some ports are reserved but higher ports are used for
1003 cores, count the reserved ports. This will allocate enough memory
1004 in spin table to properly handle all cores.
1006 config SYS_CCSRBAR_DEFAULT
1007 hex "Default CCSRBAR address"
1008 default 0xff700000 if ARCH_BSC9131 || \
1023 default 0xff600000 if ARCH_P1023
1024 default 0xfe000000 if ARCH_B4420 || \
1035 default 0xe0000000 if ARCH_QEMU_E500
1037 Default value of CCSRBAR comes from power-on-reset. It
1038 is fixed on each SoC. Some SoCs can have different value
1039 if changed by pre-boot regime. The value here must match
1040 the current value in SoC. If not sure, do not change.
1048 config SYS_DPAA_RMAN
1051 config A003399_NOR_WORKAROUND
1054 Enables a workaround for IFC erratum A003399. It is only required
1057 config A008044_WORKAROUND
1060 Enables a workaround for T1040/T1042 erratum A008044. It is only
1061 required during NAND boot and valid for Rev 1.0 SoC revision
1063 config SYS_FSL_ERRATUM_A004468
1066 config SYS_FSL_ERRATUM_A004477
1069 config SYS_FSL_ERRATUM_A004508
1072 config SYS_FSL_ERRATUM_A004580
1075 config SYS_FSL_ERRATUM_A004699
1078 config SYS_FSL_ERRATUM_A004849
1081 config SYS_FSL_ERRATUM_A004510
1084 config SYS_FSL_ERRATUM_A004510_SVR_REV
1086 depends on SYS_FSL_ERRATUM_A004510
1087 default 0x20 if ARCH_P4080
1090 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1092 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1095 config SYS_FSL_ERRATUM_A005125
1098 config SYS_FSL_ERRATUM_A005434
1101 config SYS_FSL_ERRATUM_A005812
1104 config SYS_FSL_ERRATUM_A005871
1107 config SYS_FSL_ERRATUM_A005275
1110 config SYS_FSL_ERRATUM_A006261
1113 config SYS_FSL_ERRATUM_A006379
1116 config SYS_FSL_ERRATUM_A006384
1119 config SYS_FSL_ERRATUM_A006475
1122 config SYS_FSL_ERRATUM_A006593
1125 config SYS_FSL_ERRATUM_A007075
1128 config SYS_FSL_ERRATUM_A007186
1131 config SYS_FSL_ERRATUM_A007212
1134 config SYS_FSL_ERRATUM_A007815
1137 config SYS_FSL_ERRATUM_A007798
1140 config SYS_FSL_ERRATUM_A007907
1143 config SYS_FSL_ERRATUM_A008044
1145 select A008044_WORKAROUND if MTD_RAW_NAND
1147 config SYS_FSL_ERRATUM_CPC_A002
1150 config SYS_FSL_ERRATUM_CPC_A003
1153 config SYS_FSL_ERRATUM_CPU_A003999
1156 config SYS_FSL_ERRATUM_ELBC_A001
1159 config SYS_FSL_ERRATUM_I2C_A004447
1162 config SYS_FSL_A004447_SVR_REV
1164 depends on SYS_FSL_ERRATUM_I2C_A004447
1165 default 0x00 if ARCH_MPC8548
1166 default 0x10 if ARCH_P1010
1167 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1168 default 0x20 if ARCH_P3041 || ARCH_P4080
1170 config SYS_FSL_ERRATUM_IFC_A002769
1173 config SYS_FSL_ERRATUM_IFC_A003399
1176 config SYS_FSL_ERRATUM_NMG_CPU_A011
1179 config SYS_FSL_ERRATUM_NMG_ETSEC129
1182 config SYS_FSL_ERRATUM_NMG_LBC103
1185 config SYS_FSL_ERRATUM_P1010_A003549
1188 config SYS_FSL_ERRATUM_SATA_A001
1191 config SYS_FSL_ERRATUM_SEC_A003571
1194 config SYS_FSL_ERRATUM_SRIO_A004034
1197 config SYS_FSL_ERRATUM_USB14
1200 config SYS_HAS_SERDES
1203 config SYS_P4080_ERRATUM_CPU22
1206 config SYS_P4080_ERRATUM_PCIE_A003
1209 config SYS_P4080_ERRATUM_SERDES8
1212 config SYS_P4080_ERRATUM_SERDES9
1215 config SYS_P4080_ERRATUM_SERDES_A001
1218 config SYS_P4080_ERRATUM_SERDES_A005
1221 config FSL_PCIE_DISABLE_ASPM
1224 config FSL_PCIE_RESET
1230 config SYS_FSL_RAID_ENGINE
1236 config SYS_FSL_QORIQ_CHASSIS1
1239 config SYS_FSL_QORIQ_CHASSIS2
1242 config SYS_FSL_NUM_LAWS
1243 int "Number of local access windows"
1245 default 32 if ARCH_B4420 || \
1253 default 16 if ARCH_T1024 || \
1256 default 12 if ARCH_BSC9131 || \
1268 default 10 if ARCH_MPC8544 || \
1270 default 8 if ARCH_MPC8540 || \
1273 Number of local access windows. This is fixed per SoC.
1274 If not sure, do not change.
1276 config SYS_FSL_CORES_PER_CLUSTER
1278 depends on SYS_FSL_QORIQ_CHASSIS2
1279 default 4 if ARCH_B4860 || ARCH_T2080 || ARCH_T4240
1280 default 2 if ARCH_B4420
1281 default 1 if ARCH_T1024 || ARCH_T1040 || ARCH_T1042
1283 config SYS_FSL_THREADS_PER_CORE
1285 depends on SYS_FSL_QORIQ_CHASSIS2
1289 config SYS_NUM_TLBCAMS
1290 int "Number of TLB CAM entries"
1291 default 64 if E500MC
1294 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1295 16 for other E500 SoCs.
1298 bool "Enable L2 cache support"
1300 if HETROGENOUS_CLUSTERS
1308 config PPC_CLUSTER_START
1312 config DSP_CLUSTER_START
1324 config SYS_ETVPE_CLK
1330 default 12 if ARCH_B4860
1331 default 2 if ARCH_B4420
1334 config SYS_L2_SIZE_256KB
1337 config SYS_L2_SIZE_512KB
1342 default 262144 if SYS_L2_SIZE_256KB
1343 default 524288 if SYS_L2_SIZE_512KB
1345 config BACKSIDE_L2_CACHE
1348 config SYS_L3_SIZE_256KB
1351 config SYS_L3_SIZE_512KB
1354 config SYS_L3_SIZE_1024KB
1359 default 262144 if SYS_L3_SIZE_256KB
1360 default 524288 if SYS_L3_SIZE_512KB
1361 default 1048576 if SYS_L3_SIZE_512KB
1366 config SYS_PPC_E500_USE_DEBUG_TLB
1372 config SYS_PPC_E500_DEBUG_TLB
1373 int "Temporary TLB entry for external debugger"
1374 depends on SYS_PPC_E500_USE_DEBUG_TLB
1375 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1376 default 1 if ARCH_MPC8536
1377 default 2 if ARCH_P1011 || \
1383 default 3 if ARCH_P1010 || \
1387 Select a temporary TLB entry to be used during boot to work
1388 around limitations in e500v1 and e500v2 external debugger
1389 support. This reduces the portions of the boot code where
1390 breakpoints and single stepping do not work. The value of this
1391 symbol should be set to the TLB1 entry to be used for this
1392 purpose. If unsure, do not change.
1394 config SYS_FSL_IFC_CLK_DIV
1395 int "Divider of platform clock"
1397 default 2 if ARCH_B4420 || \
1405 Defines divider of platform clock(clock input to
1408 config SYS_FSL_LBC_CLK_DIV
1409 int "Divider of platform clock"
1410 depends on FSL_ELBC || ARCH_MPC8540 || \
1414 default 2 if ARCH_P2041 || \
1421 Defines divider of platform clock(clock input to
1424 config ENABLE_36BIT_PHYS
1425 bool "Enable 36bit physical address space support"
1427 config SYS_BOOK3E_HV
1428 bool "Category E.HV is supported"
1438 config SYS_CPC_REINIT_F
1441 The CPC is configured as SRAM at the time of U-Boot entry and is
1442 required to be re-initialized.
1447 config SYS_CACHE_STASHING
1448 bool "Enable cache stashing"
1450 config SYS_FSL_PCIE_COMPAT_P4080_PCIE
1453 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
1456 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
1459 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
1462 config SYS_FSL_PCIE_COMPAT
1464 depends on FSL_CORENET
1465 default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE
1466 default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
1467 default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
1468 default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
1470 Defines the string to utilize when trying to match PCIe device tree
1471 nodes for the given platform.
1473 config SYS_FSL_SINGLE_SOURCE_CLK
1476 config SYS_FSL_SRIO_LIODN
1479 config SYS_FSL_TBCLK_DIV
1481 default 32 if ARCH_P2041 || ARCH_P3041
1482 default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
1483 ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
1484 ARCH_T1024 || ARCH_T2080
1487 Defines the core time base clock divider ratio compared to the system
1488 clock. On most PQ3 devices this is 8, on newer QorIQ devices it can
1489 be 16 or 32. The ratio varies from SoC to Soc.
1491 config SYS_FSL_USB1_PHY_ENABLE
1494 config SYS_FSL_USB2_PHY_ENABLE
1497 config SYS_FSL_USB_DUAL_PHY_ENABLE
1500 config SYS_MPC85XX_NO_RESETVEC
1501 bool "Discard resetvec section and move bootpg section up"
1502 depends on MPC85xx && !MPC85XX_HAVE_RESET_VECTOR
1504 If this variable is specified, the section .resetvec is not kept and
1505 the section .bootpg is placed in the previous 4k of the .text section.
1507 config SPL_SYS_MPC85XX_NO_RESETVEC
1508 bool "Discard resetvec section and move bootpg section up, in SPL"
1509 depends on MPC85xx && SPL && !MPC85XX_HAVE_RESET_VECTOR
1511 If this variable is specified, the section .resetvec is not kept and
1512 the section .bootpg is placed in the previous 4k of the .text section,
1513 of the SPL portion of the binary.
1515 config TPL_SYS_MPC85XX_NO_RESETVEC
1516 bool "Discard resetvec section and move bootpg section up, in TPL"
1517 depends on MPC85xx && TPL && !MPC85XX_HAVE_RESET_VECTOR
1519 If this variable is specified, the section .resetvec is not kept and
1520 the section .bootpg is placed in the previous 4k of the .text section,
1521 of the SPL portion of the binary.
1526 source "board/emulation/qemu-ppce500/Kconfig"
1527 source "board/freescale/mpc8548cds/Kconfig"
1528 source "board/freescale/p1010rdb/Kconfig"
1529 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1530 source "board/freescale/p2041rdb/Kconfig"
1531 source "board/freescale/t102xrdb/Kconfig"
1532 source "board/freescale/t104xrdb/Kconfig"
1533 source "board/freescale/t208xqds/Kconfig"
1534 source "board/freescale/t208xrdb/Kconfig"
1535 source "board/freescale/t4rdb/Kconfig"
1536 source "board/socrates/Kconfig"