arch/powerpc/cpu/mpc85xx/Kconfig

   1 menu "mpc85xx CPU"
   2         depends on MPC85xx
   3
   4 config SYS_CPU
   5         default "mpc85xx"
   6
   7 choice
   8         prompt "Target select"
   9         optional
  10
  11 config TARGET_SBC8548
  12         bool "Support sbc8548"
  13         select ARCH_MPC8548
  14
  15 config TARGET_SOCRATES
  16         bool "Support socrates"
  17         select ARCH_MPC8544
  18
  19 config TARGET_B4420QDS
  20         bool "Support B4420QDS"
  21         select ARCH_B4420
  22         select SUPPORT_SPL
  23         select PHYS_64BIT
  24
  25 config TARGET_B4860QDS
  26         bool "Support B4860QDS"
  27         select ARCH_B4860
  28         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  29         select SUPPORT_SPL
  30         select PHYS_64BIT
  31
  32 config TARGET_BSC9131RDB
  33         bool "Support BSC9131RDB"
  34         select ARCH_BSC9131
  35         select SUPPORT_SPL
  36         select BOARD_EARLY_INIT_F
  37
  38 config TARGET_BSC9132QDS
  39         bool "Support BSC9132QDS"
  40         select ARCH_BSC9132
  41         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  42         select SUPPORT_SPL
  43         select BOARD_EARLY_INIT_F
  44
  45 config TARGET_C29XPCIE
  46         bool "Support C29XPCIE"
  47         select ARCH_C29X
  48         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  49         select SUPPORT_SPL
  50         select SUPPORT_TPL
  51         select PHYS_64BIT
  52
  53 config TARGET_P3041DS
  54         bool "Support P3041DS"
  55         select PHYS_64BIT
  56         select ARCH_P3041
  57         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  58
  59 config TARGET_P4080DS
  60         bool "Support P4080DS"
  61         select PHYS_64BIT
  62         select ARCH_P4080
  63         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  64
  65 config TARGET_P5020DS
  66         bool "Support P5020DS"
  67         select PHYS_64BIT
  68         select ARCH_P5020
  69         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  70
  71 config TARGET_P5040DS
  72         bool "Support P5040DS"
  73         select PHYS_64BIT
  74         select ARCH_P5040
  75         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  76
  77 config TARGET_MPC8536DS
  78         bool "Support MPC8536DS"
  79         select ARCH_MPC8536
  80 # Use DDR3 controller with DDR2 DIMMs on this board
  81         select SYS_FSL_DDRC_GEN3
  82
  83 config TARGET_MPC8540ADS
  84         bool "Support MPC8540ADS"
  85         select ARCH_MPC8540
  86
  87 config TARGET_MPC8541CDS
  88         bool "Support MPC8541CDS"
  89         select ARCH_MPC8541
  90
  91 config TARGET_MPC8544DS
  92         bool "Support MPC8544DS"
  93         select ARCH_MPC8544
  94
  95 config TARGET_MPC8548CDS
  96         bool "Support MPC8548CDS"
  97         select ARCH_MPC8548
  98
  99 config TARGET_MPC8555CDS
 100         bool "Support MPC8555CDS"
 101         select ARCH_MPC8555
 102
 103 config TARGET_MPC8560ADS
 104         bool "Support MPC8560ADS"
 105         select ARCH_MPC8560
 106
 107 config TARGET_MPC8568MDS
 108         bool "Support MPC8568MDS"
 109         select ARCH_MPC8568
 110
 111 config TARGET_MPC8569MDS
 112         bool "Support MPC8569MDS"
 113         select ARCH_MPC8569
 114
 115 config TARGET_MPC8572DS
 116         bool "Support MPC8572DS"
 117         select ARCH_MPC8572
 118 # Use DDR3 controller with DDR2 DIMMs on this board
 119         select SYS_FSL_DDRC_GEN3
 120
 121 config TARGET_P1010RDB_PA
 122         bool "Support P1010RDB_PA"
 123         select ARCH_P1010
 124         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 125         select SUPPORT_SPL
 126         select SUPPORT_TPL
 127
 128 config TARGET_P1010RDB_PB
 129         bool "Support P1010RDB_PB"
 130         select ARCH_P1010
 131         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 132         select SUPPORT_SPL
 133         select SUPPORT_TPL
 134
 135 config TARGET_P1022DS
 136         bool "Support P1022DS"
 137         select ARCH_P1022
 138         select SUPPORT_SPL
 139         select SUPPORT_TPL
 140
 141 config TARGET_P1023RDB
 142         bool "Support P1023RDB"
 143         select ARCH_P1023
 144
 145 config TARGET_P1020MBG
 146         bool "Support P1020MBG-PC"
 147         select SUPPORT_SPL
 148         select SUPPORT_TPL
 149         select ARCH_P1020
 150
 151 config TARGET_P1020RDB_PC
 152         bool "Support P1020RDB-PC"
 153         select SUPPORT_SPL
 154         select SUPPORT_TPL
 155         select ARCH_P1020
 156
 157 config TARGET_P1020RDB_PD
 158         bool "Support P1020RDB-PD"
 159         select SUPPORT_SPL
 160         select SUPPORT_TPL
 161         select ARCH_P1020
 162
 163 config TARGET_P1020UTM
 164         bool "Support P1020UTM"
 165         select SUPPORT_SPL
 166         select SUPPORT_TPL
 167         select ARCH_P1020
 168
 169 config TARGET_P1021RDB
 170         bool "Support P1021RDB"
 171         select SUPPORT_SPL
 172         select SUPPORT_TPL
 173         select ARCH_P1021
 174
 175 config TARGET_P1024RDB
 176         bool "Support P1024RDB"
 177         select SUPPORT_SPL
 178         select SUPPORT_TPL
 179         select ARCH_P1024
 180
 181 config TARGET_P1025RDB
 182         bool "Support P1025RDB"
 183         select SUPPORT_SPL
 184         select SUPPORT_TPL
 185         select ARCH_P1025
 186
 187 config TARGET_P2020RDB
 188         bool "Support P2020RDB-PC"
 189         select SUPPORT_SPL
 190         select SUPPORT_TPL
 191         select ARCH_P2020
 192
 193 config TARGET_P1_TWR
 194         bool "Support p1_twr"
 195         select ARCH_P1025
 196
 197 config TARGET_P2041RDB
 198         bool "Support P2041RDB"
 199         select ARCH_P2041
 200         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 201         select PHYS_64BIT
 202
 203 config TARGET_QEMU_PPCE500
 204         bool "Support qemu-ppce500"
 205         select ARCH_QEMU_E500
 206         select PHYS_64BIT
 207
 208 config TARGET_T1024QDS
 209         bool "Support T1024QDS"
 210         select ARCH_T1024
 211         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 212         select SUPPORT_SPL
 213         select PHYS_64BIT
 214
 215 config TARGET_T1023RDB
 216         bool "Support T1023RDB"
 217         select ARCH_T1023
 218         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 219         select SUPPORT_SPL
 220         select PHYS_64BIT
 221
 222 config TARGET_T1024RDB
 223         bool "Support T1024RDB"
 224         select ARCH_T1024
 225         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 226         select SUPPORT_SPL
 227         select PHYS_64BIT
 228
 229 config TARGET_T1040QDS
 230         bool "Support T1040QDS"
 231         select ARCH_T1040
 232         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 233         select PHYS_64BIT
 234
 235 config TARGET_T1040RDB
 236         bool "Support T1040RDB"
 237         select ARCH_T1040
 238         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 239         select SUPPORT_SPL
 240         select PHYS_64BIT
 241
 242 config TARGET_T1040D4RDB
 243         bool "Support T1040D4RDB"
 244         select ARCH_T1040
 245         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 246         select SUPPORT_SPL
 247         select PHYS_64BIT
 248
 249 config TARGET_T1042RDB
 250         bool "Support T1042RDB"
 251         select ARCH_T1042
 252         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 253         select SUPPORT_SPL
 254         select PHYS_64BIT
 255
 256 config TARGET_T1042D4RDB
 257         bool "Support T1042D4RDB"
 258         select ARCH_T1042
 259         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 260         select SUPPORT_SPL
 261         select PHYS_64BIT
 262
 263 config TARGET_T1042RDB_PI
 264         bool "Support T1042RDB_PI"
 265         select ARCH_T1042
 266         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 267         select SUPPORT_SPL
 268         select PHYS_64BIT
 269
 270 config TARGET_T2080QDS
 271         bool "Support T2080QDS"
 272         select ARCH_T2080
 273         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 274         select SUPPORT_SPL
 275         select PHYS_64BIT
 276
 277 config TARGET_T2080RDB
 278         bool "Support T2080RDB"
 279         select ARCH_T2080
 280         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 281         select SUPPORT_SPL
 282         select PHYS_64BIT
 283
 284 config TARGET_T2081QDS
 285         bool "Support T2081QDS"
 286         select ARCH_T2081
 287         select SUPPORT_SPL
 288         select PHYS_64BIT
 289
 290 config TARGET_T4160QDS
 291         bool "Support T4160QDS"
 292         select ARCH_T4160
 293         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 294         select SUPPORT_SPL
 295         select PHYS_64BIT
 296
 297 config TARGET_T4160RDB
 298         bool "Support T4160RDB"
 299         select ARCH_T4160
 300         select SUPPORT_SPL
 301         select PHYS_64BIT
 302
 303 config TARGET_T4240QDS
 304         bool "Support T4240QDS"
 305         select ARCH_T4240
 306         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 307         select SUPPORT_SPL
 308         select PHYS_64BIT
 309
 310 config TARGET_T4240RDB
 311         bool "Support T4240RDB"
 312         select ARCH_T4240
 313         select SUPPORT_SPL
 314         select PHYS_64BIT
 315
 316 config TARGET_CONTROLCENTERD
 317         bool "Support controlcenterd"
 318         select ARCH_P1022
 319
 320 config TARGET_KMP204X
 321         bool "Support kmp204x"
 322         select ARCH_P2041
 323         select PHYS_64BIT
 324         imply CMD_CRAMFS
 325         imply FS_CRAMFS
 326
 327 config TARGET_XPEDITE520X
 328         bool "Support xpedite520x"
 329         select ARCH_MPC8548
 330
 331 config TARGET_XPEDITE537X
 332         bool "Support xpedite537x"
 333         select ARCH_MPC8572
 334 # Use DDR3 controller with DDR2 DIMMs on this board
 335         select SYS_FSL_DDRC_GEN3
 336
 337 config TARGET_XPEDITE550X
 338         bool "Support xpedite550x"
 339         select ARCH_P2020
 340
 341 config TARGET_UCP1020
 342         bool "Support uCP1020"
 343         select ARCH_P1020
 344
 345 config TARGET_CYRUS_P5020
 346         bool "Support Varisys Cyrus P5020"
 347         select ARCH_P5020
 348         select PHYS_64BIT
 349
 350 config TARGET_CYRUS_P5040
 351          bool "Support Varisys Cyrus P5040"
 352         select ARCH_P5040
 353         select PHYS_64BIT
 354
 355 endchoice
 356
 357 config ARCH_B4420
 358         bool
 359         select E500MC
 360         select E6500
 361         select FSL_LAW
 362         select SYS_FSL_DDR_VER_47
 363         select SYS_FSL_ERRATUM_A004477
 364         select SYS_FSL_ERRATUM_A005871
 365         select SYS_FSL_ERRATUM_A006379
 366         select SYS_FSL_ERRATUM_A006384
 367         select SYS_FSL_ERRATUM_A006475
 368         select SYS_FSL_ERRATUM_A006593
 369         select SYS_FSL_ERRATUM_A007075
 370         select SYS_FSL_ERRATUM_A007186
 371         select SYS_FSL_ERRATUM_A007212
 372         select SYS_FSL_ERRATUM_A009942
 373         select SYS_FSL_HAS_DDR3
 374         select SYS_FSL_HAS_SEC
 375         select SYS_FSL_QORIQ_CHASSIS2
 376         select SYS_FSL_SEC_BE
 377         select SYS_FSL_SEC_COMPAT_4
 378         select SYS_PPC64
 379         select FSL_IFC
 380
 381 config ARCH_B4860
 382         bool
 383         select E500MC
 384         select E6500
 385         select FSL_LAW
 386         select SYS_FSL_DDR_VER_47
 387         select SYS_FSL_ERRATUM_A004477
 388         select SYS_FSL_ERRATUM_A005871
 389         select SYS_FSL_ERRATUM_A006379
 390         select SYS_FSL_ERRATUM_A006384
 391         select SYS_FSL_ERRATUM_A006475
 392         select SYS_FSL_ERRATUM_A006593
 393         select SYS_FSL_ERRATUM_A007075
 394         select SYS_FSL_ERRATUM_A007186
 395         select SYS_FSL_ERRATUM_A007212
 396         select SYS_FSL_ERRATUM_A007907
 397         select SYS_FSL_ERRATUM_A009942
 398         select SYS_FSL_HAS_DDR3
 399         select SYS_FSL_HAS_SEC
 400         select SYS_FSL_QORIQ_CHASSIS2
 401         select SYS_FSL_SEC_BE
 402         select SYS_FSL_SEC_COMPAT_4
 403         select SYS_PPC64
 404         select FSL_IFC
 405
 406 config ARCH_BSC9131
 407         bool
 408         select FSL_LAW
 409         select SYS_FSL_DDR_VER_44
 410         select SYS_FSL_ERRATUM_A004477
 411         select SYS_FSL_ERRATUM_A005125
 412         select SYS_FSL_ERRATUM_ESDHC111
 413         select SYS_FSL_HAS_DDR3
 414         select SYS_FSL_HAS_SEC
 415         select SYS_FSL_SEC_BE
 416         select SYS_FSL_SEC_COMPAT_4
 417         select FSL_IFC
 418
 419 config ARCH_BSC9132
 420         bool
 421         select FSL_LAW
 422         select SYS_FSL_DDR_VER_46
 423         select SYS_FSL_ERRATUM_A004477
 424         select SYS_FSL_ERRATUM_A005125
 425         select SYS_FSL_ERRATUM_A005434
 426         select SYS_FSL_ERRATUM_ESDHC111
 427         select SYS_FSL_ERRATUM_I2C_A004447
 428         select SYS_FSL_ERRATUM_IFC_A002769
 429         select SYS_FSL_HAS_DDR3
 430         select SYS_FSL_HAS_SEC
 431         select SYS_FSL_SEC_BE
 432         select SYS_FSL_SEC_COMPAT_4
 433         select SYS_PPC_E500_USE_DEBUG_TLB
 434         select FSL_IFC
 435
 436 config ARCH_C29X
 437         bool
 438         select FSL_LAW
 439         select SYS_FSL_DDR_VER_46
 440         select SYS_FSL_ERRATUM_A005125
 441         select SYS_FSL_ERRATUM_ESDHC111
 442         select SYS_FSL_HAS_DDR3
 443         select SYS_FSL_HAS_SEC
 444         select SYS_FSL_SEC_BE
 445         select SYS_FSL_SEC_COMPAT_6
 446         select SYS_PPC_E500_USE_DEBUG_TLB
 447         select FSL_IFC
 448
 449 config ARCH_MPC8536
 450         bool
 451         select FSL_LAW
 452         select SYS_FSL_ERRATUM_A004508
 453         select SYS_FSL_ERRATUM_A005125
 454         select SYS_FSL_HAS_DDR2
 455         select SYS_FSL_HAS_DDR3
 456         select SYS_FSL_HAS_SEC
 457         select SYS_FSL_SEC_BE
 458         select SYS_FSL_SEC_COMPAT_2
 459         select SYS_PPC_E500_USE_DEBUG_TLB
 460         select FSL_ELBC
 461
 462 config ARCH_MPC8540
 463         bool
 464         select FSL_LAW
 465         select SYS_FSL_HAS_DDR1
 466
 467 config ARCH_MPC8541
 468         bool
 469         select FSL_LAW
 470         select SYS_FSL_HAS_DDR1
 471         select SYS_FSL_HAS_SEC
 472         select SYS_FSL_SEC_BE
 473         select SYS_FSL_SEC_COMPAT_2
 474
 475 config ARCH_MPC8544
 476         bool
 477         select FSL_LAW
 478         select SYS_FSL_ERRATUM_A005125
 479         select SYS_FSL_HAS_DDR2
 480         select SYS_FSL_HAS_SEC
 481         select SYS_FSL_SEC_BE
 482         select SYS_FSL_SEC_COMPAT_2
 483         select SYS_PPC_E500_USE_DEBUG_TLB
 484         select FSL_ELBC
 485
 486 config ARCH_MPC8548
 487         bool
 488         select FSL_LAW
 489         select SYS_FSL_ERRATUM_A005125
 490         select SYS_FSL_ERRATUM_NMG_DDR120
 491         select SYS_FSL_ERRATUM_NMG_LBC103
 492         select SYS_FSL_ERRATUM_NMG_ETSEC129
 493         select SYS_FSL_ERRATUM_I2C_A004447
 494         select SYS_FSL_HAS_DDR2
 495         select SYS_FSL_HAS_DDR1
 496         select SYS_FSL_HAS_SEC
 497         select SYS_FSL_SEC_BE
 498         select SYS_FSL_SEC_COMPAT_2
 499         select SYS_PPC_E500_USE_DEBUG_TLB
 500
 501 config ARCH_MPC8555
 502         bool
 503         select FSL_LAW
 504         select SYS_FSL_HAS_DDR1
 505         select SYS_FSL_HAS_SEC
 506         select SYS_FSL_SEC_BE
 507         select SYS_FSL_SEC_COMPAT_2
 508
 509 config ARCH_MPC8560
 510         bool
 511         select FSL_LAW
 512         select SYS_FSL_HAS_DDR1
 513
 514 config ARCH_MPC8568
 515         bool
 516         select FSL_LAW
 517         select SYS_FSL_HAS_DDR2
 518         select SYS_FSL_HAS_SEC
 519         select SYS_FSL_SEC_BE
 520         select SYS_FSL_SEC_COMPAT_2
 521
 522 config ARCH_MPC8569
 523         bool
 524         select FSL_LAW
 525         select SYS_FSL_ERRATUM_A004508
 526         select SYS_FSL_ERRATUM_A005125
 527         select SYS_FSL_HAS_DDR3
 528         select SYS_FSL_HAS_SEC
 529         select SYS_FSL_SEC_BE
 530         select SYS_FSL_SEC_COMPAT_2
 531         select FSL_ELBC
 532
 533 config ARCH_MPC8572
 534         bool
 535         select FSL_LAW
 536         select SYS_FSL_ERRATUM_A004508
 537         select SYS_FSL_ERRATUM_A005125
 538         select SYS_FSL_ERRATUM_DDR_115
 539         select SYS_FSL_ERRATUM_DDR111_DDR134
 540         select SYS_FSL_HAS_DDR2
 541         select SYS_FSL_HAS_DDR3
 542         select SYS_FSL_HAS_SEC
 543         select SYS_FSL_SEC_BE
 544         select SYS_FSL_SEC_COMPAT_2
 545         select SYS_PPC_E500_USE_DEBUG_TLB
 546         select FSL_ELBC
 547
 548 config ARCH_P1010
 549         bool
 550         select FSL_LAW
 551         select SYS_FSL_ERRATUM_A004477
 552         select SYS_FSL_ERRATUM_A004508
 553         select SYS_FSL_ERRATUM_A005125
 554         select SYS_FSL_ERRATUM_A006261
 555         select SYS_FSL_ERRATUM_A007075
 556         select SYS_FSL_ERRATUM_ESDHC111
 557         select SYS_FSL_ERRATUM_I2C_A004447
 558         select SYS_FSL_ERRATUM_IFC_A002769
 559         select SYS_FSL_ERRATUM_P1010_A003549
 560         select SYS_FSL_ERRATUM_SEC_A003571
 561         select SYS_FSL_ERRATUM_IFC_A003399
 562         select SYS_FSL_HAS_DDR3
 563         select SYS_FSL_HAS_SEC
 564         select SYS_FSL_SEC_BE
 565         select SYS_FSL_SEC_COMPAT_4
 566         select SYS_PPC_E500_USE_DEBUG_TLB
 567         select FSL_IFC
 568
 569 config ARCH_P1011
 570         bool
 571         select FSL_LAW
 572         select SYS_FSL_ERRATUM_A004508
 573         select SYS_FSL_ERRATUM_A005125
 574         select SYS_FSL_ERRATUM_ELBC_A001
 575         select SYS_FSL_ERRATUM_ESDHC111
 576         select SYS_FSL_HAS_DDR3
 577         select SYS_FSL_HAS_SEC
 578         select SYS_FSL_SEC_BE
 579         select SYS_FSL_SEC_COMPAT_2
 580         select SYS_PPC_E500_USE_DEBUG_TLB
 581         select FSL_ELBC
 582
 583 config ARCH_P1020
 584         bool
 585         select FSL_LAW
 586         select SYS_FSL_ERRATUM_A004508
 587         select SYS_FSL_ERRATUM_A005125
 588         select SYS_FSL_ERRATUM_ELBC_A001
 589         select SYS_FSL_ERRATUM_ESDHC111
 590         select SYS_FSL_HAS_DDR3
 591         select SYS_FSL_HAS_SEC
 592         select SYS_FSL_SEC_BE
 593         select SYS_FSL_SEC_COMPAT_2
 594         select SYS_PPC_E500_USE_DEBUG_TLB
 595         select FSL_ELBC
 596
 597 config ARCH_P1021
 598         bool
 599         select FSL_LAW
 600         select SYS_FSL_ERRATUM_A004508
 601         select SYS_FSL_ERRATUM_A005125
 602         select SYS_FSL_ERRATUM_ELBC_A001
 603         select SYS_FSL_ERRATUM_ESDHC111
 604         select SYS_FSL_HAS_DDR3
 605         select SYS_FSL_HAS_SEC
 606         select SYS_FSL_SEC_BE
 607         select SYS_FSL_SEC_COMPAT_2
 608         select SYS_PPC_E500_USE_DEBUG_TLB
 609         select FSL_ELBC
 610
 611 config ARCH_P1022
 612         bool
 613         select FSL_LAW
 614         select SYS_FSL_ERRATUM_A004477
 615         select SYS_FSL_ERRATUM_A004508
 616         select SYS_FSL_ERRATUM_A005125
 617         select SYS_FSL_ERRATUM_ELBC_A001
 618         select SYS_FSL_ERRATUM_ESDHC111
 619         select SYS_FSL_ERRATUM_SATA_A001
 620         select SYS_FSL_HAS_DDR3
 621         select SYS_FSL_HAS_SEC
 622         select SYS_FSL_SEC_BE
 623         select SYS_FSL_SEC_COMPAT_2
 624         select SYS_PPC_E500_USE_DEBUG_TLB
 625         select FSL_ELBC
 626
 627 config ARCH_P1023
 628         bool
 629         select FSL_LAW
 630         select SYS_FSL_ERRATUM_A004508
 631         select SYS_FSL_ERRATUM_A005125
 632         select SYS_FSL_ERRATUM_I2C_A004447
 633         select SYS_FSL_HAS_DDR3
 634         select SYS_FSL_HAS_SEC
 635         select SYS_FSL_SEC_BE
 636         select SYS_FSL_SEC_COMPAT_4
 637         select FSL_ELBC
 638
 639 config ARCH_P1024
 640         bool
 641         select FSL_LAW
 642         select SYS_FSL_ERRATUM_A004508
 643         select SYS_FSL_ERRATUM_A005125
 644         select SYS_FSL_ERRATUM_ELBC_A001
 645         select SYS_FSL_ERRATUM_ESDHC111
 646         select SYS_FSL_HAS_DDR3
 647         select SYS_FSL_HAS_SEC
 648         select SYS_FSL_SEC_BE
 649         select SYS_FSL_SEC_COMPAT_2
 650         select SYS_PPC_E500_USE_DEBUG_TLB
 651         select FSL_ELBC
 652
 653 config ARCH_P1025
 654         bool
 655         select FSL_LAW
 656         select SYS_FSL_ERRATUM_A004508
 657         select SYS_FSL_ERRATUM_A005125
 658         select SYS_FSL_ERRATUM_ELBC_A001
 659         select SYS_FSL_ERRATUM_ESDHC111
 660         select SYS_FSL_HAS_DDR3
 661         select SYS_FSL_HAS_SEC
 662         select SYS_FSL_SEC_BE
 663         select SYS_FSL_SEC_COMPAT_2
 664         select SYS_PPC_E500_USE_DEBUG_TLB
 665         select FSL_ELBC
 666
 667 config ARCH_P2020
 668         bool
 669         select FSL_LAW
 670         select SYS_FSL_ERRATUM_A004477
 671         select SYS_FSL_ERRATUM_A004508
 672         select SYS_FSL_ERRATUM_A005125
 673         select SYS_FSL_ERRATUM_ESDHC111
 674         select SYS_FSL_ERRATUM_ESDHC_A001
 675         select SYS_FSL_HAS_DDR3
 676         select SYS_FSL_HAS_SEC
 677         select SYS_FSL_SEC_BE
 678         select SYS_FSL_SEC_COMPAT_2
 679         select SYS_PPC_E500_USE_DEBUG_TLB
 680         select FSL_ELBC
 681
 682 config ARCH_P2041
 683         bool
 684         select E500MC
 685         select FSL_LAW
 686         select SYS_FSL_ERRATUM_A004510
 687         select SYS_FSL_ERRATUM_A004849
 688         select SYS_FSL_ERRATUM_A006261
 689         select SYS_FSL_ERRATUM_CPU_A003999
 690         select SYS_FSL_ERRATUM_DDR_A003
 691         select SYS_FSL_ERRATUM_DDR_A003474
 692         select SYS_FSL_ERRATUM_ESDHC111
 693         select SYS_FSL_ERRATUM_I2C_A004447
 694         select SYS_FSL_ERRATUM_NMG_CPU_A011
 695         select SYS_FSL_ERRATUM_SRIO_A004034
 696         select SYS_FSL_ERRATUM_USB14
 697         select SYS_FSL_HAS_DDR3
 698         select SYS_FSL_HAS_SEC
 699         select SYS_FSL_QORIQ_CHASSIS1
 700         select SYS_FSL_SEC_BE
 701         select SYS_FSL_SEC_COMPAT_4
 702         select FSL_ELBC
 703
 704 config ARCH_P3041
 705         bool
 706         select E500MC
 707         select FSL_LAW
 708         select SYS_FSL_DDR_VER_44
 709         select SYS_FSL_ERRATUM_A004510
 710         select SYS_FSL_ERRATUM_A004849
 711         select SYS_FSL_ERRATUM_A005812
 712         select SYS_FSL_ERRATUM_A006261
 713         select SYS_FSL_ERRATUM_CPU_A003999
 714         select SYS_FSL_ERRATUM_DDR_A003
 715         select SYS_FSL_ERRATUM_DDR_A003474
 716         select SYS_FSL_ERRATUM_ESDHC111
 717         select SYS_FSL_ERRATUM_I2C_A004447
 718         select SYS_FSL_ERRATUM_NMG_CPU_A011
 719         select SYS_FSL_ERRATUM_SRIO_A004034
 720         select SYS_FSL_ERRATUM_USB14
 721         select SYS_FSL_HAS_DDR3
 722         select SYS_FSL_HAS_SEC
 723         select SYS_FSL_QORIQ_CHASSIS1
 724         select SYS_FSL_SEC_BE
 725         select SYS_FSL_SEC_COMPAT_4
 726         select FSL_ELBC
 727
 728 config ARCH_P4080
 729         bool
 730         select E500MC
 731         select FSL_LAW
 732         select SYS_FSL_DDR_VER_44
 733         select SYS_FSL_ERRATUM_A004510
 734         select SYS_FSL_ERRATUM_A004580
 735         select SYS_FSL_ERRATUM_A004849
 736         select SYS_FSL_ERRATUM_A005812
 737         select SYS_FSL_ERRATUM_A007075
 738         select SYS_FSL_ERRATUM_CPC_A002
 739         select SYS_FSL_ERRATUM_CPC_A003
 740         select SYS_FSL_ERRATUM_CPU_A003999
 741         select SYS_FSL_ERRATUM_DDR_A003
 742         select SYS_FSL_ERRATUM_DDR_A003474
 743         select SYS_FSL_ERRATUM_ELBC_A001
 744         select SYS_FSL_ERRATUM_ESDHC111
 745         select SYS_FSL_ERRATUM_ESDHC13
 746         select SYS_FSL_ERRATUM_ESDHC135
 747         select SYS_FSL_ERRATUM_I2C_A004447
 748         select SYS_FSL_ERRATUM_NMG_CPU_A011
 749         select SYS_FSL_ERRATUM_SRIO_A004034
 750         select SYS_P4080_ERRATUM_CPU22
 751         select SYS_P4080_ERRATUM_PCIE_A003
 752         select SYS_P4080_ERRATUM_SERDES8
 753         select SYS_P4080_ERRATUM_SERDES9
 754         select SYS_P4080_ERRATUM_SERDES_A001
 755         select SYS_P4080_ERRATUM_SERDES_A005
 756         select SYS_FSL_HAS_DDR3
 757         select SYS_FSL_HAS_SEC
 758         select SYS_FSL_QORIQ_CHASSIS1
 759         select SYS_FSL_SEC_BE
 760         select SYS_FSL_SEC_COMPAT_4
 761         select FSL_ELBC
 762
 763 config ARCH_P5020
 764         bool
 765         select E500MC
 766         select FSL_LAW
 767         select SYS_FSL_DDR_VER_44
 768         select SYS_FSL_ERRATUM_A004510
 769         select SYS_FSL_ERRATUM_A006261
 770         select SYS_FSL_ERRATUM_DDR_A003
 771         select SYS_FSL_ERRATUM_DDR_A003474
 772         select SYS_FSL_ERRATUM_ESDHC111
 773         select SYS_FSL_ERRATUM_I2C_A004447
 774         select SYS_FSL_ERRATUM_SRIO_A004034
 775         select SYS_FSL_ERRATUM_USB14
 776         select SYS_FSL_HAS_DDR3
 777         select SYS_FSL_HAS_SEC
 778         select SYS_FSL_QORIQ_CHASSIS1
 779         select SYS_FSL_SEC_BE
 780         select SYS_FSL_SEC_COMPAT_4
 781         select SYS_PPC64
 782         select FSL_ELBC
 783
 784 config ARCH_P5040
 785         bool
 786         select E500MC
 787         select FSL_LAW
 788         select SYS_FSL_DDR_VER_44
 789         select SYS_FSL_ERRATUM_A004510
 790         select SYS_FSL_ERRATUM_A004699
 791         select SYS_FSL_ERRATUM_A005812
 792         select SYS_FSL_ERRATUM_A006261
 793         select SYS_FSL_ERRATUM_DDR_A003
 794         select SYS_FSL_ERRATUM_DDR_A003474
 795         select SYS_FSL_ERRATUM_ESDHC111
 796         select SYS_FSL_ERRATUM_USB14
 797         select SYS_FSL_HAS_DDR3
 798         select SYS_FSL_HAS_SEC
 799         select SYS_FSL_QORIQ_CHASSIS1
 800         select SYS_FSL_SEC_BE
 801         select SYS_FSL_SEC_COMPAT_4
 802         select SYS_PPC64
 803         select FSL_ELBC
 804
 805 config ARCH_QEMU_E500
 806         bool
 807
 808 config ARCH_T1023
 809         bool
 810         select E500MC
 811         select FSL_LAW
 812         select SYS_FSL_DDR_VER_50
 813         select SYS_FSL_ERRATUM_A008378
 814         select SYS_FSL_ERRATUM_A009663
 815         select SYS_FSL_ERRATUM_A009942
 816         select SYS_FSL_ERRATUM_ESDHC111
 817         select SYS_FSL_HAS_DDR3
 818         select SYS_FSL_HAS_DDR4
 819         select SYS_FSL_HAS_SEC
 820         select SYS_FSL_QORIQ_CHASSIS2
 821         select SYS_FSL_SEC_BE
 822         select SYS_FSL_SEC_COMPAT_5
 823         select FSL_IFC
 824
 825 config ARCH_T1024
 826         bool
 827         select E500MC
 828         select FSL_LAW
 829         select SYS_FSL_DDR_VER_50
 830         select SYS_FSL_ERRATUM_A008378
 831         select SYS_FSL_ERRATUM_A009663
 832         select SYS_FSL_ERRATUM_A009942
 833         select SYS_FSL_ERRATUM_ESDHC111
 834         select SYS_FSL_HAS_DDR3
 835         select SYS_FSL_HAS_DDR4
 836         select SYS_FSL_HAS_SEC
 837         select SYS_FSL_QORIQ_CHASSIS2
 838         select SYS_FSL_SEC_BE
 839         select SYS_FSL_SEC_COMPAT_5
 840         select FSL_IFC
 841
 842 config ARCH_T1040
 843         bool
 844         select E500MC
 845         select FSL_LAW
 846         select SYS_FSL_DDR_VER_50
 847         select SYS_FSL_ERRATUM_A008044
 848         select SYS_FSL_ERRATUM_A008378
 849         select SYS_FSL_ERRATUM_A009663
 850         select SYS_FSL_ERRATUM_A009942
 851         select SYS_FSL_ERRATUM_ESDHC111
 852         select SYS_FSL_HAS_DDR3
 853         select SYS_FSL_HAS_DDR4
 854         select SYS_FSL_HAS_SEC
 855         select SYS_FSL_QORIQ_CHASSIS2
 856         select SYS_FSL_SEC_BE
 857         select SYS_FSL_SEC_COMPAT_5
 858         select FSL_IFC
 859
 860 config ARCH_T1042
 861         bool
 862         select E500MC
 863         select FSL_LAW
 864         select SYS_FSL_DDR_VER_50
 865         select SYS_FSL_ERRATUM_A008044
 866         select SYS_FSL_ERRATUM_A008378
 867         select SYS_FSL_ERRATUM_A009663
 868         select SYS_FSL_ERRATUM_A009942
 869         select SYS_FSL_ERRATUM_ESDHC111
 870         select SYS_FSL_HAS_DDR3
 871         select SYS_FSL_HAS_DDR4
 872         select SYS_FSL_HAS_SEC
 873         select SYS_FSL_QORIQ_CHASSIS2
 874         select SYS_FSL_SEC_BE
 875         select SYS_FSL_SEC_COMPAT_5
 876         select FSL_IFC
 877
 878 config ARCH_T2080
 879         bool
 880         select E500MC
 881         select E6500
 882         select FSL_LAW
 883         select SYS_FSL_DDR_VER_47
 884         select SYS_FSL_ERRATUM_A006379
 885         select SYS_FSL_ERRATUM_A006593
 886         select SYS_FSL_ERRATUM_A007186
 887         select SYS_FSL_ERRATUM_A007212
 888         select SYS_FSL_ERRATUM_A007815
 889         select SYS_FSL_ERRATUM_A007907
 890         select SYS_FSL_ERRATUM_A009942
 891         select SYS_FSL_ERRATUM_ESDHC111
 892         select SYS_FSL_HAS_DDR3
 893         select SYS_FSL_HAS_SEC
 894         select SYS_FSL_QORIQ_CHASSIS2
 895         select SYS_FSL_SEC_BE
 896         select SYS_FSL_SEC_COMPAT_4
 897         select SYS_PPC64
 898         select FSL_IFC
 899
 900 config ARCH_T2081
 901         bool
 902         select E500MC
 903         select E6500
 904         select FSL_LAW
 905         select SYS_FSL_DDR_VER_47
 906         select SYS_FSL_ERRATUM_A006379
 907         select SYS_FSL_ERRATUM_A006593
 908         select SYS_FSL_ERRATUM_A007186
 909         select SYS_FSL_ERRATUM_A007212
 910         select SYS_FSL_ERRATUM_A009942
 911         select SYS_FSL_ERRATUM_ESDHC111
 912         select SYS_FSL_HAS_DDR3
 913         select SYS_FSL_HAS_SEC
 914         select SYS_FSL_QORIQ_CHASSIS2
 915         select SYS_FSL_SEC_BE
 916         select SYS_FSL_SEC_COMPAT_4
 917         select SYS_PPC64
 918         select FSL_IFC
 919
 920 config ARCH_T4160
 921         bool
 922         select E500MC
 923         select E6500
 924         select FSL_LAW
 925         select SYS_FSL_DDR_VER_47
 926         select SYS_FSL_ERRATUM_A004468
 927         select SYS_FSL_ERRATUM_A005871
 928         select SYS_FSL_ERRATUM_A006379
 929         select SYS_FSL_ERRATUM_A006593
 930         select SYS_FSL_ERRATUM_A007186
 931         select SYS_FSL_ERRATUM_A007798
 932         select SYS_FSL_ERRATUM_A009942
 933         select SYS_FSL_HAS_DDR3
 934         select SYS_FSL_HAS_SEC
 935         select SYS_FSL_QORIQ_CHASSIS2
 936         select SYS_FSL_SEC_BE
 937         select SYS_FSL_SEC_COMPAT_4
 938         select SYS_PPC64
 939         select FSL_IFC
 940
 941 config ARCH_T4240
 942         bool
 943         select E500MC
 944         select E6500
 945         select FSL_LAW
 946         select SYS_FSL_DDR_VER_47
 947         select SYS_FSL_ERRATUM_A004468
 948         select SYS_FSL_ERRATUM_A005871
 949         select SYS_FSL_ERRATUM_A006261
 950         select SYS_FSL_ERRATUM_A006379
 951         select SYS_FSL_ERRATUM_A006593
 952         select SYS_FSL_ERRATUM_A007186
 953         select SYS_FSL_ERRATUM_A007798
 954         select SYS_FSL_ERRATUM_A007815
 955         select SYS_FSL_ERRATUM_A007907
 956         select SYS_FSL_ERRATUM_A009942
 957         select SYS_FSL_HAS_DDR3
 958         select SYS_FSL_HAS_SEC
 959         select SYS_FSL_QORIQ_CHASSIS2
 960         select SYS_FSL_SEC_BE
 961         select SYS_FSL_SEC_COMPAT_4
 962         select SYS_PPC64
 963         select FSL_IFC
 964
 965 config BOOKE
 966         bool
 967         default y
 968
 969 config E500
 970         bool
 971         default y
 972         help
 973                 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
 974
 975 config E500MC
 976         bool
 977         help
 978                 Enble PowerPC E500MC core
 979
 980 config E6500
 981         bool
 982         help
 983                 Enable PowerPC E6500 core
 984
 985 config FSL_LAW
 986         bool
 987         help
 988                 Use Freescale common code for Local Access Window
 989
 990 config SECURE_BOOT
 991         bool    "Secure Boot"
 992         help
 993                 Enable Freescale Secure Boot feature. Normally selected
 994                 by defconfig. If unsure, do not change.
 995
 996 config MAX_CPUS
 997         int "Maximum number of CPUs permitted for MPC85xx"
 998         default 12 if ARCH_T4240
 999         default 8 if ARCH_P4080 || \
1000                      ARCH_T4160
1001         default 4 if ARCH_B4860 || \
1002                      ARCH_P2041 || \
1003                      ARCH_P3041 || \
1004                      ARCH_P5040 || \
1005                      ARCH_T1040 || \
1006                      ARCH_T1042 || \
1007                      ARCH_T2080 || \
1008                      ARCH_T2081
1009         default 2 if ARCH_B4420 || \
1010                      ARCH_BSC9132 || \
1011                      ARCH_MPC8572 || \
1012                      ARCH_P1020 || \
1013                      ARCH_P1021 || \
1014                      ARCH_P1022 || \
1015                      ARCH_P1023 || \
1016                      ARCH_P1024 || \
1017                      ARCH_P1025 || \
1018                      ARCH_P2020 || \
1019                      ARCH_P5020 || \
1020                      ARCH_T1023 || \
1021                      ARCH_T1024
1022         default 1
1023         help
1024           Set this number to the maximum number of possible CPUs in the SoC.
1025           SoCs may have multiple clusters with each cluster may have multiple
1026           ports. If some ports are reserved but higher ports are used for
1027           cores, count the reserved ports. This will allocate enough memory
1028           in spin table to properly handle all cores.
1029
1030 config SYS_CCSRBAR_DEFAULT
1031         hex "Default CCSRBAR address"
1032         default 0xff700000 if   ARCH_BSC9131    || \
1033                                 ARCH_BSC9132    || \
1034                                 ARCH_C29X       || \
1035                                 ARCH_MPC8536    || \
1036                                 ARCH_MPC8540    || \
1037                                 ARCH_MPC8541    || \
1038                                 ARCH_MPC8544    || \
1039                                 ARCH_MPC8548    || \
1040                                 ARCH_MPC8555    || \
1041                                 ARCH_MPC8560    || \
1042                                 ARCH_MPC8568    || \
1043                                 ARCH_MPC8569    || \
1044                                 ARCH_MPC8572    || \
1045                                 ARCH_P1010      || \
1046                                 ARCH_P1011      || \
1047                                 ARCH_P1020      || \
1048                                 ARCH_P1021      || \
1049                                 ARCH_P1022      || \
1050                                 ARCH_P1024      || \
1051                                 ARCH_P1025      || \
1052                                 ARCH_P2020
1053         default 0xff600000 if   ARCH_P1023
1054         default 0xfe000000 if   ARCH_B4420      || \
1055                                 ARCH_B4860      || \
1056                                 ARCH_P2041      || \
1057                                 ARCH_P3041      || \
1058                                 ARCH_P4080      || \
1059                                 ARCH_P5020      || \
1060                                 ARCH_P5040      || \
1061                                 ARCH_T1023      || \
1062                                 ARCH_T1024      || \
1063                                 ARCH_T1040      || \
1064                                 ARCH_T1042      || \
1065                                 ARCH_T2080      || \
1066                                 ARCH_T2081      || \
1067                                 ARCH_T4160      || \
1068                                 ARCH_T4240
1069         default 0xe0000000 if ARCH_QEMU_E500
1070         help
1071                 Default value of CCSRBAR comes from power-on-reset. It
1072                 is fixed on each SoC. Some SoCs can have different value
1073                 if changed by pre-boot regime. The value here must match
1074                 the current value in SoC. If not sure, do not change.
1075
1076 config SYS_FSL_ERRATUM_A004468
1077         bool
1078
1079 config SYS_FSL_ERRATUM_A004477
1080         bool
1081
1082 config SYS_FSL_ERRATUM_A004508
1083         bool
1084
1085 config SYS_FSL_ERRATUM_A004580
1086         bool
1087
1088 config SYS_FSL_ERRATUM_A004699
1089         bool
1090
1091 config SYS_FSL_ERRATUM_A004849
1092         bool
1093
1094 config SYS_FSL_ERRATUM_A004510
1095         bool
1096
1097 config SYS_FSL_ERRATUM_A004510_SVR_REV
1098         hex
1099         depends on SYS_FSL_ERRATUM_A004510
1100         default 0x20 if ARCH_P4080
1101         default 0x10
1102
1103 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1104         hex
1105         depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1106         default 0x11
1107
1108 config SYS_FSL_ERRATUM_A005125
1109         bool
1110
1111 config SYS_FSL_ERRATUM_A005434
1112         bool
1113
1114 config SYS_FSL_ERRATUM_A005812
1115         bool
1116
1117 config SYS_FSL_ERRATUM_A005871
1118         bool
1119
1120 config SYS_FSL_ERRATUM_A006261
1121         bool
1122
1123 config SYS_FSL_ERRATUM_A006379
1124         bool
1125
1126 config SYS_FSL_ERRATUM_A006384
1127         bool
1128
1129 config SYS_FSL_ERRATUM_A006475
1130         bool
1131
1132 config SYS_FSL_ERRATUM_A006593
1133         bool
1134
1135 config SYS_FSL_ERRATUM_A007075
1136         bool
1137
1138 config SYS_FSL_ERRATUM_A007186
1139         bool
1140
1141 config SYS_FSL_ERRATUM_A007212
1142         bool
1143
1144 config SYS_FSL_ERRATUM_A007815
1145         bool
1146
1147 config SYS_FSL_ERRATUM_A007798
1148         bool
1149
1150 config SYS_FSL_ERRATUM_A007907
1151         bool
1152
1153 config SYS_FSL_ERRATUM_A008044
1154         bool
1155
1156 config SYS_FSL_ERRATUM_CPC_A002
1157         bool
1158
1159 config SYS_FSL_ERRATUM_CPC_A003
1160         bool
1161
1162 config SYS_FSL_ERRATUM_CPU_A003999
1163         bool
1164
1165 config SYS_FSL_ERRATUM_ELBC_A001
1166         bool
1167
1168 config SYS_FSL_ERRATUM_I2C_A004447
1169         bool
1170
1171 config SYS_FSL_A004447_SVR_REV
1172         hex
1173         depends on SYS_FSL_ERRATUM_I2C_A004447
1174         default 0x00 if ARCH_MPC8548
1175         default 0x10 if ARCH_P1010
1176         default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1177         default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1178
1179 config SYS_FSL_ERRATUM_IFC_A002769
1180         bool
1181
1182 config SYS_FSL_ERRATUM_IFC_A003399
1183         bool
1184
1185 config SYS_FSL_ERRATUM_NMG_CPU_A011
1186         bool
1187
1188 config SYS_FSL_ERRATUM_NMG_ETSEC129
1189         bool
1190
1191 config SYS_FSL_ERRATUM_NMG_LBC103
1192         bool
1193
1194 config SYS_FSL_ERRATUM_P1010_A003549
1195         bool
1196
1197 config SYS_FSL_ERRATUM_SATA_A001
1198         bool
1199
1200 config SYS_FSL_ERRATUM_SEC_A003571
1201         bool
1202
1203 config SYS_FSL_ERRATUM_SRIO_A004034
1204         bool
1205
1206 config SYS_FSL_ERRATUM_USB14
1207         bool
1208
1209 config SYS_P4080_ERRATUM_CPU22
1210         bool
1211
1212 config SYS_P4080_ERRATUM_PCIE_A003
1213         bool
1214
1215 config SYS_P4080_ERRATUM_SERDES8
1216         bool
1217
1218 config SYS_P4080_ERRATUM_SERDES9
1219         bool
1220
1221 config SYS_P4080_ERRATUM_SERDES_A001
1222         bool
1223
1224 config SYS_P4080_ERRATUM_SERDES_A005
1225         bool
1226
1227 config SYS_FSL_QORIQ_CHASSIS1
1228         bool
1229
1230 config SYS_FSL_QORIQ_CHASSIS2
1231         bool
1232
1233 config SYS_FSL_NUM_LAWS
1234         int "Number of local access windows"
1235         depends on FSL_LAW
1236         default 32 if   ARCH_B4420      || \
1237                         ARCH_B4860      || \
1238                         ARCH_P2041      || \
1239                         ARCH_P3041      || \
1240                         ARCH_P4080      || \
1241                         ARCH_P5020      || \
1242                         ARCH_P5040      || \
1243                         ARCH_T2080      || \
1244                         ARCH_T2081      || \
1245                         ARCH_T4160      || \
1246                         ARCH_T4240
1247         default 16 if   ARCH_T1023      || \
1248                         ARCH_T1024      || \
1249                         ARCH_T1040      || \
1250                         ARCH_T1042
1251         default 12 if   ARCH_BSC9131    || \
1252                         ARCH_BSC9132    || \
1253                         ARCH_C29X       || \
1254                         ARCH_MPC8536    || \
1255                         ARCH_MPC8572    || \
1256                         ARCH_P1010      || \
1257                         ARCH_P1011      || \
1258                         ARCH_P1020      || \
1259                         ARCH_P1021      || \
1260                         ARCH_P1022      || \
1261                         ARCH_P1023      || \
1262                         ARCH_P1024      || \
1263                         ARCH_P1025      || \
1264                         ARCH_P2020
1265         default 10 if   ARCH_MPC8544    || \
1266                         ARCH_MPC8548    || \
1267                         ARCH_MPC8568    || \
1268                         ARCH_MPC8569
1269         default 8 if    ARCH_MPC8540    || \
1270                         ARCH_MPC8541    || \
1271                         ARCH_MPC8555    || \
1272                         ARCH_MPC8560
1273         help
1274                 Number of local access windows. This is fixed per SoC.
1275                 If not sure, do not change.
1276
1277 config SYS_FSL_THREADS_PER_CORE
1278         int
1279         default 2 if E6500
1280         default 1
1281
1282 config SYS_NUM_TLBCAMS
1283         int "Number of TLB CAM entries"
1284         default 64 if E500MC
1285         default 16
1286         help
1287                 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1288                 16 for other E500 SoCs.
1289
1290 config SYS_PPC64
1291         bool
1292
1293 config SYS_PPC_E500_USE_DEBUG_TLB
1294         bool
1295
1296 config FSL_IFC
1297         bool
1298
1299 config FSL_ELBC
1300         bool
1301
1302 config SYS_PPC_E500_DEBUG_TLB
1303         int "Temporary TLB entry for external debugger"
1304         depends on SYS_PPC_E500_USE_DEBUG_TLB
1305         default 0 if    ARCH_MPC8544 || ARCH_MPC8548
1306         default 1 if    ARCH_MPC8536
1307         default 2 if    ARCH_MPC8572    || \
1308                         ARCH_P1011      || \
1309                         ARCH_P1020      || \
1310                         ARCH_P1021      || \
1311                         ARCH_P1022      || \
1312                         ARCH_P1024      || \
1313                         ARCH_P1025      || \
1314                         ARCH_P2020
1315         default 3 if    ARCH_P1010      || \
1316                         ARCH_BSC9132    || \
1317                         ARCH_C29X
1318         help
1319                 Select a temporary TLB entry to be used during boot to work
1320                 around limitations in e500v1 and e500v2 external debugger
1321                 support. This reduces the portions of the boot code where
1322                 breakpoints and single stepping do not work. The value of this
1323                 symbol should be set to the TLB1 entry to be used for this
1324                 purpose. If unsure, do not change.
1325
1326 config SYS_FSL_IFC_CLK_DIV
1327         int "Divider of platform clock"
1328         depends on FSL_IFC
1329         default 2 if    ARCH_B4420      || \
1330                         ARCH_B4860      || \
1331                         ARCH_T1024      || \
1332                         ARCH_T1023      || \
1333                         ARCH_T1040      || \
1334                         ARCH_T1042      || \
1335                         ARCH_T4160      || \
1336                         ARCH_T4240
1337         default 1
1338         help
1339                 Defines divider of platform clock(clock input to
1340                 IFC controller).
1341
1342 config SYS_FSL_LBC_CLK_DIV
1343         int "Divider of platform clock"
1344         depends on FSL_ELBC || ARCH_MPC8540 || \
1345                 ARCH_MPC8548 || ARCH_MPC8541 || \
1346                 ARCH_MPC8555 || ARCH_MPC8560 || \
1347                 ARCH_MPC8568
1348
1349         default 2 if    ARCH_P2041      || \
1350                         ARCH_P3041      || \
1351                         ARCH_P4080      || \
1352                         ARCH_P5020      || \
1353                         ARCH_P5040
1354         default 1
1355
1356         help
1357                 Defines divider of platform clock(clock input to
1358                 eLBC controller).
1359
1360 source "board/freescale/b4860qds/Kconfig"
1361 source "board/freescale/bsc9131rdb/Kconfig"
1362 source "board/freescale/bsc9132qds/Kconfig"
1363 source "board/freescale/c29xpcie/Kconfig"
1364 source "board/freescale/corenet_ds/Kconfig"
1365 source "board/freescale/mpc8536ds/Kconfig"
1366 source "board/freescale/mpc8540ads/Kconfig"
1367 source "board/freescale/mpc8541cds/Kconfig"
1368 source "board/freescale/mpc8544ds/Kconfig"
1369 source "board/freescale/mpc8548cds/Kconfig"
1370 source "board/freescale/mpc8555cds/Kconfig"
1371 source "board/freescale/mpc8560ads/Kconfig"
1372 source "board/freescale/mpc8568mds/Kconfig"
1373 source "board/freescale/mpc8569mds/Kconfig"
1374 source "board/freescale/mpc8572ds/Kconfig"
1375 source "board/freescale/p1010rdb/Kconfig"
1376 source "board/freescale/p1022ds/Kconfig"
1377 source "board/freescale/p1023rdb/Kconfig"
1378 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1379 source "board/freescale/p1_twr/Kconfig"
1380 source "board/freescale/p2041rdb/Kconfig"
1381 source "board/freescale/qemu-ppce500/Kconfig"
1382 source "board/freescale/t102xqds/Kconfig"
1383 source "board/freescale/t102xrdb/Kconfig"
1384 source "board/freescale/t1040qds/Kconfig"
1385 source "board/freescale/t104xrdb/Kconfig"
1386 source "board/freescale/t208xqds/Kconfig"
1387 source "board/freescale/t208xrdb/Kconfig"
1388 source "board/freescale/t4qds/Kconfig"
1389 source "board/freescale/t4rdb/Kconfig"
1390 source "board/gdsys/p1022/Kconfig"
1391 source "board/keymile/kmp204x/Kconfig"
1392 source "board/sbc8548/Kconfig"
1393 source "board/socrates/Kconfig"
1394 source "board/varisys/cyrus/Kconfig"
1395 source "board/xes/xpedite520x/Kconfig"
1396 source "board/xes/xpedite537x/Kconfig"
1397 source "board/xes/xpedite550x/Kconfig"
1398 source "board/Arcturus/ucp1020/Kconfig"
1399
1400 endmenu