arch/powerpc/cpu/mpc85xx/b4860_serdes.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/fsl_serdes.h>
   9 #include <asm/processor.h>
  10 #include <asm/io.h>
  11 #include "fsl_corenet2_serdes.h"
  12
  13 struct serdes_config {
  14         u8 protocol;
  15         u8 lanes[SRDS_MAX_LANES];
  16 };
  17
  18 #ifdef CONFIG_PPC_B4860
  19 static struct serdes_config serdes1_cfg_tbl[] = {
  20         /* SerDes 1 */
  21         {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
  22                 CPRI4, CPRI3, CPRI2, CPRI1}},
  23         {0x0E, {CPRI8, CPRI7,   CPRI6, CPRI5,
  24                 CPRI4, CPRI3, CPRI2, CPRI1}},
  25         {0x12, {CPRI8, CPRI7,   CPRI6, CPRI5,
  26                 CPRI4, CPRI3, CPRI2, CPRI1}},
  27         {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  28                 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
  29         {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  30                 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
  31         {0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  32                 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
  33         {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  34                 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
  35         {0x30, {AURORA, AURORA,
  36                 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  37                 CPRI4, CPRI3, CPRI2, CPRI1}},
  38         {0x32, {AURORA, AURORA,
  39                 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  40                 CPRI4, CPRI3, CPRI2, CPRI1}},
  41         {0x33, {AURORA, AURORA,
  42                 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  43                 CPRI4, CPRI3, CPRI2, CPRI1}},
  44         {0x34, {AURORA, AURORA,
  45                 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  46                 CPRI4, CPRI3, CPRI2, CPRI1}},
  47         {0x3E, {CPRI8, CPRI7,   CPRI6, CPRI5,
  48                 CPRI4, CPRI3, CPRI2, CPRI1}},
  49         {}
  50 };
  51 static struct serdes_config serdes2_cfg_tbl[] = {
  52         /* SerDes 2 */
  53         {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  54                 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  55                 AURORA, AURORA, SRIO1, SRIO1}},
  56         {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  57                 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  58                 AURORA, AURORA, SRIO1, SRIO1}},
  59         {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  60                 SRIO2, SRIO2,
  61                 AURORA, AURORA, SRIO1, SRIO1}},
  62         {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  63                 SRIO2, SRIO2,
  64                 AURORA, AURORA,
  65                 SRIO1, SRIO1}},
  66         {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  67                 SGMII_FM1_DTSEC3, AURORA,
  68                 SRIO1, SRIO1, SRIO1, SRIO1}},
  69         {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  70                 SGMII_FM1_DTSEC3, AURORA,
  71                 SRIO1, SRIO1, SRIO1, SRIO1}},
  72         {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  73                 SGMII_FM1_DTSEC3, AURORA,
  74                 SRIO1, SRIO1, SRIO1, SRIO1}},
  75         {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  76                 SGMII_FM1_DTSEC3, AURORA,
  77                 SRIO1, SRIO1, SRIO1, SRIO1}},
  78         {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
  79                 SRIO1, SRIO1, SRIO1, SRIO1}},
  80         {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  81                 SRIO2, SRIO2, AURORA, AURORA,
  82                 XFI_FM1_MAC9, XFI_FM1_MAC10}},
  83         {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  84                 SRIO2, SRIO2, AURORA, AURORA,
  85                 XFI_FM1_MAC9, XFI_FM1_MAC10}},
  86         {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  87                 SRIO2, SRIO2,
  88                 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  89                 XFI_FM1_MAC9, XFI_FM1_MAC10}},
  90         {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
  91                 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  92                 XFI_FM1_MAC9, XFI_FM1_MAC10}},
  93         {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  94                 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  95                 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
  96                 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
  97         {0x9E, {PCIE1, PCIE1,   PCIE1, PCIE1,
  98                 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
  99                 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
 100         {0x9A, {PCIE1, PCIE1,
 101                 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 102                 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
 103                 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
 104         {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
 105                 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 106                 XFI_FM1_MAC9, XFI_FM1_MAC10}},
 107         {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
 108                 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
 109                 SRIO1, SRIO1, SRIO1, SRIO1}},
 110         {0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
 111                 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
 112                 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
 113                 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
 114         {}
 115 };
 116 #endif
 117
 118 #ifdef CONFIG_PPC_B4420
 119 static struct serdes_config serdes1_cfg_tbl[] = {
 120         {0x0D, {NONE, NONE, CPRI6, CPRI5,
 121                 CPRI4, CPRI3, NONE, NONE} },
 122         {0x0E, {NONE, NONE, CPRI8, CPRI5,
 123                 CPRI4, CPRI3, NONE, NONE} },
 124         {0x0F, {NONE, NONE, CPRI6, CPRI5,
 125                 CPRI4, CPRI3, NONE, NONE} },
 126         {0x18, {NONE, NONE,
 127                 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 128                 NONE, NONE, NONE, NONE} },
 129         {0x1B, {NONE, NONE,
 130                 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 131                 NONE, NONE, NONE, NONE} },
 132         {0x1E, {NONE, NONE, AURORA, AURORA,
 133                 NONE, NONE, NONE, NONE} },
 134         {0x21, {NONE, NONE, AURORA, AURORA,
 135                 NONE, NONE, NONE, NONE} },
 136         {0x3E, {NONE, NONE, CPRI6, CPRI5,
 137                 CPRI4, CPRI3, NONE, NONE} },
 138         {}
 139 };
 140 static struct serdes_config serdes2_cfg_tbl[] = {
 141         {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 142                 SGMII_FM1_DTSEC3, AURORA,
 143                 NONE, NONE, NONE, NONE} },
 144         {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 145                 SGMII_FM1_DTSEC3, AURORA,
 146                 NONE, NONE, NONE, NONE} },
 147         {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 148                 AURORA, AURORA, NONE, NONE, NONE, NONE} },
 149         {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 150                 AURORA, AURORA, NONE, NONE, NONE, NONE} },
 151         {0x9A, {PCIE1, PCIE1,
 152                 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 153                 NONE, NONE, NONE, NONE} },
 154         {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
 155                 NONE, NONE, NONE, NONE} },
 156         {}
 157 };
 158 #endif
 159
 160 static struct serdes_config *serdes_cfg_tbl[] = {
 161         serdes1_cfg_tbl,
 162         serdes2_cfg_tbl,
 163 };
 164
 165 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
 166 {
 167         struct serdes_config *ptr;
 168
 169         if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
 170                 return 0;
 171
 172         ptr = serdes_cfg_tbl[serdes];
 173         while (ptr->protocol) {
 174                 if (ptr->protocol == cfg)
 175                         return ptr->lanes[lane];
 176                 ptr++;
 177         }
 178
 179         return 0;
 180 }
 181
 182 int is_serdes_prtcl_valid(int serdes, u32 prtcl)
 183 {
 184         int i;
 185         struct serdes_config *ptr;
 186
 187         if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
 188                 return 0;
 189
 190         ptr = serdes_cfg_tbl[serdes];
 191         while (ptr->protocol) {
 192                 if (ptr->protocol == prtcl)
 193                         break;
 194                 ptr++;
 195         }
 196
 197         if (!ptr->protocol)
 198                 return 0;
 199
 200         for (i = 0; i < SRDS_MAX_LANES; i++) {
 201                 if (ptr->lanes[i] != NONE)
 202                         return 1;
 203         }
 204
 205         return 0;
 206 }