arch/powerpc/cpu/mpc85xx/cpu.c

   1 /*
   2  * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
   3  * (C) Copyright 2002, 2003 Motorola Inc.
   4  * Xianghua Xiao (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2000
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <config.h>
  29 #include <common.h>
  30 #include <watchdog.h>
  31 #include <command.h>
  32 #include <fsl_esdhc.h>
  33 #include <asm/cache.h>
  34 #include <asm/io.h>
  35 #include <asm/mmu.h>
  36 #include <asm/fsl_ifc.h>
  37 #include <asm/fsl_law.h>
  38 #include <asm/fsl_lbc.h>
  39 #include <post.h>
  40 #include <asm/processor.h>
  41 #include <asm/fsl_ddr_sdram.h>
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 /*
  46  * Default board reset function
  47  */
  48 static void
  49 __board_reset(void)
  50 {
  51         /* Do nothing */
  52 }
  53 void board_reset(void) __attribute__((weak, alias("__board_reset")));
  54
  55 int checkcpu (void)
  56 {
  57         sys_info_t sysinfo;
  58         uint pvr, svr;
  59         uint ver;
  60         uint major, minor;
  61         struct cpu_type *cpu;
  62         char buf1[32], buf2[32];
  63 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
  64         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  65 #endif /* CONFIG_FSL_CORENET */
  66 #ifdef CONFIG_DDR_CLK_FREQ
  67         u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
  68                 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  69 #else
  70 #ifdef CONFIG_FSL_CORENET
  71         u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
  72                 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
  73 #else
  74         u32 ddr_ratio = 0;
  75 #endif /* CONFIG_FSL_CORENET */
  76 #endif /* CONFIG_DDR_CLK_FREQ */
  77         unsigned int i, core, nr_cores = cpu_numcores();
  78         u32 mask = cpu_mask();
  79
  80         svr = get_svr();
  81         major = SVR_MAJ(svr);
  82         minor = SVR_MIN(svr);
  83
  84         if (cpu_numcores() > 1) {
  85 #ifndef CONFIG_MP
  86                 puts("Unicore software on multiprocessor system!!\n"
  87                      "To enable mutlticore build define CONFIG_MP\n");
  88 #endif
  89                 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  90                 printf("CPU%d:  ", pic->whoami);
  91         } else {
  92                 puts("CPU:   ");
  93         }
  94
  95         cpu = gd->cpu;
  96
  97         puts(cpu->name);
  98         if (IS_E_PROCESSOR(svr))
  99                 puts("E");
 100
 101         printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
 102
 103         pvr = get_pvr();
 104         ver = PVR_VER(pvr);
 105         major = PVR_MAJ(pvr);
 106         minor = PVR_MIN(pvr);
 107
 108         printf("Core:  ");
 109         switch(ver) {
 110         case PVR_VER_E500_V1:
 111         case PVR_VER_E500_V2:
 112                 puts("E500");
 113                 break;
 114         case PVR_VER_E500MC:
 115                 puts("E500MC");
 116                 break;
 117         case PVR_VER_E5500:
 118                 puts("E5500");
 119                 break;
 120         case PVR_VER_E6500:
 121                 puts("E6500");
 122                 break;
 123         default:
 124                 puts("Unknown");
 125                 break;
 126         }
 127
 128         printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
 129
 130         get_sys_info(&sysinfo);
 131
 132         puts("Clock Configuration:");
 133         for_each_cpu(i, core, nr_cores, mask) {
 134                 if (!(i & 3))
 135                         printf ("\n       ");
 136                 printf("CPU%d:%-4s MHz, ", core,
 137                         strmhz(buf1, sysinfo.freqProcessor[core]));
 138         }
 139         printf("\n       CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
 140
 141 #ifdef CONFIG_FSL_CORENET
 142         if (ddr_sync == 1) {
 143                 printf("       DDR:%-4s MHz (%s MT/s data rate) "
 144                         "(Synchronous), ",
 145                         strmhz(buf1, sysinfo.freqDDRBus/2),
 146                         strmhz(buf2, sysinfo.freqDDRBus));
 147         } else {
 148                 printf("       DDR:%-4s MHz (%s MT/s data rate) "
 149                         "(Asynchronous), ",
 150                         strmhz(buf1, sysinfo.freqDDRBus/2),
 151                         strmhz(buf2, sysinfo.freqDDRBus));
 152         }
 153 #else
 154         switch (ddr_ratio) {
 155         case 0x0:
 156                 printf("       DDR:%-4s MHz (%s MT/s data rate), ",
 157                         strmhz(buf1, sysinfo.freqDDRBus/2),
 158                         strmhz(buf2, sysinfo.freqDDRBus));
 159                 break;
 160         case 0x7:
 161                 printf("       DDR:%-4s MHz (%s MT/s data rate) "
 162                         "(Synchronous), ",
 163                         strmhz(buf1, sysinfo.freqDDRBus/2),
 164                         strmhz(buf2, sysinfo.freqDDRBus));
 165                 break;
 166         default:
 167                 printf("       DDR:%-4s MHz (%s MT/s data rate) "
 168                         "(Asynchronous), ",
 169                         strmhz(buf1, sysinfo.freqDDRBus/2),
 170                         strmhz(buf2, sysinfo.freqDDRBus));
 171                 break;
 172         }
 173 #endif
 174
 175 #if defined(CONFIG_FSL_LBC)
 176         if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
 177                 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
 178         } else {
 179                 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
 180                        sysinfo.freqLocalBus);
 181         }
 182 #endif
 183
 184 #ifdef CONFIG_CPM2
 185         printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
 186 #endif
 187
 188 #ifdef CONFIG_QE
 189         printf("       QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
 190 #endif
 191
 192 #ifdef CONFIG_SYS_DPAA_FMAN
 193         for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
 194                 printf("       FMAN%d: %s MHz\n", i + 1,
 195                         strmhz(buf1, sysinfo.freqFMan[i]));
 196         }
 197 #endif
 198
 199 #ifdef CONFIG_SYS_DPAA_PME
 200         printf("       PME:   %s MHz\n", strmhz(buf1, sysinfo.freqPME));
 201 #endif
 202
 203         puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
 204
 205         return 0;
 206 }
 207
 208
 209 /* ------------------------------------------------------------------------- */
 210
 211 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 212 {
 213 /* Everything after the first generation of PQ3 parts has RSTCR */
 214 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
 215     defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
 216         unsigned long val, msr;
 217
 218         /*
 219          * Initiate hard reset in debug control register DBCR0
 220          * Make sure MSR[DE] = 1.  This only resets the core.
 221          */
 222         msr = mfmsr ();
 223         msr |= MSR_DE;
 224         mtmsr (msr);
 225
 226         val = mfspr(DBCR0);
 227         val |= 0x70000000;
 228         mtspr(DBCR0,val);
 229 #else
 230         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 231
 232         /* Attempt board-specific reset */
 233         board_reset();
 234
 235         /* Next try asserting HRESET_REQ */
 236         out_be32(&gur->rstcr, 0x2);
 237         udelay(100);
 238 #endif
 239
 240         return 1;
 241 }
 242
 243
 244 /*
 245  * Get timebase clock frequency
 246  */
 247 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
 248 #define CONFIG_SYS_FSL_TBCLK_DIV 8
 249 #endif
 250 unsigned long get_tbclk (void)
 251 {
 252         unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
 253
 254         return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
 255 }
 256
 257
 258 #if defined(CONFIG_WATCHDOG)
 259 void
 260 watchdog_reset(void)
 261 {
 262         int re_enable = disable_interrupts();
 263         reset_85xx_watchdog();
 264         if (re_enable) enable_interrupts();
 265 }
 266
 267 void
 268 reset_85xx_watchdog(void)
 269 {
 270         /*
 271          * Clear TSR(WIS) bit by writing 1
 272          */
 273         unsigned long val;
 274         val = mfspr(SPRN_TSR);
 275         val |= TSR_WIS;
 276         mtspr(SPRN_TSR, val);
 277 }
 278 #endif  /* CONFIG_WATCHDOG */
 279
 280 /*
 281  * Initializes on-chip MMC controllers.
 282  * to override, implement board_mmc_init()
 283  */
 284 int cpu_mmc_init(bd_t *bis)
 285 {
 286 #ifdef CONFIG_FSL_ESDHC
 287         return fsl_esdhc_mmc_init(bis);
 288 #else
 289         return 0;
 290 #endif
 291 }
 292
 293 /*
 294  * Print out the state of various machine registers.
 295  * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
 296  * parameters for IFC and TLBs
 297  */
 298 void mpc85xx_reginfo(void)
 299 {
 300         print_tlbcam();
 301         print_laws();
 302 #if defined(CONFIG_FSL_LBC)
 303         print_lbc_regs();
 304 #endif
 305 #ifdef CONFIG_FSL_IFC
 306         print_ifc_regs();
 307 #endif
 308
 309 }
 310
 311 /* Common ddr init for non-corenet fsl 85xx platforms */
 312 #ifndef CONFIG_FSL_CORENET
 313 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR)
 314 phys_size_t initdram(int board_type)
 315 {
 316 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
 317         return fsl_ddr_sdram_size();
 318 #else
 319         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 320 #endif
 321 }
 322 #else /* CONFIG_SYS_RAMBOOT */
 323 phys_size_t initdram(int board_type)
 324 {
 325         phys_size_t dram_size = 0;
 326
 327 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
 328         {
 329                 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 330                 unsigned int x = 10;
 331                 unsigned int i;
 332
 333                 /*
 334                  * Work around to stabilize DDR DLL
 335                  */
 336                 out_be32(&gur->ddrdllcr, 0x81000000);
 337                 asm("sync;isync;msync");
 338                 udelay(200);
 339                 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
 340                         setbits_be32(&gur->devdisr, 0x00010000);
 341                         for (i = 0; i < x; i++)
 342                                 ;
 343                         clrbits_be32(&gur->devdisr, 0x00010000);
 344                         x++;
 345                 }
 346         }
 347 #endif
 348
 349 #if     defined(CONFIG_SPD_EEPROM)      || \
 350         defined(CONFIG_DDR_SPD)         || \
 351         defined(CONFIG_SYS_DDR_RAW_TIMING)
 352         dram_size = fsl_ddr_sdram();
 353 #else
 354         dram_size = fixed_sdram();
 355 #endif
 356         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 357         dram_size *= 0x100000;
 358
 359 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 360         /*
 361          * Initialize and enable DDR ECC.
 362          */
 363         ddr_enable_ecc(dram_size);
 364 #endif
 365
 366 #if defined(CONFIG_FSL_LBC)
 367         /* Some boards also have sdram on the lbc */
 368         lbc_sdram_init();
 369 #endif
 370
 371         debug("DDR: ");
 372         return dram_size;
 373 }
 374 #endif /* CONFIG_SYS_RAMBOOT */
 375 #endif
 376
 377 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
 378
 379 /* Board-specific functions defined in each board's ddr.c */
 380 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 381         unsigned int ctrl_num);
 382 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
 383                        phys_addr_t *rpn);
 384 unsigned int
 385         setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
 386
 387 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
 388
 389 static void dump_spd_ddr_reg(void)
 390 {
 391         int i, j, k, m;
 392         u8 *p_8;
 393         u32 *p_32;
 394         ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
 395         generic_spd_eeprom_t
 396                 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
 397
 398         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 399                 fsl_ddr_get_spd(spd[i], i);
 400
 401         puts("SPD data of all dimms (zero vaule is omitted)...\n");
 402         puts("Byte (hex)  ");
 403         k = 1;
 404         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 405                 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
 406                         printf("Dimm%d ", k++);
 407         }
 408         puts("\n");
 409         for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
 410                 m = 0;
 411                 printf("%3d (0x%02x)  ", k, k);
 412                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 413                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 414                                 p_8 = (u8 *) &spd[i][j];
 415                                 if (p_8[k]) {
 416                                         printf("0x%02x  ", p_8[k]);
 417                                         m++;
 418                                 } else
 419                                         puts("      ");
 420                         }
 421                 }
 422                 if (m)
 423                         puts("\n");
 424                 else
 425                         puts("\r");
 426         }
 427
 428         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 429                 switch (i) {
 430                 case 0:
 431                         ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
 432                         break;
 433 #ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
 434                 case 1:
 435                         ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
 436                         break;
 437 #endif
 438                 default:
 439                         printf("%s unexpected controller number = %u\n",
 440                                 __func__, i);
 441                         return;
 442                 }
 443         }
 444         printf("DDR registers dump for all controllers "
 445                 "(zero vaule is omitted)...\n");
 446         puts("Offset (hex)   ");
 447         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 448                 printf("     Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
 449         puts("\n");
 450         for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
 451                 m = 0;
 452                 printf("%6d (0x%04x)", k * 4, k * 4);
 453                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 454                         p_32 = (u32 *) ddr[i];
 455                         if (p_32[k]) {
 456                                 printf("        0x%08x", p_32[k]);
 457                                 m++;
 458                         } else
 459                                 puts("                  ");
 460                 }
 461                 if (m)
 462                         puts("\n");
 463                 else
 464                         puts("\r");
 465         }
 466         puts("\n");
 467 }
 468
 469 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
 470 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
 471 {
 472         u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
 473         unsigned long epn;
 474         u32 tsize, valid, ptr;
 475         int ddr_esel;
 476
 477         clear_ddr_tlbs_phys(p_addr, size>>20);
 478
 479         /* Setup new tlb to cover the physical address */
 480         setup_ddr_tlbs_phys(p_addr, size>>20);
 481
 482         ptr = vstart;
 483         ddr_esel = find_tlb_idx((void *)ptr, 1);
 484         if (ddr_esel != -1) {
 485                 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
 486         } else {
 487                 printf("TLB error in function %s\n", __func__);
 488                 return -1;
 489         }
 490
 491         return 0;
 492 }
 493
 494 /*
 495  * slide the testing window up to test another area
 496  * for 32_bit system, the maximum testable memory is limited to
 497  * CONFIG_MAX_MEM_MAPPED
 498  */
 499 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 500 {
 501         phys_addr_t test_cap, p_addr;
 502         phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
 503
 504 #if !defined(CONFIG_PHYS_64BIT) || \
 505     !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
 506         (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
 507                 test_cap = p_size;
 508 #else
 509                 test_cap = gd->ram_size;
 510 #endif
 511         p_addr = (*vstart) + (*size) + (*phys_offset);
 512         if (p_addr < test_cap - 1) {
 513                 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
 514                 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
 515                         return -1;
 516                 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
 517                 *size = (u32) p_size;
 518                 printf("Testing 0x%08llx - 0x%08llx\n",
 519                         (u64)(*vstart) + (*phys_offset),
 520                         (u64)(*vstart) + (*phys_offset) + (*size) - 1);
 521         } else
 522                 return 1;
 523
 524         return 0;
 525 }
 526
 527 /* initialization for testing area */
 528 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 529 {
 530         phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
 531
 532         *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
 533         *size = (u32) p_size;   /* CONFIG_MAX_MEM_MAPPED < 4G */
 534         *phys_offset = 0;
 535
 536 #if !defined(CONFIG_PHYS_64BIT) || \
 537     !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
 538         (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
 539                 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
 540                         puts("Cannot test more than ");
 541                         print_size(CONFIG_MAX_MEM_MAPPED,
 542                                 " without proper 36BIT support.\n");
 543                 }
 544 #endif
 545         printf("Testing 0x%08llx - 0x%08llx\n",
 546                 (u64)(*vstart) + (*phys_offset),
 547                 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
 548
 549         return 0;
 550 }
 551
 552 /* invalid TLBs for DDR and remap as normal after testing */
 553 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 554 {
 555         unsigned long epn;
 556         u32 tsize, valid, ptr;
 557         phys_addr_t rpn = 0;
 558         int ddr_esel;
 559
 560         /* disable the TLBs for this testing */
 561         ptr = *vstart;
 562
 563         while (ptr < (*vstart) + (*size)) {
 564                 ddr_esel = find_tlb_idx((void *)ptr, 1);
 565                 if (ddr_esel != -1) {
 566                         read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
 567                         disable_tlb(ddr_esel);
 568                 }
 569                 ptr += TSIZE_TO_BYTES(tsize);
 570         }
 571
 572         puts("Remap DDR ");
 573         setup_ddr_tlbs(gd->ram_size>>20);
 574         puts("\n");
 575
 576         return 0;
 577 }
 578
 579 void arch_memory_failure_handle(void)
 580 {
 581         dump_spd_ddr_reg();
 582 }
 583 #endif