arch/powerpc/cpu/mpc85xx/cpu.c

   1 /*
   2  * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
   3  * (C) Copyright 2002, 2003 Motorola Inc.
   4  * Xianghua Xiao (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2000
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <config.h>
  29 #include <common.h>
  30 #include <watchdog.h>
  31 #include <command.h>
  32 #include <fsl_esdhc.h>
  33 #include <asm/cache.h>
  34 #include <asm/io.h>
  35 #include <asm/mmu.h>
  36 #include <asm/fsl_ifc.h>
  37 #include <asm/fsl_law.h>
  38 #include <asm/fsl_lbc.h>
  39 #include <post.h>
  40 #include <asm/processor.h>
  41 #include <asm/fsl_ddr_sdram.h>
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 /*
  46  * Default board reset function
  47  */
  48 static void
  49 __board_reset(void)
  50 {
  51         /* Do nothing */
  52 }
  53 void board_reset(void) __attribute__((weak, alias("__board_reset")));
  54
  55 int checkcpu (void)
  56 {
  57         sys_info_t sysinfo;
  58         uint pvr, svr;
  59         uint ver;
  60         uint major, minor;
  61         struct cpu_type *cpu;
  62         char buf1[32], buf2[32];
  63 #if (defined(CONFIG_DDR_CLK_FREQ) || \
  64         defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
  65         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  66 #endif /* CONFIG_FSL_CORENET */
  67
  68         /*
  69          * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
  70          * mode. Previous platform use ddr ratio to do the same. This
  71          * information is only for display here.
  72          */
  73 #ifdef CONFIG_FSL_CORENET
  74 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  75         u32 ddr_sync = 0;       /* only async mode is supported */
  76 #else
  77         u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
  78                 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
  79 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  80 #else   /* CONFIG_FSL_CORENET */
  81 #ifdef CONFIG_DDR_CLK_FREQ
  82         u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
  83                 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  84 #else
  85         u32 ddr_ratio = 0;
  86 #endif /* CONFIG_DDR_CLK_FREQ */
  87 #endif /* CONFIG_FSL_CORENET */
  88
  89         unsigned int i, core, nr_cores = cpu_numcores();
  90         u32 mask = cpu_mask();
  91
  92         svr = get_svr();
  93         major = SVR_MAJ(svr);
  94         minor = SVR_MIN(svr);
  95
  96         if (cpu_numcores() > 1) {
  97 #ifndef CONFIG_MP
  98                 puts("Unicore software on multiprocessor system!!\n"
  99                      "To enable mutlticore build define CONFIG_MP\n");
 100 #endif
 101                 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 102                 printf("CPU%d:  ", pic->whoami);
 103         } else {
 104                 puts("CPU:   ");
 105         }
 106
 107         cpu = gd->arch.cpu;
 108
 109         puts(cpu->name);
 110         if (IS_E_PROCESSOR(svr))
 111                 puts("E");
 112
 113         printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
 114
 115         pvr = get_pvr();
 116         ver = PVR_VER(pvr);
 117         major = PVR_MAJ(pvr);
 118         minor = PVR_MIN(pvr);
 119
 120         printf("Core:  ");
 121         switch(ver) {
 122         case PVR_VER_E500_V1:
 123         case PVR_VER_E500_V2:
 124                 puts("E500");
 125                 break;
 126         case PVR_VER_E500MC:
 127                 puts("E500MC");
 128                 break;
 129         case PVR_VER_E5500:
 130                 puts("E5500");
 131                 break;
 132         case PVR_VER_E6500:
 133                 puts("E6500");
 134                 break;
 135         default:
 136                 puts("Unknown");
 137                 break;
 138         }
 139
 140         printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
 141
 142         if (nr_cores > CONFIG_MAX_CPUS) {
 143                 panic("\nUnexpected number of cores: %d, max is %d\n",
 144                         nr_cores, CONFIG_MAX_CPUS);
 145         }
 146
 147         get_sys_info(&sysinfo);
 148
 149         puts("Clock Configuration:");
 150         for_each_cpu(i, core, nr_cores, mask) {
 151                 if (!(i & 3))
 152                         printf ("\n       ");
 153                 printf("CPU%d:%-4s MHz, ", core,
 154                         strmhz(buf1, sysinfo.freqProcessor[core]));
 155         }
 156         printf("\n       CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
 157
 158 #ifdef CONFIG_FSL_CORENET
 159         if (ddr_sync == 1) {
 160                 printf("       DDR:%-4s MHz (%s MT/s data rate) "
 161                         "(Synchronous), ",
 162                         strmhz(buf1, sysinfo.freqDDRBus/2),
 163                         strmhz(buf2, sysinfo.freqDDRBus));
 164         } else {
 165                 printf("       DDR:%-4s MHz (%s MT/s data rate) "
 166                         "(Asynchronous), ",
 167                         strmhz(buf1, sysinfo.freqDDRBus/2),
 168                         strmhz(buf2, sysinfo.freqDDRBus));
 169         }
 170 #else
 171         switch (ddr_ratio) {
 172         case 0x0:
 173                 printf("       DDR:%-4s MHz (%s MT/s data rate), ",
 174                         strmhz(buf1, sysinfo.freqDDRBus/2),
 175                         strmhz(buf2, sysinfo.freqDDRBus));
 176                 break;
 177         case 0x7:
 178                 printf("       DDR:%-4s MHz (%s MT/s data rate) "
 179                         "(Synchronous), ",
 180                         strmhz(buf1, sysinfo.freqDDRBus/2),
 181                         strmhz(buf2, sysinfo.freqDDRBus));
 182                 break;
 183         default:
 184                 printf("       DDR:%-4s MHz (%s MT/s data rate) "
 185                         "(Asynchronous), ",
 186                         strmhz(buf1, sysinfo.freqDDRBus/2),
 187                         strmhz(buf2, sysinfo.freqDDRBus));
 188                 break;
 189         }
 190 #endif
 191
 192 #if defined(CONFIG_FSL_LBC)
 193         if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
 194                 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
 195         } else {
 196                 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
 197                        sysinfo.freqLocalBus);
 198         }
 199 #endif
 200
 201 #if defined(CONFIG_FSL_IFC)
 202         printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
 203 #endif
 204
 205 #ifdef CONFIG_CPM2
 206         printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
 207 #endif
 208
 209 #ifdef CONFIG_QE
 210         printf("       QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
 211 #endif
 212
 213 #ifdef CONFIG_SYS_DPAA_FMAN
 214         for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
 215                 printf("       FMAN%d: %s MHz\n", i + 1,
 216                         strmhz(buf1, sysinfo.freqFMan[i]));
 217         }
 218 #endif
 219
 220 #ifdef CONFIG_SYS_DPAA_QBMAN
 221         printf("       QMAN:  %s MHz\n", strmhz(buf1, sysinfo.freqQMAN));
 222 #endif
 223
 224 #ifdef CONFIG_SYS_DPAA_PME
 225         printf("       PME:   %s MHz\n", strmhz(buf1, sysinfo.freqPME));
 226 #endif
 227
 228         puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
 229
 230         return 0;
 231 }
 232
 233
 234 /* ------------------------------------------------------------------------- */
 235
 236 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 237 {
 238 /* Everything after the first generation of PQ3 parts has RSTCR */
 239 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
 240     defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
 241         unsigned long val, msr;
 242
 243         /*
 244          * Initiate hard reset in debug control register DBCR0
 245          * Make sure MSR[DE] = 1.  This only resets the core.
 246          */
 247         msr = mfmsr ();
 248         msr |= MSR_DE;
 249         mtmsr (msr);
 250
 251         val = mfspr(DBCR0);
 252         val |= 0x70000000;
 253         mtspr(DBCR0,val);
 254 #else
 255         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 256
 257         /* Attempt board-specific reset */
 258         board_reset();
 259
 260         /* Next try asserting HRESET_REQ */
 261         out_be32(&gur->rstcr, 0x2);
 262         udelay(100);
 263 #endif
 264
 265         return 1;
 266 }
 267
 268
 269 /*
 270  * Get timebase clock frequency
 271  */
 272 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
 273 #define CONFIG_SYS_FSL_TBCLK_DIV 8
 274 #endif
 275 unsigned long get_tbclk (void)
 276 {
 277         unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
 278
 279         return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
 280 }
 281
 282
 283 #if defined(CONFIG_WATCHDOG)
 284 void
 285 reset_85xx_watchdog(void)
 286 {
 287         /*
 288          * Clear TSR(WIS) bit by writing 1
 289          */
 290         mtspr(SPRN_TSR, TSR_WIS);
 291 }
 292
 293 void
 294 watchdog_reset(void)
 295 {
 296         int re_enable = disable_interrupts();
 297
 298         reset_85xx_watchdog();
 299         if (re_enable)
 300                 enable_interrupts();
 301 }
 302 #endif  /* CONFIG_WATCHDOG */
 303
 304 /*
 305  * Initializes on-chip MMC controllers.
 306  * to override, implement board_mmc_init()
 307  */
 308 int cpu_mmc_init(bd_t *bis)
 309 {
 310 #ifdef CONFIG_FSL_ESDHC
 311         return fsl_esdhc_mmc_init(bis);
 312 #else
 313         return 0;
 314 #endif
 315 }
 316
 317 /*
 318  * Print out the state of various machine registers.
 319  * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
 320  * parameters for IFC and TLBs
 321  */
 322 void mpc85xx_reginfo(void)
 323 {
 324         print_tlbcam();
 325         print_laws();
 326 #if defined(CONFIG_FSL_LBC)
 327         print_lbc_regs();
 328 #endif
 329 #ifdef CONFIG_FSL_IFC
 330         print_ifc_regs();
 331 #endif
 332
 333 }
 334
 335 /* Common ddr init for non-corenet fsl 85xx platforms */
 336 #ifndef CONFIG_FSL_CORENET
 337 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
 338         !defined(CONFIG_SYS_INIT_L2_ADDR)
 339 phys_size_t initdram(int board_type)
 340 {
 341 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
 342         return fsl_ddr_sdram_size();
 343 #else
 344         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 345 #endif
 346 }
 347 #else /* CONFIG_SYS_RAMBOOT */
 348 phys_size_t initdram(int board_type)
 349 {
 350         phys_size_t dram_size = 0;
 351
 352 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
 353         {
 354                 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 355                 unsigned int x = 10;
 356                 unsigned int i;
 357
 358                 /*
 359                  * Work around to stabilize DDR DLL
 360                  */
 361                 out_be32(&gur->ddrdllcr, 0x81000000);
 362                 asm("sync;isync;msync");
 363                 udelay(200);
 364                 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
 365                         setbits_be32(&gur->devdisr, 0x00010000);
 366                         for (i = 0; i < x; i++)
 367                                 ;
 368                         clrbits_be32(&gur->devdisr, 0x00010000);
 369                         x++;
 370                 }
 371         }
 372 #endif
 373
 374 #if     defined(CONFIG_SPD_EEPROM)      || \
 375         defined(CONFIG_DDR_SPD)         || \
 376         defined(CONFIG_SYS_DDR_RAW_TIMING)
 377         dram_size = fsl_ddr_sdram();
 378 #else
 379         dram_size = fixed_sdram();
 380 #endif
 381         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 382         dram_size *= 0x100000;
 383
 384 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 385         /*
 386          * Initialize and enable DDR ECC.
 387          */
 388         ddr_enable_ecc(dram_size);
 389 #endif
 390
 391 #if defined(CONFIG_FSL_LBC)
 392         /* Some boards also have sdram on the lbc */
 393         lbc_sdram_init();
 394 #endif
 395
 396         debug("DDR: ");
 397         return dram_size;
 398 }
 399 #endif /* CONFIG_SYS_RAMBOOT */
 400 #endif
 401
 402 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
 403
 404 /* Board-specific functions defined in each board's ddr.c */
 405 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 406         unsigned int ctrl_num);
 407 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
 408                        phys_addr_t *rpn);
 409 unsigned int
 410         setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
 411
 412 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
 413
 414 static void dump_spd_ddr_reg(void)
 415 {
 416         int i, j, k, m;
 417         u8 *p_8;
 418         u32 *p_32;
 419         ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
 420         generic_spd_eeprom_t
 421                 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
 422
 423         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 424                 fsl_ddr_get_spd(spd[i], i);
 425
 426         puts("SPD data of all dimms (zero vaule is omitted)...\n");
 427         puts("Byte (hex)  ");
 428         k = 1;
 429         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 430                 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
 431                         printf("Dimm%d ", k++);
 432         }
 433         puts("\n");
 434         for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
 435                 m = 0;
 436                 printf("%3d (0x%02x)  ", k, k);
 437                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 438                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 439                                 p_8 = (u8 *) &spd[i][j];
 440                                 if (p_8[k]) {
 441                                         printf("0x%02x  ", p_8[k]);
 442                                         m++;
 443                                 } else
 444                                         puts("      ");
 445                         }
 446                 }
 447                 if (m)
 448                         puts("\n");
 449                 else
 450                         puts("\r");
 451         }
 452
 453         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 454                 switch (i) {
 455                 case 0:
 456                         ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
 457                         break;
 458 #if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
 459                 case 1:
 460                         ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
 461                         break;
 462 #endif
 463 #if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
 464                 case 2:
 465                         ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
 466                         break;
 467 #endif
 468 #if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
 469                 case 3:
 470                         ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
 471                         break;
 472 #endif
 473                 default:
 474                         printf("%s unexpected controller number = %u\n",
 475                                 __func__, i);
 476                         return;
 477                 }
 478         }
 479         printf("DDR registers dump for all controllers "
 480                 "(zero vaule is omitted)...\n");
 481         puts("Offset (hex)   ");
 482         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 483                 printf("     Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
 484         puts("\n");
 485         for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
 486                 m = 0;
 487                 printf("%6d (0x%04x)", k * 4, k * 4);
 488                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 489                         p_32 = (u32 *) ddr[i];
 490                         if (p_32[k]) {
 491                                 printf("        0x%08x", p_32[k]);
 492                                 m++;
 493                         } else
 494                                 puts("                  ");
 495                 }
 496                 if (m)
 497                         puts("\n");
 498                 else
 499                         puts("\r");
 500         }
 501         puts("\n");
 502 }
 503
 504 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
 505 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
 506 {
 507         u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
 508         unsigned long epn;
 509         u32 tsize, valid, ptr;
 510         int ddr_esel;
 511
 512         clear_ddr_tlbs_phys(p_addr, size>>20);
 513
 514         /* Setup new tlb to cover the physical address */
 515         setup_ddr_tlbs_phys(p_addr, size>>20);
 516
 517         ptr = vstart;
 518         ddr_esel = find_tlb_idx((void *)ptr, 1);
 519         if (ddr_esel != -1) {
 520                 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
 521         } else {
 522                 printf("TLB error in function %s\n", __func__);
 523                 return -1;
 524         }
 525
 526         return 0;
 527 }
 528
 529 /*
 530  * slide the testing window up to test another area
 531  * for 32_bit system, the maximum testable memory is limited to
 532  * CONFIG_MAX_MEM_MAPPED
 533  */
 534 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 535 {
 536         phys_addr_t test_cap, p_addr;
 537         phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
 538
 539 #if !defined(CONFIG_PHYS_64BIT) || \
 540     !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
 541         (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
 542                 test_cap = p_size;
 543 #else
 544                 test_cap = gd->ram_size;
 545 #endif
 546         p_addr = (*vstart) + (*size) + (*phys_offset);
 547         if (p_addr < test_cap - 1) {
 548                 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
 549                 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
 550                         return -1;
 551                 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
 552                 *size = (u32) p_size;
 553                 printf("Testing 0x%08llx - 0x%08llx\n",
 554                         (u64)(*vstart) + (*phys_offset),
 555                         (u64)(*vstart) + (*phys_offset) + (*size) - 1);
 556         } else
 557                 return 1;
 558
 559         return 0;
 560 }
 561
 562 /* initialization for testing area */
 563 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 564 {
 565         phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
 566
 567         *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
 568         *size = (u32) p_size;   /* CONFIG_MAX_MEM_MAPPED < 4G */
 569         *phys_offset = 0;
 570
 571 #if !defined(CONFIG_PHYS_64BIT) || \
 572     !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
 573         (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
 574                 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
 575                         puts("Cannot test more than ");
 576                         print_size(CONFIG_MAX_MEM_MAPPED,
 577                                 " without proper 36BIT support.\n");
 578                 }
 579 #endif
 580         printf("Testing 0x%08llx - 0x%08llx\n",
 581                 (u64)(*vstart) + (*phys_offset),
 582                 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
 583
 584         return 0;
 585 }
 586
 587 /* invalid TLBs for DDR and remap as normal after testing */
 588 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 589 {
 590         unsigned long epn;
 591         u32 tsize, valid, ptr;
 592         phys_addr_t rpn = 0;
 593         int ddr_esel;
 594
 595         /* disable the TLBs for this testing */
 596         ptr = *vstart;
 597
 598         while (ptr < (*vstart) + (*size)) {
 599                 ddr_esel = find_tlb_idx((void *)ptr, 1);
 600                 if (ddr_esel != -1) {
 601                         read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
 602                         disable_tlb(ddr_esel);
 603                 }
 604                 ptr += TSIZE_TO_BYTES(tsize);
 605         }
 606
 607         puts("Remap DDR ");
 608         setup_ddr_tlbs(gd->ram_size>>20);
 609         puts("\n");
 610
 611         return 0;
 612 }
 613
 614 void arch_memory_failure_handle(void)
 615 {
 616         dump_spd_ddr_reg();
 617 }
 618 #endif