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powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS
[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu_init.c
1 /*
2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13 #include <common.h>
14 #include <watchdog.h>
15 #include <asm/processor.h>
16 #include <ioports.h>
17 #include <sata.h>
18 #include <fm_eth.h>
19 #include <asm/io.h>
20 #include <asm/cache.h>
21 #include <asm/mmu.h>
22 #include <asm/fsl_errata.h>
23 #include <asm/fsl_law.h>
24 #include <asm/fsl_serdes.h>
25 #include <asm/fsl_srio.h>
26 #include <fsl_usb.h>
27 #include <hwconfig.h>
28 #include <linux/compiler.h>
29 #include "mp.h"
30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
31 #include <nand.h>
32 #include <errno.h>
33 #endif
34
35 #include "../../../../drivers/block/fsl_sata.h"
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
40 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
41 {
42 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
43 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
44
45 /* Increase Disconnect Threshold by 50mV */
46 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
47 INC_DCNT_THRESHOLD_50MV;
48 /* Enable programming of USB High speed Disconnect threshold */
49 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
50 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
51
52 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
53 /* Increase Disconnect Threshold by 50mV */
54 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
55 INC_DCNT_THRESHOLD_50MV;
56 /* Enable programming of USB High speed Disconnect threshold */
57 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
58 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
59 #else
60
61 u32 temp = 0;
62 u32 status = in_be32(&usb_phy->status1);
63
64 u32 squelch_prog_rd_0_2 =
65 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
66 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
67
68 u32 squelch_prog_rd_3_5 =
69 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
70 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
71
72 setbits_be32(&usb_phy->config1,
73 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
74 setbits_be32(&usb_phy->config2,
75 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
76
77 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
78 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
79
80 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
81 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
82 #endif
83 }
84 #endif
85
86
87 #ifdef CONFIG_QE
88 extern qe_iop_conf_t qe_iop_conf_tab[];
89 extern void qe_config_iopin(u8 port, u8 pin, int dir,
90 int open_drain, int assign);
91 extern void qe_init(uint qe_base);
92 extern void qe_reset(void);
93
94 static void config_qe_ioports(void)
95 {
96 u8 port, pin;
97 int dir, open_drain, assign;
98 int i;
99
100 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
101 port = qe_iop_conf_tab[i].port;
102 pin = qe_iop_conf_tab[i].pin;
103 dir = qe_iop_conf_tab[i].dir;
104 open_drain = qe_iop_conf_tab[i].open_drain;
105 assign = qe_iop_conf_tab[i].assign;
106 qe_config_iopin(port, pin, dir, open_drain, assign);
107 }
108 }
109 #endif
110
111 #ifdef CONFIG_CPM2
112 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
113 {
114 int portnum;
115
116 for (portnum = 0; portnum < 4; portnum++) {
117 uint pmsk = 0,
118 ppar = 0,
119 psor = 0,
120 pdir = 0,
121 podr = 0,
122 pdat = 0;
123 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
124 iop_conf_t *eiopc = iopc + 32;
125 uint msk = 1;
126
127 /*
128 * NOTE:
129 * index 0 refers to pin 31,
130 * index 31 refers to pin 0
131 */
132 while (iopc < eiopc) {
133 if (iopc->conf) {
134 pmsk |= msk;
135 if (iopc->ppar)
136 ppar |= msk;
137 if (iopc->psor)
138 psor |= msk;
139 if (iopc->pdir)
140 pdir |= msk;
141 if (iopc->podr)
142 podr |= msk;
143 if (iopc->pdat)
144 pdat |= msk;
145 }
146
147 msk <<= 1;
148 iopc++;
149 }
150
151 if (pmsk != 0) {
152 volatile ioport_t *iop = ioport_addr (cpm, portnum);
153 uint tpmsk = ~pmsk;
154
155 /*
156 * the (somewhat confused) paragraph at the
157 * bottom of page 35-5 warns that there might
158 * be "unknown behaviour" when programming
159 * PSORx and PDIRx, if PPARx = 1, so I
160 * decided this meant I had to disable the
161 * dedicated function first, and enable it
162 * last.
163 */
164 iop->ppar &= tpmsk;
165 iop->psor = (iop->psor & tpmsk) | psor;
166 iop->podr = (iop->podr & tpmsk) | podr;
167 iop->pdat = (iop->pdat & tpmsk) | pdat;
168 iop->pdir = (iop->pdir & tpmsk) | pdir;
169 iop->ppar |= ppar;
170 }
171 }
172 }
173 #endif
174
175 #ifdef CONFIG_SYS_FSL_CPC
176 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
177 static void disable_cpc_sram(void)
178 {
179 int i;
180
181 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
182
183 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
184 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
185 /* find and disable LAW of SRAM */
186 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
187
188 if (law.index == -1) {
189 printf("\nFatal error happened\n");
190 return;
191 }
192 disable_law(law.index);
193
194 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
195 out_be32(&cpc->cpccsr0, 0);
196 out_be32(&cpc->cpcsrcr0, 0);
197 }
198 }
199 }
200 #endif
201
202 static void enable_cpc(void)
203 {
204 int i;
205 u32 size = 0;
206
207 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
208
209 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
210 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
211 size += CPC_CFG0_SZ_K(cpccfg0);
212
213 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
214 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
215 #endif
216 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
217 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
218 #endif
219 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
220 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
221 #endif
222 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
223 if (has_erratum_a006379()) {
224 setbits_be32(&cpc->cpchdbcr0,
225 CPC_HDBCR0_SPLRU_LEVEL_EN);
226 }
227 #endif
228
229 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
230 /* Read back to sync write */
231 in_be32(&cpc->cpccsr0);
232
233 }
234
235 puts("Corenet Platform Cache: ");
236 print_size(size * 1024, " enabled\n");
237 }
238
239 static void invalidate_cpc(void)
240 {
241 int i;
242 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
243
244 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
245 /* skip CPC when it used as all SRAM */
246 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
247 continue;
248 /* Flash invalidate the CPC and clear all the locks */
249 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
250 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
251 ;
252 }
253 }
254 #else
255 #define enable_cpc()
256 #define invalidate_cpc()
257 #endif /* CONFIG_SYS_FSL_CPC */
258
259 /*
260 * Breathe some life into the CPU...
261 *
262 * Set up the memory map
263 * initialize a bunch of registers
264 */
265
266 #ifdef CONFIG_FSL_CORENET
267 static void corenet_tb_init(void)
268 {
269 volatile ccsr_rcpm_t *rcpm =
270 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
271 volatile ccsr_pic_t *pic =
272 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
273 u32 whoami = in_be32(&pic->whoami);
274
275 /* Enable the timebase register for this core */
276 out_be32(&rcpm->ctbenrl, (1 << whoami));
277 }
278 #endif
279
280 void cpu_init_f (void)
281 {
282 extern void m8560_cpm_reset (void);
283 #ifdef CONFIG_SYS_DCSRBAR_PHYS
284 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
285 #endif
286 #if defined(CONFIG_SECURE_BOOT)
287 struct law_entry law;
288 #endif
289 #ifdef CONFIG_MPC8548
290 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
291 uint svr = get_svr();
292
293 /*
294 * CPU2 errata workaround: A core hang possible while executing
295 * a msync instruction and a snoopable transaction from an I/O
296 * master tagged to make quick forward progress is present.
297 * Fixed in silicon rev 2.1.
298 */
299 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
300 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
301 #endif
302
303 disable_tlb(14);
304 disable_tlb(15);
305
306 #if defined(CONFIG_SECURE_BOOT)
307 /* Disable the LAW created for NOR flash by the PBI commands */
308 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
309 if (law.index != -1)
310 disable_law(law.index);
311
312 #if defined(CONFIG_SYS_CPC_REINIT_F)
313 disable_cpc_sram();
314 #endif
315 #endif
316
317 #ifdef CONFIG_CPM2
318 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
319 #endif
320
321 init_early_memctl_regs();
322
323 #if defined(CONFIG_CPM2)
324 m8560_cpm_reset();
325 #endif
326 #ifdef CONFIG_QE
327 /* Config QE ioports */
328 config_qe_ioports();
329 #endif
330 #if defined(CONFIG_FSL_DMA)
331 dma_init();
332 #endif
333 #ifdef CONFIG_FSL_CORENET
334 corenet_tb_init();
335 #endif
336 init_used_tlb_cams();
337
338 /* Invalidate the CPC before DDR gets enabled */
339 invalidate_cpc();
340
341 #ifdef CONFIG_SYS_DCSRBAR_PHYS
342 /* set DCSRCR so that DCSR space is 1G */
343 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
344 in_be32(&gur->dcsrcr);
345 #endif
346
347 }
348
349 /* Implement a dummy function for those platforms w/o SERDES */
350 static void __fsl_serdes__init(void)
351 {
352 return ;
353 }
354 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
355
356 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
357 int enable_cluster_l2(void)
358 {
359 int i = 0;
360 u32 cluster;
361 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
362 struct ccsr_cluster_l2 __iomem *l2cache;
363
364 cluster = in_be32(&gur->tp_cluster[i].lower);
365 if (cluster & TP_CLUSTER_EOC)
366 return 0;
367
368 /* The first cache has already been set up, so skip it */
369 i++;
370
371 /* Look through the remaining clusters, and set up their caches */
372 do {
373 int j, cluster_valid = 0;
374
375 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
376
377 cluster = in_be32(&gur->tp_cluster[i].lower);
378
379 /* check that at least one core/accel is enabled in cluster */
380 for (j = 0; j < 4; j++) {
381 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
382 u32 type = in_be32(&gur->tp_ityp[idx]);
383
384 if (type & TP_ITYP_AV)
385 cluster_valid = 1;
386 }
387
388 if (cluster_valid) {
389 /* set stash ID to (cluster) * 2 + 32 + 1 */
390 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
391
392 printf("enable l2 for cluster %d %p\n", i, l2cache);
393
394 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
395 while ((in_be32(&l2cache->l2csr0)
396 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
397 ;
398 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
399 }
400 i++;
401 } while (!(cluster & TP_CLUSTER_EOC));
402
403 return 0;
404 }
405 #endif
406
407 /*
408 * Initialize L2 as cache.
409 *
410 * The newer 8548, etc, parts have twice as much cache, but
411 * use the same bit-encoding as the older 8555, etc, parts.
412 *
413 */
414 int cpu_init_r(void)
415 {
416 __maybe_unused u32 svr = get_svr();
417 #ifdef CONFIG_SYS_LBC_LCRR
418 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
419 #endif
420 #ifdef CONFIG_L2_CACHE
421 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
422 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
423 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
424 #endif
425 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
426 extern int spin_table_compat;
427 const char *spin;
428 #endif
429 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
430 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
431 #endif
432 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
433 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
434 /*
435 * CPU22 and NMG_CPU_A011 share the same workaround.
436 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
437 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
438 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
439 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
440 * be disabled by hwconfig with syntax:
441 *
442 * fsl_cpu_a011:disable
443 */
444 extern int enable_cpu_a011_workaround;
445 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
446 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
447 #else
448 char buffer[HWCONFIG_BUFFER_SIZE];
449 char *buf = NULL;
450 int n, res;
451
452 n = getenv_f("hwconfig", buffer, sizeof(buffer));
453 if (n > 0)
454 buf = buffer;
455
456 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
457 if (res > 0)
458 enable_cpu_a011_workaround = 0;
459 else {
460 if (n >= HWCONFIG_BUFFER_SIZE) {
461 printf("fsl_cpu_a011 was not found. hwconfig variable "
462 "may be too long\n");
463 }
464 enable_cpu_a011_workaround =
465 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
466 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
467 }
468 #endif
469 if (enable_cpu_a011_workaround) {
470 flush_dcache();
471 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
472 sync();
473 }
474 #endif
475 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
476 /*
477 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
478 * in write shadow mode. Checking DCWS before setting SPR 976.
479 */
480 if (mfspr(L1CSR2) & L1CSR2_DCWS)
481 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
482 #endif
483
484 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
485 spin = getenv("spin_table_compat");
486 if (spin && (*spin == 'n'))
487 spin_table_compat = 0;
488 else
489 spin_table_compat = 1;
490 #endif
491
492 puts ("L2: ");
493
494 #if defined(CONFIG_L2_CACHE)
495 volatile uint cache_ctl;
496 uint ver;
497 u32 l2siz_field;
498
499 ver = SVR_SOC_VER(svr);
500
501 asm("msync;isync");
502 cache_ctl = l2cache->l2ctl;
503
504 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
505 if (cache_ctl & MPC85xx_L2CTL_L2E) {
506 /* Clear L2 SRAM memory-mapped base address */
507 out_be32(&l2cache->l2srbar0, 0x0);
508 out_be32(&l2cache->l2srbar1, 0x0);
509
510 /* set MBECCDIS=0, SBECCDIS=0 */
511 clrbits_be32(&l2cache->l2errdis,
512 (MPC85xx_L2ERRDIS_MBECC |
513 MPC85xx_L2ERRDIS_SBECC));
514
515 /* set L2E=0, L2SRAM=0 */
516 clrbits_be32(&l2cache->l2ctl,
517 (MPC85xx_L2CTL_L2E |
518 MPC85xx_L2CTL_L2SRAM_ENTIRE));
519 }
520 #endif
521
522 l2siz_field = (cache_ctl >> 28) & 0x3;
523
524 switch (l2siz_field) {
525 case 0x0:
526 printf(" unknown size (0x%08x)\n", cache_ctl);
527 return -1;
528 break;
529 case 0x1:
530 if (ver == SVR_8540 || ver == SVR_8560 ||
531 ver == SVR_8541 || ver == SVR_8555) {
532 puts("128 KiB ");
533 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
534 cache_ctl = 0xc4000000;
535 } else {
536 puts("256 KiB ");
537 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
538 }
539 break;
540 case 0x2:
541 if (ver == SVR_8540 || ver == SVR_8560 ||
542 ver == SVR_8541 || ver == SVR_8555) {
543 puts("256 KiB ");
544 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
545 cache_ctl = 0xc8000000;
546 } else {
547 puts("512 KiB ");
548 /* set L2E=1, L2I=1, & L2SRAM=0 */
549 cache_ctl = 0xc0000000;
550 }
551 break;
552 case 0x3:
553 puts("1024 KiB ");
554 /* set L2E=1, L2I=1, & L2SRAM=0 */
555 cache_ctl = 0xc0000000;
556 break;
557 }
558
559 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
560 puts("already enabled");
561 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
562 u32 l2srbar = l2cache->l2srbar0;
563 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
564 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
565 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
566 l2cache->l2srbar0 = l2srbar;
567 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
568 }
569 #endif /* CONFIG_SYS_INIT_L2_ADDR */
570 puts("\n");
571 } else {
572 asm("msync;isync");
573 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
574 asm("msync;isync");
575 puts("enabled\n");
576 }
577 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
578 if (SVR_SOC_VER(svr) == SVR_P2040) {
579 puts("N/A\n");
580 goto skip_l2;
581 }
582
583 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
584
585 /* invalidate the L2 cache */
586 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
587 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
588 ;
589
590 #ifdef CONFIG_SYS_CACHE_STASHING
591 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
592 mtspr(SPRN_L2CSR1, (32 + 1));
593 #endif
594
595 /* enable the cache */
596 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
597
598 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
599 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
600 ;
601 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
602 }
603
604 skip_l2:
605 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
606 if (l2cache->l2csr0 & L2CSR0_L2E)
607 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
608 " enabled\n");
609
610 enable_cluster_l2();
611 #else
612 puts("disabled\n");
613 #endif
614
615 #if defined(CONFIG_RAMBOOT_PBL)
616 disable_cpc_sram();
617 #endif
618 enable_cpc();
619
620 #ifndef CONFIG_SYS_FSL_NO_SERDES
621 /* needs to be in ram since code uses global static vars */
622 fsl_serdes_init();
623 #endif
624
625 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
626 #define MCFGR_AXIPIPE 0x000000f0
627 if (IS_SVR_REV(svr, 1, 0))
628 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
629 #endif
630
631 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
632 if (IS_SVR_REV(svr, 1, 0)) {
633 int i;
634 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
635
636 for (i = 0; i < 12; i++) {
637 p += i + (i > 5 ? 11 : 0);
638 out_be32(p, 0x2);
639 }
640 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
641 out_be32(p, 0x34);
642 }
643 #endif
644
645 #ifdef CONFIG_SYS_SRIO
646 srio_init();
647 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
648 char *s = getenv("bootmaster");
649 if (s) {
650 if (!strcmp(s, "SRIO1")) {
651 srio_boot_master(1);
652 srio_boot_master_release_slave(1);
653 }
654 if (!strcmp(s, "SRIO2")) {
655 srio_boot_master(2);
656 srio_boot_master_release_slave(2);
657 }
658 }
659 #endif
660 #endif
661
662 #if defined(CONFIG_MP)
663 setup_mp();
664 #endif
665
666 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
667 {
668 if (SVR_MAJ(svr) < 3) {
669 void *p;
670 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
671 setbits_be32(p, 1 << (31 - 14));
672 }
673 }
674 #endif
675
676 #ifdef CONFIG_SYS_LBC_LCRR
677 /*
678 * Modify the CLKDIV field of LCRR register to improve the writing
679 * speed for NOR flash.
680 */
681 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
682 __raw_readl(&lbc->lcrr);
683 isync();
684 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
685 udelay(100);
686 #endif
687 #endif
688
689 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
690 {
691 struct ccsr_usb_phy __iomem *usb_phy1 =
692 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
693 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
694 if (has_erratum_a006261())
695 fsl_erratum_a006261_workaround(usb_phy1);
696 #endif
697 out_be32(&usb_phy1->usb_enable_override,
698 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
699 }
700 #endif
701 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
702 {
703 struct ccsr_usb_phy __iomem *usb_phy2 =
704 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
705 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
706 if (has_erratum_a006261())
707 fsl_erratum_a006261_workaround(usb_phy2);
708 #endif
709 out_be32(&usb_phy2->usb_enable_override,
710 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
711 }
712 #endif
713
714 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
715 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
716 * multi-bit ECC errors which has impact on performance, so software
717 * should disable all ECC reporting from USB1 and USB2.
718 */
719 if (IS_SVR_REV(get_svr(), 1, 0)) {
720 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
721 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
722 setbits_be32(&dcfg->ecccr1,
723 (DCSR_DCFG_ECC_DISABLE_USB1 |
724 DCSR_DCFG_ECC_DISABLE_USB2));
725 }
726 #endif
727
728 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
729 struct ccsr_usb_phy __iomem *usb_phy =
730 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
731 setbits_be32(&usb_phy->pllprg[1],
732 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
733 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
734 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
735 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
736 setbits_be32(&usb_phy->port1.ctrl,
737 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
738 setbits_be32(&usb_phy->port1.drvvbuscfg,
739 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
740 setbits_be32(&usb_phy->port1.pwrfltcfg,
741 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
742 setbits_be32(&usb_phy->port2.ctrl,
743 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
744 setbits_be32(&usb_phy->port2.drvvbuscfg,
745 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
746 setbits_be32(&usb_phy->port2.pwrfltcfg,
747 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
748
749 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
750 if (has_erratum_a006261())
751 fsl_erratum_a006261_workaround(usb_phy);
752 #endif
753
754 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
755
756 #ifdef CONFIG_FMAN_ENET
757 fman_enet_init();
758 #endif
759
760 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
761 /*
762 * For P1022/1013 Rev1.0 silicon, after power on SATA host
763 * controller is configured in legacy mode instead of the
764 * expected enterprise mode. Software needs to clear bit[28]
765 * of HControl register to change to enterprise mode from
766 * legacy mode. We assume that the controller is offline.
767 */
768 if (IS_SVR_REV(svr, 1, 0) &&
769 ((SVR_SOC_VER(svr) == SVR_P1022) ||
770 (SVR_SOC_VER(svr) == SVR_P1013))) {
771 fsl_sata_reg_t *reg;
772
773 /* first SATA controller */
774 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
775 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
776
777 /* second SATA controller */
778 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
779 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
780 }
781 #endif
782
783
784 return 0;
785 }
786
787 void arch_preboot_os(void)
788 {
789 u32 msr;
790
791 /*
792 * We are changing interrupt offsets and are about to boot the OS so
793 * we need to make sure we disable all async interrupts. EE is already
794 * disabled by the time we get called.
795 */
796 msr = mfmsr();
797 msr &= ~(MSR_ME|MSR_CE);
798 mtmsr(msr);
799 }
800
801 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
802 int sata_initialize(void)
803 {
804 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
805 return __sata_initialize();
806
807 return 1;
808 }
809 #endif
810
811 void cpu_secondary_init_r(void)
812 {
813 #ifdef CONFIG_QE
814 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
815 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
816 int ret;
817 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
818
819 /* load QE firmware from NAND flash to DDR first */
820 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
821 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
822
823 if (ret && ret == -EUCLEAN) {
824 printf ("NAND read for QE firmware at offset %x failed %d\n",
825 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
826 }
827 #endif
828 qe_init(qe_base);
829 qe_reset();
830 #endif
831 }
"Das U-Boot" Source Tree