2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <fdt_support.h>
29 #include <asm/processor.h>
30 #include <linux/ctype.h>
32 #include <asm/fsl_portals.h>
33 #ifdef CONFIG_FSL_ESDHC
34 #include <fsl_esdhc.h>
36 #include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */
38 DECLARE_GLOBAL_DATA_PTR
;
40 extern void ft_qe_setup(void *blob
);
41 extern void ft_fixup_num_cores(void *blob
);
42 extern void ft_srio_setup(void *blob
);
47 void ft_fixup_cpu(void *blob
, u64 memory_limit
)
50 ulong spin_tbl_addr
= get_spin_phys_addr();
51 u32 bootpg
= determine_mp_bootpg();
53 const char *enable_method
;
55 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
56 while (off
!= -FDT_ERR_NOTFOUND
) {
57 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
60 u64 val
= *reg
* SIZE_BOOT_ENTRY
+ spin_tbl_addr
;
61 val
= cpu_to_fdt32(val
);
63 fdt_setprop_string(blob
, off
, "status",
66 fdt_setprop_string(blob
, off
, "status",
70 if (hold_cores_in_reset(0)) {
71 #ifdef CONFIG_FSL_CORENET
72 /* Cores held in reset, use BRR to release */
73 enable_method
= "fsl,brr-holdoff";
75 /* Cores held in reset, use EEBPCR to release */
76 enable_method
= "fsl,eebpcr-holdoff";
79 /* Cores out of reset and in a spin-loop */
80 enable_method
= "spin-table";
82 fdt_setprop(blob
, off
, "cpu-release-addr",
86 fdt_setprop_string(blob
, off
, "enable-method",
89 printf ("cpu NULL\n");
91 off
= fdt_node_offset_by_prop_value(blob
, off
,
92 "device_type", "cpu", 4);
95 /* Reserve the boot page so OSes dont use it */
96 if ((u64
)bootpg
< memory_limit
) {
97 off
= fdt_add_mem_rsv(blob
, bootpg
, (u64
)4096);
99 printf("%s: %s\n", __FUNCTION__
, fdt_strerror(off
));
104 #ifdef CONFIG_SYS_FSL_CPC
105 static inline void ft_fixup_l3cache(void *blob
, int off
)
107 u32 line_size
, num_ways
, size
, num_sets
;
108 cpc_corenet_t
*cpc
= (void *)CONFIG_SYS_FSL_CPC_ADDR
;
109 u32 cfg0
= in_be32(&cpc
->cpccfg0
);
111 size
= CPC_CFG0_SZ_K(cfg0
) * 1024 * CONFIG_SYS_NUM_CPC
;
112 num_ways
= CPC_CFG0_NUM_WAYS(cfg0
);
113 line_size
= CPC_CFG0_LINE_SZ(cfg0
);
114 num_sets
= size
/ (line_size
* num_ways
);
116 fdt_setprop(blob
, off
, "cache-unified", NULL
, 0);
117 fdt_setprop_cell(blob
, off
, "cache-block-size", line_size
);
118 fdt_setprop_cell(blob
, off
, "cache-size", size
);
119 fdt_setprop_cell(blob
, off
, "cache-sets", num_sets
);
120 fdt_setprop_cell(blob
, off
, "cache-level", 3);
121 #ifdef CONFIG_SYS_CACHE_STASHING
122 fdt_setprop_cell(blob
, off
, "cache-stash-id", 1);
126 #define ft_fixup_l3cache(x, y)
129 #if defined(CONFIG_L2_CACHE)
130 /* return size in kilobytes */
131 static inline u32
l2cache_size(void)
133 volatile ccsr_l2cache_t
*l2cache
= (void *)CONFIG_SYS_MPC85xx_L2_ADDR
;
134 volatile u32 l2siz_field
= (l2cache
->l2ctl
>> 28) & 0x3;
135 u32 ver
= SVR_SOC_VER(get_svr());
137 switch (l2siz_field
) {
141 if (ver
== SVR_8540
|| ver
== SVR_8560
||
142 ver
== SVR_8541
|| ver
== SVR_8555
)
148 if (ver
== SVR_8540
|| ver
== SVR_8560
||
149 ver
== SVR_8541
|| ver
== SVR_8555
)
162 static inline void ft_fixup_l2cache(void *blob
)
166 struct cpu_type
*cpu
= identify_cpu(SVR_SOC_VER(get_svr()));
168 const u32 line_size
= 32;
169 const u32 num_ways
= 8;
170 const u32 size
= l2cache_size() * 1024;
171 const u32 num_sets
= size
/ (line_size
* num_ways
);
173 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
175 debug("no cpu node fount\n");
179 ph
= (u32
*)fdt_getprop(blob
, off
, "next-level-cache", 0);
182 debug("no next-level-cache property\n");
186 off
= fdt_node_offset_by_phandle(blob
, *ph
);
188 printf("%s: %s\n", __func__
, fdt_strerror(off
));
195 if (isdigit(cpu
->name
[0])) {
196 /* MPCxxxx, where xxxx == 4-digit number */
197 len
= sprintf(buf
, "fsl,mpc%s-l2-cache-controller",
200 /* Pxxxx or Txxxx, where xxxx == 4-digit number */
201 len
= sprintf(buf
, "fsl,%c%s-l2-cache-controller",
202 tolower(cpu
->name
[0]), cpu
->name
+ 1) + 1;
206 * append "cache" after the NULL character that the previous
207 * sprintf wrote. This is how a device tree stores multiple
208 * strings in a property.
210 len
+= sprintf(buf
+ len
, "cache") + 1;
212 fdt_setprop(blob
, off
, "compatible", buf
, len
);
214 fdt_setprop(blob
, off
, "cache-unified", NULL
, 0);
215 fdt_setprop_cell(blob
, off
, "cache-block-size", line_size
);
216 fdt_setprop_cell(blob
, off
, "cache-size", size
);
217 fdt_setprop_cell(blob
, off
, "cache-sets", num_sets
);
218 fdt_setprop_cell(blob
, off
, "cache-level", 2);
220 /* we dont bother w/L3 since no platform of this type has one */
222 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
223 static inline void ft_fixup_l2cache(void *blob
)
225 int off
, l2_off
, l3_off
= -1;
227 u32 l2cfg0
= mfspr(SPRN_L2CFG0
);
228 u32 size
, line_size
, num_ways
, num_sets
;
231 /* P2040/P2040E has no L2, so dont set any L2 props */
232 if (SVR_SOC_VER(get_svr()) == SVR_P2040
)
235 size
= (l2cfg0
& 0x3fff) * 64 * 1024;
236 num_ways
= ((l2cfg0
>> 14) & 0x1f) + 1;
237 line_size
= (((l2cfg0
>> 23) & 0x3) + 1) * 32;
238 num_sets
= size
/ (line_size
* num_ways
);
240 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
242 while (off
!= -FDT_ERR_NOTFOUND
) {
243 ph
= (u32
*)fdt_getprop(blob
, off
, "next-level-cache", 0);
246 debug("no next-level-cache property\n");
250 l2_off
= fdt_node_offset_by_phandle(blob
, *ph
);
252 printf("%s: %s\n", __func__
, fdt_strerror(off
));
257 #ifdef CONFIG_SYS_CACHE_STASHING
258 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
260 fdt_setprop_cell(blob
, l2_off
, "cache-stash-id",
261 (*reg
* 2) + 32 + 1);
264 fdt_setprop(blob
, l2_off
, "cache-unified", NULL
, 0);
265 fdt_setprop_cell(blob
, l2_off
, "cache-block-size",
267 fdt_setprop_cell(blob
, l2_off
, "cache-size", size
);
268 fdt_setprop_cell(blob
, l2_off
, "cache-sets", num_sets
);
269 fdt_setprop_cell(blob
, l2_off
, "cache-level", 2);
270 fdt_setprop(blob
, l2_off
, "compatible", "cache", 6);
274 ph
= (u32
*)fdt_getprop(blob
, l2_off
, "next-level-cache", 0);
277 debug("no next-level-cache property\n");
283 off
= fdt_node_offset_by_prop_value(blob
, off
,
284 "device_type", "cpu", 4);
287 l3_off
= fdt_node_offset_by_phandle(blob
, l3_off
);
289 printf("%s: %s\n", __func__
, fdt_strerror(off
));
292 ft_fixup_l3cache(blob
, l3_off
);
296 #define ft_fixup_l2cache(x)
299 static inline void ft_fixup_cache(void *blob
)
303 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
305 while (off
!= -FDT_ERR_NOTFOUND
) {
306 u32 l1cfg0
= mfspr(SPRN_L1CFG0
);
307 u32 l1cfg1
= mfspr(SPRN_L1CFG1
);
308 u32 isize
, iline_size
, inum_sets
, inum_ways
;
309 u32 dsize
, dline_size
, dnum_sets
, dnum_ways
;
312 dsize
= (l1cfg0
& 0x7ff) * 1024;
313 dnum_ways
= ((l1cfg0
>> 11) & 0xff) + 1;
314 dline_size
= (((l1cfg0
>> 23) & 0x3) + 1) * 32;
315 dnum_sets
= dsize
/ (dline_size
* dnum_ways
);
317 fdt_setprop_cell(blob
, off
, "d-cache-block-size", dline_size
);
318 fdt_setprop_cell(blob
, off
, "d-cache-size", dsize
);
319 fdt_setprop_cell(blob
, off
, "d-cache-sets", dnum_sets
);
321 #ifdef CONFIG_SYS_CACHE_STASHING
323 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
325 fdt_setprop_cell(blob
, off
, "cache-stash-id",
326 (*reg
* 2) + 32 + 0);
331 isize
= (l1cfg1
& 0x7ff) * 1024;
332 inum_ways
= ((l1cfg1
>> 11) & 0xff) + 1;
333 iline_size
= (((l1cfg1
>> 23) & 0x3) + 1) * 32;
334 inum_sets
= isize
/ (iline_size
* inum_ways
);
336 fdt_setprop_cell(blob
, off
, "i-cache-block-size", iline_size
);
337 fdt_setprop_cell(blob
, off
, "i-cache-size", isize
);
338 fdt_setprop_cell(blob
, off
, "i-cache-sets", inum_sets
);
340 off
= fdt_node_offset_by_prop_value(blob
, off
,
341 "device_type", "cpu", 4);
344 ft_fixup_l2cache(blob
);
348 void fdt_add_enet_stashing(void *fdt
)
350 do_fixup_by_compat(fdt
, "gianfar", "bd-stash", NULL
, 0, 1);
352 do_fixup_by_compat_u32(fdt
, "gianfar", "rx-stash-len", 96, 1);
354 do_fixup_by_compat_u32(fdt
, "gianfar", "rx-stash-idx", 0, 1);
355 do_fixup_by_compat(fdt
, "fsl,etsec2", "bd-stash", NULL
, 0, 1);
356 do_fixup_by_compat_u32(fdt
, "fsl,etsec2", "rx-stash-len", 96, 1);
357 do_fixup_by_compat_u32(fdt
, "fsl,etsec2", "rx-stash-idx", 0, 1);
360 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
361 #ifdef CONFIG_SYS_DPAA_FMAN
362 static void ft_fixup_clks(void *blob
, const char *compat
, u32 offset
,
365 phys_addr_t phys
= offset
+ CONFIG_SYS_CCSRBAR_PHYS
;
366 int off
= fdt_node_offset_by_compat_reg(blob
, compat
, phys
);
369 off
= fdt_setprop_cell(blob
, off
, "clock-frequency", freq
);
371 printf("WARNING enable to set clock-frequency "
372 "for %s: %s\n", compat
, fdt_strerror(off
));
377 static void ft_fixup_dpaa_clks(void *blob
)
381 get_sys_info(&sysinfo
);
382 #ifdef CONFIG_SYS_DPAA_FMAN
383 ft_fixup_clks(blob
, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET
,
384 sysinfo
.freqFMan
[0]);
386 #if (CONFIG_SYS_NUM_FMAN == 2)
387 ft_fixup_clks(blob
, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET
,
388 sysinfo
.freqFMan
[1]);
392 #ifdef CONFIG_SYS_DPAA_PME
393 do_fixup_by_compat_u32(blob
, "fsl,pme",
394 "clock-frequency", sysinfo
.freqPME
, 1);
398 #define ft_fixup_dpaa_clks(x)
402 static void ft_fixup_qe_snum(void *blob
)
406 svr
= mfspr(SPRN_SVR
);
407 if (SVR_SOC_VER(svr
) == SVR_8569
) {
408 if(IS_SVR_REV(svr
, 1, 0))
409 do_fixup_by_compat_u32(blob
, "fsl,qe",
410 "fsl,qe-num-snums", 46, 1);
412 do_fixup_by_compat_u32(blob
, "fsl,qe",
413 "fsl,qe-num-snums", 76, 1);
419 * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree
421 * The binding for an Fman firmware node is documented in
422 * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains
423 * the actual Fman firmware binary data. The operating system is expected to
424 * be able to parse the binary data to determine any attributes it needs.
426 #ifdef CONFIG_SYS_DPAA_FMAN
427 void fdt_fixup_fman_firmware(void *blob
)
429 int rc
, fmnode
, fwnode
= -1;
431 struct qe_firmware
*fmanfw
;
432 const struct qe_header
*hdr
;
437 /* The first Fman we find will contain the actual firmware. */
438 fmnode
= fdt_node_offset_by_compatible(blob
, -1, "fsl,fman");
440 /* Exit silently if there are no Fman devices */
443 /* If we already have a firmware node, then also exit silently. */
444 if (fdt_node_offset_by_compatible(blob
, -1, "fsl,fman-firmware") > 0)
447 /* If the environment variable is not set, then exit silently */
448 p
= getenv("fman_ucode");
452 fmanfw
= (struct qe_firmware
*) simple_strtoul(p
, NULL
, 0);
456 hdr
= &fmanfw
->header
;
457 length
= be32_to_cpu(hdr
->length
);
459 /* Verify the firmware. */
460 if ((hdr
->magic
[0] != 'Q') || (hdr
->magic
[1] != 'E') ||
461 (hdr
->magic
[2] != 'F')) {
462 printf("Data at %p is not an Fman firmware\n", fmanfw
);
466 if (length
> CONFIG_SYS_QE_FMAN_FW_LENGTH
) {
467 printf("Fman firmware at %p is too large (size=%u)\n",
472 length
-= sizeof(u32
); /* Subtract the size of the CRC */
473 crc
= be32_to_cpu(*(u32
*)((void *)fmanfw
+ length
));
474 if (crc
!= crc32_no_comp(0, (void *)fmanfw
, length
)) {
475 printf("Fman firmware at %p has invalid CRC\n", fmanfw
);
479 /* Increase the size of the fdt to make room for the node. */
480 rc
= fdt_increase_size(blob
, fmanfw
->header
.length
);
482 printf("Unable to make room for Fman firmware: %s\n",
487 /* Create the firmware node. */
488 fwnode
= fdt_add_subnode(blob
, fmnode
, "fman-firmware");
491 fdt_get_path(blob
, fmnode
, s
, sizeof(s
));
492 printf("Could not add firmware node to %s: %s\n", s
,
493 fdt_strerror(fwnode
));
496 rc
= fdt_setprop_string(blob
, fwnode
, "compatible", "fsl,fman-firmware");
499 fdt_get_path(blob
, fwnode
, s
, sizeof(s
));
500 printf("Could not add compatible property to node %s: %s\n", s
,
504 phandle
= fdt_create_phandle(blob
, fwnode
);
507 fdt_get_path(blob
, fwnode
, s
, sizeof(s
));
508 printf("Could not add phandle property to node %s: %s\n", s
,
512 rc
= fdt_setprop(blob
, fwnode
, "fsl,firmware", fmanfw
, fmanfw
->header
.length
);
515 fdt_get_path(blob
, fwnode
, s
, sizeof(s
));
516 printf("Could not add firmware property to node %s: %s\n", s
,
521 /* Find all other Fman nodes and point them to the firmware node. */
522 while ((fmnode
= fdt_node_offset_by_compatible(blob
, fmnode
, "fsl,fman")) > 0) {
523 rc
= fdt_setprop_cell(blob
, fmnode
, "fsl,firmware-phandle", phandle
);
526 fdt_get_path(blob
, fmnode
, s
, sizeof(s
));
527 printf("Could not add pointer property to node %s: %s\n",
528 s
, fdt_strerror(rc
));
534 #define fdt_fixup_fman_firmware(x)
537 #if defined(CONFIG_PPC_P4080)
538 static void fdt_fixup_usb(void *fdt
)
540 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
541 u32 rcwsr11
= in_be32(&gur
->rcwsr
[11]);
544 off
= fdt_node_offset_by_compatible(fdt
, -1, "fsl,mpc85xx-usb2-mph");
545 if ((rcwsr11
& FSL_CORENET_RCWSR11_EC1
) !=
546 FSL_CORENET_RCWSR11_EC1_FM1_USB1
)
547 fdt_status_disabled(fdt
, off
);
549 off
= fdt_node_offset_by_compatible(fdt
, -1, "fsl,mpc85xx-usb2-dr");
550 if ((rcwsr11
& FSL_CORENET_RCWSR11_EC2
) !=
551 FSL_CORENET_RCWSR11_EC2_USB2
)
552 fdt_status_disabled(fdt
, off
);
555 #define fdt_fixup_usb(x)
558 void ft_cpu_setup(void *blob
, bd_t
*bd
)
564 /* delete crypto node if not on an E-processor */
565 if (!IS_E_PROCESSOR(get_svr()))
566 fdt_fixup_crypto_node(blob
, 0);
568 fdt_fixup_ethernet(blob
);
570 fdt_add_enet_stashing(blob
);
572 do_fixup_by_prop_u32(blob
, "device_type", "cpu", 4,
573 "timebase-frequency", get_tbclk(), 1);
574 do_fixup_by_prop_u32(blob
, "device_type", "cpu", 4,
575 "bus-frequency", bd
->bi_busfreq
, 1);
576 get_sys_info(&sysinfo
);
577 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
578 while (off
!= -FDT_ERR_NOTFOUND
) {
579 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
580 val
= cpu_to_fdt32(sysinfo
.freqProcessor
[*reg
]);
581 fdt_setprop(blob
, off
, "clock-frequency", &val
, 4);
582 off
= fdt_node_offset_by_prop_value(blob
, off
, "device_type",
585 do_fixup_by_prop_u32(blob
, "device_type", "soc", 4,
586 "bus-frequency", bd
->bi_busfreq
, 1);
588 do_fixup_by_compat_u32(blob
, "fsl,pq3-localbus",
589 "bus-frequency", gd
->lbc_clk
, 1);
590 do_fixup_by_compat_u32(blob
, "fsl,elbc",
591 "bus-frequency", gd
->lbc_clk
, 1);
594 ft_fixup_qe_snum(blob
);
597 fdt_fixup_fman_firmware(blob
);
599 #ifdef CONFIG_SYS_NS16550
600 do_fixup_by_compat_u32(blob
, "ns16550",
601 "clock-frequency", CONFIG_SYS_NS16550_CLK
, 1);
605 do_fixup_by_compat_u32(blob
, "fsl,cpm2-scc-uart",
606 "current-speed", bd
->bi_baudrate
, 1);
608 do_fixup_by_compat_u32(blob
, "fsl,cpm2-brg",
609 "clock-frequency", bd
->bi_brgfreq
, 1);
612 #ifdef CONFIG_FSL_CORENET
613 do_fixup_by_compat_u32(blob
, "fsl,qoriq-clockgen-1.0",
614 "clock-frequency", CONFIG_SYS_CLK_FREQ
, 1);
617 fdt_fixup_memory(blob
, (u64
)bd
->bi_memstart
, (u64
)bd
->bi_memsize
);
620 ft_fixup_cpu(blob
, (u64
)bd
->bi_memstart
+ (u64
)bd
->bi_memsize
);
621 ft_fixup_num_cores(blob
);
624 ft_fixup_cache(blob
);
626 #if defined(CONFIG_FSL_ESDHC)
627 fdt_fixup_esdhc(blob
, bd
);
630 ft_fixup_dpaa_clks(blob
);
632 #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
633 fdt_portal(blob
, "fsl,bman-portal", "bman-portals",
634 (u64
)CONFIG_SYS_BMAN_MEM_PHYS
,
635 CONFIG_SYS_BMAN_MEM_SIZE
);
636 fdt_fixup_bportals(blob
);
639 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
640 fdt_portal(blob
, "fsl,qman-portal", "qman-portals",
641 (u64
)CONFIG_SYS_QMAN_MEM_PHYS
,
642 CONFIG_SYS_QMAN_MEM_SIZE
);
644 fdt_fixup_qportals(blob
);
647 #ifdef CONFIG_SYS_SRIO
652 * system-clock = CCB clock/2
653 * Here gd->bus_clk = CCB clock
654 * We are using the system clock as 1588 Timer reference
655 * clock source select
657 do_fixup_by_compat_u32(blob
, "fsl,gianfar-ptp-timer",
658 "timer-frequency", gd
->bus_clk
/2, 1);
661 * clock-freq should change to clock-frequency and
662 * flexcan-v1.0 should change to p1010-flexcan respectively
665 do_fixup_by_compat_u32(blob
, "fsl,flexcan-v1.0",
666 "clock_freq", gd
->bus_clk
/2, 1);
668 do_fixup_by_compat_u32(blob
, "fsl,flexcan-v1.0",
669 "clock-frequency", gd
->bus_clk
/2, 1);
671 do_fixup_by_compat_u32(blob
, "fsl,p1010-flexcan",
672 "clock-frequency", gd
->bus_clk
/2, 1);
678 * For some CCSR devices, we only have the virtual address, not the physical
679 * address. This is because we map CCSR as a whole, so we typically don't need
680 * a macro for the physical address of any device within CCSR. In this case,
681 * we calculate the physical address of that device using it's the difference
682 * between the virtual address of the device and the virtual address of the
685 #define CCSR_VIRT_TO_PHYS(x) \
686 (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
688 static void msg(const char *name
, uint64_t uaddr
, uint64_t daddr
)
690 printf("Warning: U-Boot configured %s at address %llx,\n"
691 "but the device tree has it at %llx\n", name
, uaddr
, daddr
);
695 * Verify the device tree
697 * This function compares several CONFIG_xxx macros that contain physical
698 * addresses with the corresponding nodes in the device tree, to see if
699 * the physical addresses are all correct. For example, if
700 * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
701 * of the first UART. We convert this to a physical address and compare
702 * that with the physical address of the first ns16550-compatible node
703 * in the device tree. If they don't match, then we display a warning.
705 * Returns 1 on success, 0 on failure
707 int ft_verify_fdt(void *fdt
)
713 /* First check the CCSR base address */
714 off
= fdt_node_offset_by_prop_value(fdt
, -1, "device_type", "soc", 4);
716 addr
= fdt_get_base_address(fdt
, off
);
719 printf("Warning: could not determine base CCSR address in "
721 /* No point in checking anything else */
725 if (addr
!= CONFIG_SYS_CCSRBAR_PHYS
) {
726 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS
, addr
);
727 /* No point in checking anything else */
732 * Check some nodes via aliases. We assume that U-Boot and the device
733 * tree enumerate the devices equally. E.g. the first serial port in
734 * U-Boot is the same as "serial0" in the device tree.
736 aliases
= fdt_path_offset(fdt
, "/aliases");
738 #ifdef CONFIG_SYS_NS16550_COM1
739 if (!fdt_verify_alias_address(fdt
, aliases
, "serial0",
740 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1
)))
744 #ifdef CONFIG_SYS_NS16550_COM2
745 if (!fdt_verify_alias_address(fdt
, aliases
, "serial1",
746 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2
)))
752 * The localbus node is typically a root node, even though the lbc
753 * controller is part of CCSR. If we were to put the lbc node under
754 * the SOC node, then the 'ranges' property in the lbc node would
755 * translate through the 'ranges' property of the parent SOC node, and
756 * we don't want that. Since it's a separate node, it's possible for
757 * the 'reg' property to be wrong, so check it here. For now, we
758 * only check for "fsl,elbc" nodes.
760 #ifdef CONFIG_SYS_LBC_ADDR
761 off
= fdt_node_offset_by_compatible(fdt
, -1, "fsl,elbc");
763 const u32
*reg
= fdt_getprop(fdt
, off
, "reg", NULL
);
765 uint64_t uaddr
= CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR
);
767 addr
= fdt_translate_address(fdt
, off
, reg
);
769 msg("the localbus", uaddr
, addr
);