2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <fdt_support.h>
29 #include <asm/processor.h>
30 #include <linux/ctype.h>
32 #include <asm/fsl_portals.h>
33 #ifdef CONFIG_FSL_ESDHC
34 #include <fsl_esdhc.h>
36 #include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */
38 DECLARE_GLOBAL_DATA_PTR
;
40 extern void ft_qe_setup(void *blob
);
41 extern void ft_fixup_num_cores(void *blob
);
42 extern void ft_srio_setup(void *blob
);
47 void ft_fixup_cpu(void *blob
, u64 memory_limit
)
50 phys_addr_t spin_tbl_addr
= get_spin_phys_addr();
51 u32 bootpg
= determine_mp_bootpg(NULL
);
53 const char *enable_method
;
55 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
56 while (off
!= -FDT_ERR_NOTFOUND
) {
57 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
60 u32 phys_cpu_id
= thread_to_core(*reg
);
61 u64 val
= phys_cpu_id
* SIZE_BOOT_ENTRY
+ spin_tbl_addr
;
62 val
= cpu_to_fdt64(val
);
64 fdt_setprop_string(blob
, off
, "status",
67 fdt_setprop_string(blob
, off
, "status",
71 if (hold_cores_in_reset(0)) {
72 #ifdef CONFIG_FSL_CORENET
73 /* Cores held in reset, use BRR to release */
74 enable_method
= "fsl,brr-holdoff";
76 /* Cores held in reset, use EEBPCR to release */
77 enable_method
= "fsl,eebpcr-holdoff";
80 /* Cores out of reset and in a spin-loop */
81 enable_method
= "spin-table";
83 fdt_setprop(blob
, off
, "cpu-release-addr",
87 fdt_setprop_string(blob
, off
, "enable-method",
90 printf ("cpu NULL\n");
92 off
= fdt_node_offset_by_prop_value(blob
, off
,
93 "device_type", "cpu", 4);
96 /* Reserve the boot page so OSes dont use it */
97 if ((u64
)bootpg
< memory_limit
) {
98 off
= fdt_add_mem_rsv(blob
, bootpg
, (u64
)4096);
100 printf("Failed to reserve memory for bootpg: %s\n",
104 #ifndef CONFIG_MPC8xxx_DISABLE_BPTR
106 * Reserve the default boot page so OSes dont use it.
107 * The default boot page is always mapped to bootpg above using
108 * boot page translation.
110 if (0xfffff000ull
< memory_limit
) {
111 off
= fdt_add_mem_rsv(blob
, 0xfffff000ull
, (u64
)4096);
113 printf("Failed to reserve memory for 0xfffff000: %s\n",
119 /* Reserve spin table page */
120 if (spin_tbl_addr
< memory_limit
) {
121 off
= fdt_add_mem_rsv(blob
,
122 (spin_tbl_addr
& ~0xffful
), 4096);
124 printf("Failed to reserve memory for spin table: %s\n",
130 #ifdef CONFIG_SYS_FSL_CPC
131 static inline void ft_fixup_l3cache(void *blob
, int off
)
133 u32 line_size
, num_ways
, size
, num_sets
;
134 cpc_corenet_t
*cpc
= (void *)CONFIG_SYS_FSL_CPC_ADDR
;
135 u32 cfg0
= in_be32(&cpc
->cpccfg0
);
137 size
= CPC_CFG0_SZ_K(cfg0
) * 1024 * CONFIG_SYS_NUM_CPC
;
138 num_ways
= CPC_CFG0_NUM_WAYS(cfg0
);
139 line_size
= CPC_CFG0_LINE_SZ(cfg0
);
140 num_sets
= size
/ (line_size
* num_ways
);
142 fdt_setprop(blob
, off
, "cache-unified", NULL
, 0);
143 fdt_setprop_cell(blob
, off
, "cache-block-size", line_size
);
144 fdt_setprop_cell(blob
, off
, "cache-size", size
);
145 fdt_setprop_cell(blob
, off
, "cache-sets", num_sets
);
146 fdt_setprop_cell(blob
, off
, "cache-level", 3);
147 #ifdef CONFIG_SYS_CACHE_STASHING
148 fdt_setprop_cell(blob
, off
, "cache-stash-id", 1);
152 #define ft_fixup_l3cache(x, y)
155 #if defined(CONFIG_L2_CACHE)
156 /* return size in kilobytes */
157 static inline u32
l2cache_size(void)
159 volatile ccsr_l2cache_t
*l2cache
= (void *)CONFIG_SYS_MPC85xx_L2_ADDR
;
160 volatile u32 l2siz_field
= (l2cache
->l2ctl
>> 28) & 0x3;
161 u32 ver
= SVR_SOC_VER(get_svr());
163 switch (l2siz_field
) {
167 if (ver
== SVR_8540
|| ver
== SVR_8560
||
168 ver
== SVR_8541
|| ver
== SVR_8555
)
174 if (ver
== SVR_8540
|| ver
== SVR_8560
||
175 ver
== SVR_8541
|| ver
== SVR_8555
)
188 static inline void ft_fixup_l2cache(void *blob
)
192 struct cpu_type
*cpu
= identify_cpu(SVR_SOC_VER(get_svr()));
194 const u32 line_size
= 32;
195 const u32 num_ways
= 8;
196 const u32 size
= l2cache_size() * 1024;
197 const u32 num_sets
= size
/ (line_size
* num_ways
);
199 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
201 debug("no cpu node fount\n");
205 ph
= (u32
*)fdt_getprop(blob
, off
, "next-level-cache", 0);
208 debug("no next-level-cache property\n");
212 off
= fdt_node_offset_by_phandle(blob
, *ph
);
214 printf("%s: %s\n", __func__
, fdt_strerror(off
));
221 if (isdigit(cpu
->name
[0])) {
222 /* MPCxxxx, where xxxx == 4-digit number */
223 len
= sprintf(buf
, "fsl,mpc%s-l2-cache-controller",
226 /* Pxxxx or Txxxx, where xxxx == 4-digit number */
227 len
= sprintf(buf
, "fsl,%c%s-l2-cache-controller",
228 tolower(cpu
->name
[0]), cpu
->name
+ 1) + 1;
232 * append "cache" after the NULL character that the previous
233 * sprintf wrote. This is how a device tree stores multiple
234 * strings in a property.
236 len
+= sprintf(buf
+ len
, "cache") + 1;
238 fdt_setprop(blob
, off
, "compatible", buf
, len
);
240 fdt_setprop(blob
, off
, "cache-unified", NULL
, 0);
241 fdt_setprop_cell(blob
, off
, "cache-block-size", line_size
);
242 fdt_setprop_cell(blob
, off
, "cache-size", size
);
243 fdt_setprop_cell(blob
, off
, "cache-sets", num_sets
);
244 fdt_setprop_cell(blob
, off
, "cache-level", 2);
246 /* we dont bother w/L3 since no platform of this type has one */
248 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
249 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
250 static inline void ft_fixup_l2cache(void *blob
)
252 int off
, l2_off
, l3_off
= -1;
254 #ifdef CONFIG_BACKSIDE_L2_CACHE
255 u32 l2cfg0
= mfspr(SPRN_L2CFG0
);
257 struct ccsr_cluster_l2
*l2cache
=
258 (struct ccsr_cluster_l2 __iomem
*)(CONFIG_SYS_FSL_CLUSTER_1_L2
);
259 u32 l2cfg0
= in_be32(&l2cache
->l2cfg0
);
261 u32 size
, line_size
, num_ways
, num_sets
;
264 /* P2040/P2040E has no L2, so dont set any L2 props */
265 if (SVR_SOC_VER(get_svr()) == SVR_P2040
)
268 size
= (l2cfg0
& 0x3fff) * 64 * 1024;
269 num_ways
= ((l2cfg0
>> 14) & 0x1f) + 1;
270 line_size
= (((l2cfg0
>> 23) & 0x3) + 1) * 32;
271 num_sets
= size
/ (line_size
* num_ways
);
273 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
275 while (off
!= -FDT_ERR_NOTFOUND
) {
276 ph
= (u32
*)fdt_getprop(blob
, off
, "next-level-cache", 0);
279 debug("no next-level-cache property\n");
283 l2_off
= fdt_node_offset_by_phandle(blob
, *ph
);
285 printf("%s: %s\n", __func__
, fdt_strerror(off
));
290 #ifdef CONFIG_SYS_CACHE_STASHING
291 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
292 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
293 /* Only initialize every eighth thread */
294 if (reg
&& !((*reg
) % 8))
298 fdt_setprop_cell(blob
, l2_off
, "cache-stash-id",
299 (*reg
* 2) + 32 + 1);
302 fdt_setprop(blob
, l2_off
, "cache-unified", NULL
, 0);
303 fdt_setprop_cell(blob
, l2_off
, "cache-block-size",
305 fdt_setprop_cell(blob
, l2_off
, "cache-size", size
);
306 fdt_setprop_cell(blob
, l2_off
, "cache-sets", num_sets
);
307 fdt_setprop_cell(blob
, l2_off
, "cache-level", 2);
308 fdt_setprop(blob
, l2_off
, "compatible", "cache", 6);
312 ph
= (u32
*)fdt_getprop(blob
, l2_off
, "next-level-cache", 0);
315 debug("no next-level-cache property\n");
321 off
= fdt_node_offset_by_prop_value(blob
, off
,
322 "device_type", "cpu", 4);
325 l3_off
= fdt_node_offset_by_phandle(blob
, l3_off
);
327 printf("%s: %s\n", __func__
, fdt_strerror(off
));
330 ft_fixup_l3cache(blob
, l3_off
);
334 #define ft_fixup_l2cache(x)
337 static inline void ft_fixup_cache(void *blob
)
341 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
343 while (off
!= -FDT_ERR_NOTFOUND
) {
344 u32 l1cfg0
= mfspr(SPRN_L1CFG0
);
345 u32 l1cfg1
= mfspr(SPRN_L1CFG1
);
346 u32 isize
, iline_size
, inum_sets
, inum_ways
;
347 u32 dsize
, dline_size
, dnum_sets
, dnum_ways
;
350 dsize
= (l1cfg0
& 0x7ff) * 1024;
351 dnum_ways
= ((l1cfg0
>> 11) & 0xff) + 1;
352 dline_size
= (((l1cfg0
>> 23) & 0x3) + 1) * 32;
353 dnum_sets
= dsize
/ (dline_size
* dnum_ways
);
355 fdt_setprop_cell(blob
, off
, "d-cache-block-size", dline_size
);
356 fdt_setprop_cell(blob
, off
, "d-cache-size", dsize
);
357 fdt_setprop_cell(blob
, off
, "d-cache-sets", dnum_sets
);
359 #ifdef CONFIG_SYS_CACHE_STASHING
361 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
363 fdt_setprop_cell(blob
, off
, "cache-stash-id",
364 (*reg
* 2) + 32 + 0);
369 isize
= (l1cfg1
& 0x7ff) * 1024;
370 inum_ways
= ((l1cfg1
>> 11) & 0xff) + 1;
371 iline_size
= (((l1cfg1
>> 23) & 0x3) + 1) * 32;
372 inum_sets
= isize
/ (iline_size
* inum_ways
);
374 fdt_setprop_cell(blob
, off
, "i-cache-block-size", iline_size
);
375 fdt_setprop_cell(blob
, off
, "i-cache-size", isize
);
376 fdt_setprop_cell(blob
, off
, "i-cache-sets", inum_sets
);
378 off
= fdt_node_offset_by_prop_value(blob
, off
,
379 "device_type", "cpu", 4);
382 ft_fixup_l2cache(blob
);
386 void fdt_add_enet_stashing(void *fdt
)
388 do_fixup_by_compat(fdt
, "gianfar", "bd-stash", NULL
, 0, 1);
390 do_fixup_by_compat_u32(fdt
, "gianfar", "rx-stash-len", 96, 1);
392 do_fixup_by_compat_u32(fdt
, "gianfar", "rx-stash-idx", 0, 1);
393 do_fixup_by_compat(fdt
, "fsl,etsec2", "bd-stash", NULL
, 0, 1);
394 do_fixup_by_compat_u32(fdt
, "fsl,etsec2", "rx-stash-len", 96, 1);
395 do_fixup_by_compat_u32(fdt
, "fsl,etsec2", "rx-stash-idx", 0, 1);
398 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
399 #ifdef CONFIG_SYS_DPAA_FMAN
400 static void ft_fixup_clks(void *blob
, const char *compat
, u32 offset
,
403 phys_addr_t phys
= offset
+ CONFIG_SYS_CCSRBAR_PHYS
;
404 int off
= fdt_node_offset_by_compat_reg(blob
, compat
, phys
);
407 off
= fdt_setprop_cell(blob
, off
, "clock-frequency", freq
);
409 printf("WARNING enable to set clock-frequency "
410 "for %s: %s\n", compat
, fdt_strerror(off
));
415 static void ft_fixup_dpaa_clks(void *blob
)
419 get_sys_info(&sysinfo
);
420 #ifdef CONFIG_SYS_DPAA_FMAN
421 ft_fixup_clks(blob
, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET
,
422 sysinfo
.freqFMan
[0]);
424 #if (CONFIG_SYS_NUM_FMAN == 2)
425 ft_fixup_clks(blob
, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET
,
426 sysinfo
.freqFMan
[1]);
430 #ifdef CONFIG_SYS_DPAA_QBMAN
431 do_fixup_by_compat_u32(blob
, "fsl,qman",
432 "clock-frequency", sysinfo
.freqQMAN
, 1);
435 #ifdef CONFIG_SYS_DPAA_PME
436 do_fixup_by_compat_u32(blob
, "fsl,pme",
437 "clock-frequency", sysinfo
.freqPME
, 1);
441 #define ft_fixup_dpaa_clks(x)
445 static void ft_fixup_qe_snum(void *blob
)
449 svr
= mfspr(SPRN_SVR
);
450 if (SVR_SOC_VER(svr
) == SVR_8569
) {
451 if(IS_SVR_REV(svr
, 1, 0))
452 do_fixup_by_compat_u32(blob
, "fsl,qe",
453 "fsl,qe-num-snums", 46, 1);
455 do_fixup_by_compat_u32(blob
, "fsl,qe",
456 "fsl,qe-num-snums", 76, 1);
462 * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree
464 * The binding for an Fman firmware node is documented in
465 * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains
466 * the actual Fman firmware binary data. The operating system is expected to
467 * be able to parse the binary data to determine any attributes it needs.
469 #ifdef CONFIG_SYS_DPAA_FMAN
470 void fdt_fixup_fman_firmware(void *blob
)
472 int rc
, fmnode
, fwnode
= -1;
474 struct qe_firmware
*fmanfw
;
475 const struct qe_header
*hdr
;
480 /* The first Fman we find will contain the actual firmware. */
481 fmnode
= fdt_node_offset_by_compatible(blob
, -1, "fsl,fman");
483 /* Exit silently if there are no Fman devices */
486 /* If we already have a firmware node, then also exit silently. */
487 if (fdt_node_offset_by_compatible(blob
, -1, "fsl,fman-firmware") > 0)
490 /* If the environment variable is not set, then exit silently */
491 p
= getenv("fman_ucode");
495 fmanfw
= (struct qe_firmware
*) simple_strtoul(p
, NULL
, 0);
499 hdr
= &fmanfw
->header
;
500 length
= be32_to_cpu(hdr
->length
);
502 /* Verify the firmware. */
503 if ((hdr
->magic
[0] != 'Q') || (hdr
->magic
[1] != 'E') ||
504 (hdr
->magic
[2] != 'F')) {
505 printf("Data at %p is not an Fman firmware\n", fmanfw
);
509 if (length
> CONFIG_SYS_QE_FMAN_FW_LENGTH
) {
510 printf("Fman firmware at %p is too large (size=%u)\n",
515 length
-= sizeof(u32
); /* Subtract the size of the CRC */
516 crc
= be32_to_cpu(*(u32
*)((void *)fmanfw
+ length
));
517 if (crc
!= crc32_no_comp(0, (void *)fmanfw
, length
)) {
518 printf("Fman firmware at %p has invalid CRC\n", fmanfw
);
522 /* Increase the size of the fdt to make room for the node. */
523 rc
= fdt_increase_size(blob
, fmanfw
->header
.length
);
525 printf("Unable to make room for Fman firmware: %s\n",
530 /* Create the firmware node. */
531 fwnode
= fdt_add_subnode(blob
, fmnode
, "fman-firmware");
534 fdt_get_path(blob
, fmnode
, s
, sizeof(s
));
535 printf("Could not add firmware node to %s: %s\n", s
,
536 fdt_strerror(fwnode
));
539 rc
= fdt_setprop_string(blob
, fwnode
, "compatible", "fsl,fman-firmware");
542 fdt_get_path(blob
, fwnode
, s
, sizeof(s
));
543 printf("Could not add compatible property to node %s: %s\n", s
,
547 phandle
= fdt_create_phandle(blob
, fwnode
);
550 fdt_get_path(blob
, fwnode
, s
, sizeof(s
));
551 printf("Could not add phandle property to node %s: %s\n", s
,
555 rc
= fdt_setprop(blob
, fwnode
, "fsl,firmware", fmanfw
, fmanfw
->header
.length
);
558 fdt_get_path(blob
, fwnode
, s
, sizeof(s
));
559 printf("Could not add firmware property to node %s: %s\n", s
,
564 /* Find all other Fman nodes and point them to the firmware node. */
565 while ((fmnode
= fdt_node_offset_by_compatible(blob
, fmnode
, "fsl,fman")) > 0) {
566 rc
= fdt_setprop_cell(blob
, fmnode
, "fsl,firmware-phandle", phandle
);
569 fdt_get_path(blob
, fmnode
, s
, sizeof(s
));
570 printf("Could not add pointer property to node %s: %s\n",
571 s
, fdt_strerror(rc
));
577 #define fdt_fixup_fman_firmware(x)
580 #if defined(CONFIG_PPC_P4080)
581 static void fdt_fixup_usb(void *fdt
)
583 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
584 u32 rcwsr11
= in_be32(&gur
->rcwsr
[11]);
587 off
= fdt_node_offset_by_compatible(fdt
, -1, "fsl,mpc85xx-usb2-mph");
588 if ((rcwsr11
& FSL_CORENET_RCWSR11_EC1
) !=
589 FSL_CORENET_RCWSR11_EC1_FM1_USB1
)
590 fdt_status_disabled(fdt
, off
);
592 off
= fdt_node_offset_by_compatible(fdt
, -1, "fsl,mpc85xx-usb2-dr");
593 if ((rcwsr11
& FSL_CORENET_RCWSR11_EC2
) !=
594 FSL_CORENET_RCWSR11_EC2_USB2
)
595 fdt_status_disabled(fdt
, off
);
598 #define fdt_fixup_usb(x)
601 void ft_cpu_setup(void *blob
, bd_t
*bd
)
607 /* delete crypto node if not on an E-processor */
608 if (!IS_E_PROCESSOR(get_svr()))
609 fdt_fixup_crypto_node(blob
, 0);
610 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
612 ccsr_sec_t __iomem
*sec
;
614 sec
= (void __iomem
*)CONFIG_SYS_FSL_SEC_ADDR
;
615 fdt_fixup_crypto_node(blob
, in_be32(&sec
->secvid_ms
));
619 fdt_fixup_ethernet(blob
);
621 fdt_add_enet_stashing(blob
);
623 do_fixup_by_prop_u32(blob
, "device_type", "cpu", 4,
624 "timebase-frequency", get_tbclk(), 1);
625 do_fixup_by_prop_u32(blob
, "device_type", "cpu", 4,
626 "bus-frequency", bd
->bi_busfreq
, 1);
627 get_sys_info(&sysinfo
);
628 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
629 while (off
!= -FDT_ERR_NOTFOUND
) {
630 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
631 val
= cpu_to_fdt32(sysinfo
.freqProcessor
[*reg
]);
632 fdt_setprop(blob
, off
, "clock-frequency", &val
, 4);
633 off
= fdt_node_offset_by_prop_value(blob
, off
, "device_type",
636 do_fixup_by_prop_u32(blob
, "device_type", "soc", 4,
637 "bus-frequency", bd
->bi_busfreq
, 1);
639 do_fixup_by_compat_u32(blob
, "fsl,pq3-localbus",
640 "bus-frequency", gd
->arch
.lbc_clk
, 1);
641 do_fixup_by_compat_u32(blob
, "fsl,elbc",
642 "bus-frequency", gd
->arch
.lbc_clk
, 1);
645 ft_fixup_qe_snum(blob
);
648 fdt_fixup_fman_firmware(blob
);
650 #ifdef CONFIG_SYS_NS16550
651 do_fixup_by_compat_u32(blob
, "ns16550",
652 "clock-frequency", CONFIG_SYS_NS16550_CLK
, 1);
656 do_fixup_by_compat_u32(blob
, "fsl,cpm2-scc-uart",
657 "current-speed", bd
->bi_baudrate
, 1);
659 do_fixup_by_compat_u32(blob
, "fsl,cpm2-brg",
660 "clock-frequency", bd
->bi_brgfreq
, 1);
663 #ifdef CONFIG_FSL_CORENET
664 do_fixup_by_compat_u32(blob
, "fsl,qoriq-clockgen-1.0",
665 "clock-frequency", CONFIG_SYS_CLK_FREQ
, 1);
666 do_fixup_by_compat_u32(blob
, "fsl,mpic",
667 "clock-frequency", get_bus_freq(0)/2, 1);
669 do_fixup_by_compat_u32(blob
, "fsl,mpic",
670 "clock-frequency", get_bus_freq(0), 1);
673 fdt_fixup_memory(blob
, (u64
)bd
->bi_memstart
, (u64
)bd
->bi_memsize
);
676 ft_fixup_cpu(blob
, (u64
)bd
->bi_memstart
+ (u64
)bd
->bi_memsize
);
677 ft_fixup_num_cores(blob
);
680 ft_fixup_cache(blob
);
682 #if defined(CONFIG_FSL_ESDHC)
683 fdt_fixup_esdhc(blob
, bd
);
686 ft_fixup_dpaa_clks(blob
);
688 #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
689 fdt_portal(blob
, "fsl,bman-portal", "bman-portals",
690 (u64
)CONFIG_SYS_BMAN_MEM_PHYS
,
691 CONFIG_SYS_BMAN_MEM_SIZE
);
692 fdt_fixup_bportals(blob
);
695 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
696 fdt_portal(blob
, "fsl,qman-portal", "qman-portals",
697 (u64
)CONFIG_SYS_QMAN_MEM_PHYS
,
698 CONFIG_SYS_QMAN_MEM_SIZE
);
700 fdt_fixup_qportals(blob
);
703 #ifdef CONFIG_SYS_SRIO
708 * system-clock = CCB clock/2
709 * Here gd->bus_clk = CCB clock
710 * We are using the system clock as 1588 Timer reference
711 * clock source select
713 do_fixup_by_compat_u32(blob
, "fsl,gianfar-ptp-timer",
714 "timer-frequency", gd
->bus_clk
/2, 1);
717 * clock-freq should change to clock-frequency and
718 * flexcan-v1.0 should change to p1010-flexcan respectively
721 do_fixup_by_compat_u32(blob
, "fsl,flexcan-v1.0",
722 "clock_freq", gd
->bus_clk
/2, 1);
724 do_fixup_by_compat_u32(blob
, "fsl,flexcan-v1.0",
725 "clock-frequency", gd
->bus_clk
/2, 1);
727 do_fixup_by_compat_u32(blob
, "fsl,p1010-flexcan",
728 "clock-frequency", gd
->bus_clk
/2, 1);
734 * For some CCSR devices, we only have the virtual address, not the physical
735 * address. This is because we map CCSR as a whole, so we typically don't need
736 * a macro for the physical address of any device within CCSR. In this case,
737 * we calculate the physical address of that device using it's the difference
738 * between the virtual address of the device and the virtual address of the
741 #define CCSR_VIRT_TO_PHYS(x) \
742 (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
744 static void msg(const char *name
, uint64_t uaddr
, uint64_t daddr
)
746 printf("Warning: U-Boot configured %s at address %llx,\n"
747 "but the device tree has it at %llx\n", name
, uaddr
, daddr
);
751 * Verify the device tree
753 * This function compares several CONFIG_xxx macros that contain physical
754 * addresses with the corresponding nodes in the device tree, to see if
755 * the physical addresses are all correct. For example, if
756 * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
757 * of the first UART. We convert this to a physical address and compare
758 * that with the physical address of the first ns16550-compatible node
759 * in the device tree. If they don't match, then we display a warning.
761 * Returns 1 on success, 0 on failure
763 int ft_verify_fdt(void *fdt
)
769 /* First check the CCSR base address */
770 off
= fdt_node_offset_by_prop_value(fdt
, -1, "device_type", "soc", 4);
772 addr
= fdt_get_base_address(fdt
, off
);
775 printf("Warning: could not determine base CCSR address in "
777 /* No point in checking anything else */
781 if (addr
!= CONFIG_SYS_CCSRBAR_PHYS
) {
782 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS
, addr
);
783 /* No point in checking anything else */
788 * Check some nodes via aliases. We assume that U-Boot and the device
789 * tree enumerate the devices equally. E.g. the first serial port in
790 * U-Boot is the same as "serial0" in the device tree.
792 aliases
= fdt_path_offset(fdt
, "/aliases");
794 #ifdef CONFIG_SYS_NS16550_COM1
795 if (!fdt_verify_alias_address(fdt
, aliases
, "serial0",
796 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1
)))
800 #ifdef CONFIG_SYS_NS16550_COM2
801 if (!fdt_verify_alias_address(fdt
, aliases
, "serial1",
802 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2
)))
808 * The localbus node is typically a root node, even though the lbc
809 * controller is part of CCSR. If we were to put the lbc node under
810 * the SOC node, then the 'ranges' property in the lbc node would
811 * translate through the 'ranges' property of the parent SOC node, and
812 * we don't want that. Since it's a separate node, it's possible for
813 * the 'reg' property to be wrong, so check it here. For now, we
814 * only check for "fsl,elbc" nodes.
816 #ifdef CONFIG_SYS_LBC_ADDR
817 off
= fdt_node_offset_by_compatible(fdt
, -1, "fsl,elbc");
819 const fdt32_t
*reg
= fdt_getprop(fdt
, off
, "reg", NULL
);
821 uint64_t uaddr
= CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR
);
823 addr
= fdt_translate_address(fdt
, off
, reg
);
825 msg("the localbus", uaddr
, addr
);